// TrkNextInstructionAfterPC.cpp

// 

// Copyright (c) 2010 Accenture. All rights reserved.

// This component and the accompanying materials are made available

// under the terms of the "Eclipse Public License v1.0"

// which accompanies this distribution, and is available

// at the URL "http://www.eclipse.org/legal/epl-v10.html".

// 

// Initial Contributors:

// Accenture - Initial contribution

//

#include "fdebuggerkernel.h"

//BEGIN TOMSCI

#include <kernel/arm/arm.h>

#define LOG_MSG(x)

#define LOG_MSG2(x,y)

#define LOG_MSG3(x,y,z)

#define iChannel this // Saves rewriting a whole load

#define ReturnIfError(x) { TInt y = (x); if (KErrNone != y) return y; }

#ifdef ASSERT

#undef ASSERT

#endif

#ifdef __WINS__

#define ASSERT(x) __ASSERT_ALWAYS((x), Kern::Fault("TRKNIAPC Assertion failed: " #x, __LINE__))

#else

#define ASSERT(x) if (!(x)) { Kern::Printf("TRKNIAPC Assertion failed @ %d: " #x, __LINE__); NKern::Sleep(NKern::TimerTicks(5000)); }

#endif

TInt DDebuggerEventHandler::ReadKernelRegisterValue(DThread* aThread, TInt aRegister, TUint32& aResult)

	{

	TUint32 regs[32];

	TUint32 valid = 0;

	NKern::ThreadGetUserContext(&aThread->iNThread, &regs[0], valid);

	if (valid & (1<<aRegister))

		{

		aResult = regs[aRegister];

		return KErrNone;

		}

	else

		{

		return KErrNotSupported;

		}

	}

TInt DDebuggerEventHandler::DoReadMemory(DThread* aThread, TLinAddr aAddress, TInt aLength, TDes8& aResult)

	{

	// First check if this address is something we've overwritten with a software breakpoint - if so, return the stored value instead

	ASSERT(aLength == 4 || aLength == 2);

	if (aResult.MaxLength() < aLength) return KErrArgument;

	// Check for a breakpoint covering this region

	SBreakpoint* b = FindBreakpointByAddress(aAddress & ~1);

	if (b && b->iOrigInstruction.Length() > 0)

		{

		ASSERT(b->iOrigInstruction.Length() == aLength); // Otherwise we've trying to read an ARM instruction from somewhere we have a thumb breakpoint (or vice versa)

		aResult.Copy(b->iOrigInstruction);

		return KErrNone;

		}

	TInt err = Kern::ThreadRawRead(aThread, (void*)aAddress, (void*)aResult.Ptr(), aLength);

	if (err == KErrNone) aResult.SetLength(aLength);

	return err;

	}

namespace Debug {

	enum TArchitectureMode

	{

	/** Represents the ARM CPU architecture. */

	EArmMode = 1,

	/** Represents the Thumb CPU architecture. */

	EThumbMode = 2,

	/**

	  Represents the Thumb2 CPU architecture.

	  @prototype

	  */

	EThumb2EEMode = 3

	};

}

using namespace Debug;

typedef TUint32 T4ByteRegisterValue;

//END TOMSCI

// Register definitions

#define SP_REGISTER			13

#define LINK_REGISTER		14

#define PC_REGISTER			15

#define STATUS_REGISTER		16

/*

// ARM instruction bitmasks

#define ARM_OPCODE(x)		(((TUint32)(x) & 0x0E000000) >> 25)

// Generic instruction defines

#define ARM_RM(x)				((TUint32)(x) & 0x0000000F)			// bit 0- 4

#define ARM_RS(x)				(((TUint32)(x) & 0x00000F00) >> 8)	// bit 8-11

#define ARM_RD(x)				(((TUint32)(x) & 0x0000F000) >> 12)	// bit 12-15

#define ARM_RN(x)				(((TUint32)(x) & 0x000F0000) >> 16)	// bit 16-19

#define ARM_LOAD(x)				(((TUint32)(x) & 0x00100000) >> 20)	// bit 20

// Data processing instruction defines

#define ARM_DATA_SHIFT(x)		(((TUint32)(x) & 0x00000060) >> 5) 	// bit 5- 6

#define ARM_DATA_C(x)			(((TUint32)(x) & 0x00000F80) >> 7) 	// bit 7-11

#define ARM_DATA_IMM(x)			((TUint32)(x) & 0x000000FF)			// bit 0-7

#define ARM_DATA_ROT(x)			(((TUint32)(x) & 0x00000F00) >> 8) 	// bit 8-11

// Single date transfer instruction defines

#define ARM_SINGLE_IMM(x)		((TUint32)(x) & 0x00000FFF)			// bit 0-11

#define ARM_SINGLE_BYTE(x)		(((TUint32)(x) & 0x00400000) >> 22)	// bit 22

#define ARM_SINGLE_U(x)			(((TUint32)(x) & 0x00800000) >> 23)	// bit 23

#define ARM_SINGLE_PRE(x)		(((TUint32)(x) & 0x01000000) >> 24)	// bit 24

// Block data transfer instruction defines

#define ARM_BLOCK_REGLIST(x)	((TUint32)(x) & 0x0000FFFF)		// bit 0-15

#define ARM_BLOCK_U(x)			(((TUint32)(x) & 0x00800000) >> 23)	// bit 23

#define ARM_BLOCK_PRE(x)		(((TUint32)(x) & 0x01000000) >> 24)	// bit 24

// Branch instruction defines

#define ARM_B_ADDR(x)			((x & 0x00800000) ? ((TUint32)(x) & 0x00FFFFFF | 0xFF000000) : (TUint32)(x) & 0x00FFFFFF)

#define ARM_INSTR_B_DEST(x,a)	(ARM_B_ADDR(x) << 2) + ((TUint32)(a) + 8)

#define ARM_CARRY_BIT			0x20000000	// bit 30

// Thumb instruction bitmasks

#define THUMB_OPCODE(x)		(((TUint16)(x) & 0xF800) >> 11)

#define THUMB_INST_7_15(x)	(((TUint16)(x) & 0xFF80) >> 7)

#define THUMB_INST_8_15(x)	(((TUint16)(x) & 0xFF00) >> 8)

*/

TUint32 IsBitSet(const TUint32 aBitset, const TUint8 aNum)

	{

	return (aBitset & (1 << aNum) );

	}

// 

// BitCount

//

// Count number of bits in aVal

TUint32 BitCount(const TUint32 aVal)

	{

	TUint32 num = 0;

	for(TInt i = 0; i < 32; i++)

		{

		if ((1 << i) & aVal)

			{

			num++;

			}

		}

	return num;

	}

//

// Thumb2 opcode decoding

//

// Special data instructions and branch and exchange.

//

// Returns Opcode as defined in ARM ARM DDI0406A, section A6.2.3

TUint16 t2opcode16special(const TUint16 aInst)

	{

	TUint8 aVal = (aInst & 0x03C0) >> 5;

	return aVal;

	}

// Thumb2 opcode decoding instructions

// 

// Returns Opcode as defined in ARM ARM DDI0406A, section A6.2

// 16-bit Thumb instruction encoding

TUint16 t2opcode16(const TUint16 aInst)

{

	TUint16 aVal = (aInst & 0xFC00) >> 9;

	return aVal;

}

// ARM opcode decoding functions

TUint32 arm_opcode(const TUint32 aInst)

{

// #define ARM_OPCODE(x)		(((TUint32)(x) & 0x0E000000) >> 25)

	TUint32 aVal = ((aInst) & 0x0E000000) >> 25;

	return aVal;

}

TUint32  arm_rm(const TUint32 aInst)

{

//#define ARM_RM(x)				((TUint32)(x) & 0x0000000F)			// bit 0- 4

	TUint32 aVal = (aInst) & 0x0000000F;

	return aVal;

}

TUint32  arm_rs(const TUint32 aInst)

{

//#define ARM_RS(x)				(((TUint32)(x) & 0x00000F00) >> 8)	// bit 8-11

	TUint32 aVal = ((aInst) & 0x00000F00) >> 8;

	return aVal;

}

TUint32  arm_rd(const TUint32 aInst)

{

//#define ARM_RD(x)				(((TUint32)(x) & 0x0000F000) >> 12)	// bit 12-15

	TUint32 aVal = ((aInst) & 0x0000F000) >> 12;

	return aVal;

}

TUint32  arm_rn(const TUint32 aInst)

{

//#define ARM_RN(x)				(((TUint32)(x) & 0x000F0000) >> 16)	// bit 16-19

	TUint32 aVal = ((aInst) & 0x000F0000) >> 16;

	return aVal;

}

TUint32 arm_load(const TUint32 aInst)

{

//#define ARM_LOAD(x)				(((TUint32)(x) & 0x00100000) >> 20)	// bit 20

	TUint32 aVal = ((aInst) & 0x00100000) >> 20;

	return aVal;

}

// Data processing instruction defines

TUint32 arm_data_shift(const TUint32 aInst)

{

//#define ARM_DATA_SHIFT(x)		(((TUint32)(x) & 0x00000060) >> 5) 	// bit 5- 6

	TUint32 aVal = ((aInst) & 0x00000060) >> 5;

	return aVal;

}

TUint32 arm_data_c(const TUint32 aInst)

{

//#define ARM_DATA_C(x)			(((TUint32)(x) & 0x00000F80) >> 7) 	// bit 7-11

	TUint32 aVal = ((aInst) & 0x00000F80) >> 7;

	return aVal;

}

TUint32 arm_data_imm(const TUint32 aInst)

{

//#define ARM_DATA_IMM(x)			((TUint32)(x) & 0x000000FF)			// bit 0-7

	TUint32 aVal = (aInst) & 0x000000FF;

	return aVal;

}

TUint32 arm_data_rot(const TUint32 aInst)

{

//#define ARM_DATA_ROT(x)			(((TUint32)(x) & 0x00000F00) >> 8) 	// bit 8-11

	TUint32 aVal = ((aInst) & 0x00000F00) >> 8;

	return aVal;

}

// Single date transfer instruction defines

TUint32 arm_single_imm(const TUint32 aInst)

{

//#define ARM_SINGLE_IMM(x)		((TUint32)(x) & 0x00000FFF)			// bit 0-11

	TUint32 aVal = (aInst) & 0x00000FFF;

	return aVal;

}

TUint32 arm_single_byte(const TUint32 aInst)

{

//#define ARM_SINGLE_BYTE(x)		(((TUint32)(x) & 0x00400000) >> 22)	// bit 22

	TUint32 aVal = ((aInst) & 0x00400000) >> 22;

	return aVal;

}

TUint32 arm_single_u(const TUint32 aInst)

{

//#define ARM_SINGLE_U(x)			(((TUint32)(x) & 0x00800000) >> 23)	// bit 23

	TUint32 aVal = ((aInst) & 0x00800000) >> 23;

	return aVal;

}

TUint32 arm_single_pre(const TUint32 aInst)

{

//#define ARM_SINGLE_PRE(x)		(((TUint32)(x) & 0x01000000) >> 24)	// bit 24

	TUint32 aVal = ((aInst) & 0x01000000) >> 24;

	return aVal;

}

// Block data transfer instruction defines

TUint32 arm_block_reglist(const TUint32 aInst)

{

//#define ARM_BLOCK_REGLIST(x)	((TUint32)(x) & 0x0000FFFF)		// bit 0-15

	TUint32 aVal = (aInst) & 0x0000FFFF;

	return aVal;

}

TUint32 arm_block_u(const TUint32 aInst)

{

//#define ARM_BLOCK_U(x)			(((TUint32)(x) & 0x00800000) >> 23)	// bit 23

	TUint32 aVal = ((aInst) & 0x00800000) >> 23;

	return aVal;

}

TUint32 arm_block_pre(const TUint32 aInst)

{

//#define ARM_BLOCK_PRE(x)		(((TUint32)(x) & 0x01000000) >> 24)	// bit 24

	TUint32 aVal = ((aInst) & 0x01000000) >> 24;

	return aVal;

}

// Branch instruction defines

TUint32 arm_b_addr(const TUint32 aInst)

{

//#define ARM_B_ADDR(x)			((x & 0x00800000) ? ((TUint32)(x) & 0x00FFFFFF | 0xFF000000) : (TUint32)(x) & 0x00FFFFFF)

	TUint32 aVal = ((aInst & 0x00800000) ? ((TUint32)(aInst) & 0x00FFFFFF | 0xFF000000) : (TUint32)(aInst) & 0x00FFFFFF);

	return aVal;

}

TUint32 arm_instr_b_dest(const TUint32 aInst, TUint32& aAddress)

{

//#define ARM_INSTR_B_DEST(x,a)	(ARM_B_ADDR(x) << 2) + ((TUint32)(a) + 8)

	TUint32 aVal = (arm_b_addr(aInst) << 2) + ((TUint32)(aAddress) + 8);

	return aVal;

}

TUint32 thumb_b_addr(const TUint32 aInst)

{

//#define THUMB_B_ADDR(x) ((x & 0x0400) ? ((((TUint32)(x) & 0x07FF)<<11) | (((TUint32)(x) & 0x07FF0000)>>16) | 0xFFC00000) :\

                                            ((TUint32)(x) & 0x07FF)<<11) | (((TUint32)(x) & 0x07FF0000)>>16)

	TUint32 aVal = ((((TUint32)(aInst) & 0x07FF)<<11) | ((TUint32)(aInst) & 0x07FF0000)>>16);

	return ((aInst & 0x0400) ? (aVal | 0xFFC00000) : aVal);

}

TUint32 thumb_instr_b_dest(const TUint32 aInst, TUint32& aAddress)

{

//#define THUMB_INSTR_B_DEST(x,a)	(THUMB_B_ADDR(x) << 1) + ((TUint32)(a) + 4)

	TUint32 aVal = (thumb_b_addr(aInst) << 1) + ((TUint32)(aAddress) + 4);

	return aVal;

}

TUint32 arm_carry_bit(void)

{

//#define ARM_CARRY_BIT			0x20000000	// bit 30

	TUint32 aVal = 0x20000000;

	return aVal;

}

// Thumb instruction bitmasks

TUint16 thumb_opcode(const TUint16 aInst)

{

//	#define THUMB_OPCODE(x)		(((TUint16)(x) & 0xF800) >> 11)

	TUint16 aVal = ((aInst) & 0xF800) >> 11;

	return aVal;

}

TUint16 thumb_inst_7_15(const TUint16 aInst)

{

//	#define THUMB_INST_7_15(x)	(((TUint16)(x) & 0xFF80) >> 7)

	TUint16 aVal = ((aInst) & 0xFF80) >> 7;

	return aVal;

}

TUint16 thumb_inst_8_15(const TUint16 aInst)

{

//	#define THUMB_INST_8_15(x)	(((TUint16)(x) & 0xFF00) >> 8)

	TUint16 aVal = ((aInst) & 0xFF00) >> 8;

	return aVal;

}

TBool IsExecuted(TUint8 aCondition ,TUint32 aStatusRegister)

{

	LOG_MSG("DRMDStepping::IsExecuted()");

	TBool N = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000008;

	TBool Z = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000004;

	TBool C = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000002;

	TBool V = ((aStatusRegister >> 28) & 0x0000000F) & 0x00000001;

	switch(aCondition)

	{

		case 0:

			return Z;

		case 1:

			return !Z;

		case 2:

			return C;

		case 3:

			return !C;

		case 4:

			return N;

		case 5:

			return !N;

		case 6:

			return V;

		case 7:

			return !V;

		case 8:

			return (C && !Z);

		case 9:

			return (!C || Z);

		case 10:

			return (N == V);

		case 11:

			return (N != V);

		case 12:

			return ((N == V) && !Z);

		case 13:

			return (Z || (N != V));

		case 14:

		case 15:

			return ETrue;

	}

	return EFalse;

}

TBool DDebuggerEventHandler::IsPreviousInstructionMovePCToLR(DThread *aThread)

{

	TInt err = KErrNone;

	// there are several types of instructions that modify the PC that aren't

	// designated as linked or non linked branches.  the way gcc generates the

	// code can tell us whether or not these instructions are to be treated as

	// linked branches.  the main cases are bx and any type of mov or load or

	// arithmatic operation that changes the PC.  if these are really just

	// function calls that will return, gcc will generate a mov	lr, pc

	// instruction as the previous instruction.  note that this is just for arm

	// and armi

	// get the address of the previous instruction

	TUint32 address = 0;

	//err = iChannel->ReadKernelRegisterValue(aThread, PC_REGISTER, address);

	err = ReadKernelRegisterValue(aThread, PC_REGISTER, address);

	if(err != KErrNone)

	{

		LOG_MSG2("Non-zero error code discarded: %d", err);

	}

	address -= 4;

	TBuf8<4> previousInstruction;

	err = DoReadMemory(aThread, address, 4, previousInstruction);

	if (KErrNone != err)

	{

		LOG_MSG2("Error %d reading memory at address %x", address);

		return EFalse;

	}

	const TUint32 movePCToLRIgnoringCondition = 0x01A0E00F;

	TUint32 inst = *(TUint32 *)previousInstruction.Ptr();

	if ((inst & 0x0FFFFFFF) == movePCToLRIgnoringCondition)

	{

		return ETrue;

	}

	return EFalse;

}

void DecodeDataProcessingInstruction(TUint8 aOpcode, TUint32 aOp1, TUint32 aOp2, TUint32 aStatusRegister, TUint32 &aBreakAddress)

{

	LOG_MSG("DRMDStepping::DecodeDataProcessingInstruction()");

	switch(aOpcode)

	{

		case 0:

		{

			// AND

			aBreakAddress = aOp1 & aOp2;

			break;

		}

		case 1:

		{

			// EOR

			aBreakAddress = aOp1 ^ aOp2;

			break;

		}

		case 2:

		{

			// SUB

			aBreakAddress = aOp1 - aOp2;