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1 // hwbreak.cia |
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2 // |
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3 // Copyright (c) 2010 Accenture. All rights reserved. |
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4 // This component and the accompanying materials are made available |
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5 // under the terms of the "Eclipse Public License v1.0" |
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6 // which accompanies this distribution, and is available |
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7 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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8 // |
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9 // Initial Contributors: |
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10 // Accenture - Initial contribution |
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11 // |
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12 #include <fshell/common.mmh> |
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13 #include <u32std.h> |
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14 |
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15 #define READ_BCR(cond, n, resultreg) asm("MRC"#cond" p14,0,"#resultreg",c0,c"#n",5") |
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16 #define WRITE_BCR(n, valuereg) asm("MCR p14,0,"#valuereg",c0,c"#n",5") |
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17 #define WRITE_BVR(n, valuereg) asm("MCR p14,0,"#valuereg",c0,c"#n",4") |
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18 |
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19 #ifdef __GCCE__ |
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20 #ifdef __NAKED__ |
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21 #undef __NAKED__ |
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22 #endif |
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23 #define __NAKED__ __attribute__((__naked__)) |
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24 #endif |
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25 |
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26 __NAKED__ void MCR_SetContextIdBrp(TInt /*aRegister*/, TUint /*aContextId*/) |
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27 { |
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28 asm("ldr r2, KContextIdBCR"); |
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29 |
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30 // Use BVR 4 or 5 as appropriate |
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31 asm("cmp r0, #4"); |
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32 asm("beq usefour"); |
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33 |
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34 // otherwise use 5 |
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35 WRITE_BVR(5, r1); |
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36 WRITE_BCR(5, r2); |
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37 asm("b contextdone"); |
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38 |
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39 asm("usefour:"); |
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40 WRITE_BVR(4, r1); |
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41 WRITE_BCR(4, r2); |
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42 |
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43 asm("contextdone:"); |
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44 __JUMP(,lr); |
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45 |
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46 // These are according to "ARM 13.3.9. CP14 c80-c85, Breakpoint Control Registers (BCR)" |
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47 asm("KContextIdBCR:"); |
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48 asm(".word 0x003001E7"); |
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49 } |
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50 |
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51 __NAKED__ TUint MRC_ReadBcr(TInt /*aRegister*/) |
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52 { |
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53 // Switch on aRegister |
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54 asm("cmp r0, #0"); |
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55 READ_BCR(eq, 0, r0); |
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56 __JUMP(eq, lr); |
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57 |
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58 asm("cmp r0, #1"); |
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59 READ_BCR(eq, 1, r0); |
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60 __JUMP(eq, lr); |
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61 |
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62 asm("cmp r0, #2"); |
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63 READ_BCR(eq, 2, r0); |
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64 __JUMP(eq, lr); |
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65 |
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66 asm("cmp r0, #3"); |
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67 READ_BCR(eq, 3, r0); |
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68 __JUMP(eq, lr); |
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69 |
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70 asm("cmp r0, #4"); |
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71 READ_BCR(eq, 4, r0); |
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72 __JUMP(eq, lr); |
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73 |
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74 asm("cmp r0, #5"); |
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75 READ_BCR(eq, 5, r0); |
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76 __JUMP(eq, lr); |
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77 |
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78 // Shouldn't get here, compiler shutter-upper |
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79 #ifdef __GCCE__ |
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80 return 0; |
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81 #else |
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82 __JUMP(, lr); |
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83 #endif |
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84 } |
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85 |
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86 __NAKED__ void MCR_SetBreakpointPair(TInt /*aRegister*/, TUint /*aBvrValue*/, TUint /*aBcrValue*/ ) |
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87 { |
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88 // Switch on aRegister |
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89 asm("cmp r0, #0"); |
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90 asm("beq zero"); |
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91 asm("cmp r0, #1"); |
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92 asm("beq one"); |
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93 asm("cmp r0, #2"); |
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94 asm("beq two"); |
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95 asm("cmp r0, #3"); |
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96 asm("beq three"); |
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97 |
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98 // If we reach here it's an error... |
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99 asm("b done"); |
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100 |
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101 asm("zero:"); |
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102 WRITE_BVR(0, r1); |
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103 WRITE_BCR(0, r2); |
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104 asm("b done"); |
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105 |
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106 asm("one:"); |
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107 WRITE_BVR(1, r1); |
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108 WRITE_BCR(1, r2); |
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109 asm("b done"); |
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110 |
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111 asm("two:"); |
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112 WRITE_BVR(2, r1); |
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113 WRITE_BCR(2, r2); |
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114 asm("b done"); |
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115 |
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116 asm("three:"); |
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117 WRITE_BVR(3, r1); |
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118 WRITE_BCR(4, r2); |
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119 asm("b done"); |
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120 |
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121 asm("done:"); |
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122 __JUMP(,lr); |
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123 } |
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124 |
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125 __NAKED__ TUint32 GetDscr() |
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126 { |
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127 asm("MRC p14,0,r0,c0,c1,0"); |
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128 __JUMP(,lr); |
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129 } |
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130 |
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131 __NAKED__ TUint32 GetDrar() |
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132 { |
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133 // Read Debug ROM Address Register |
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134 asm("MRC p14, 0, r0, c1, c0, 0"); |
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135 __JUMP(,lr); |
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136 } |
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137 |
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138 __NAKED__ TUint32 GetDsar() |
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139 { |
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140 // Read Debug Self Address Offset Register |
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141 asm("MRC p14, 0, r0, c2, c0, 0"); |
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142 __JUMP(,lr); |
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143 } |
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144 |
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145 __NAKED__ void MCR_SetDscr(TUint32 /*aVal*/) |
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146 { |
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147 asm("MCR p14,0,r0,c0,c1,0"); |
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148 __JUMP(,lr); |
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149 } |
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150 |
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151 __NAKED__ TUint32 GetContextId() |
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152 { |
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153 asm("MRC p15, 0, r0, c13, c0, 1"); |
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154 __JUMP(,lr); |
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155 } |
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156 |
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157 __NAKED__ void Dsb() |
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158 { |
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159 asm("Dsb:"); |
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160 // Data Sync Barrier |
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161 // From the various definitions of ARM_DSBxx in cpudefs.h |
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162 #if defined(FSHELL_ARM11XX_SUPPORT) |
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163 asm("mcr p15, 0, r0, c7, c10, 4 ") |
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164 #elif defined(FSHELL_ARM_MEM_MAPPED_DEBUG) |
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165 asm("nop"); // Shut up complaints about branches to non-code symbols |
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166 asm(".word %a0" : : "i" ((TInt)(0xf57ff04f))); |
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167 #endif |
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168 __JUMP(,lr); |
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169 } |
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170 |
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171 __NAKED__ void Isb() |
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172 { |
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173 asm("Isb:"); |
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174 // Instruction Sync Barrier |
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175 // From the various definitions of ARM_ISBxx in cpudefs.h |
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176 |
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177 #if defined(FSHELL_ARM11XX_SUPPORT) |
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178 asm("mcr p15, 0, r0, c7, c5, 4 ") |
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179 #elif defined(FSHELL_ARM_MEM_MAPPED_DEBUG) |
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180 asm("nop"); // Shut up complaints about branches to non-code symbols |
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181 asm(".word %a0" : : "i" ((TInt)(0xf57ff06f))); |
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182 #endif |
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183 __JUMP(,lr); |
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184 } |
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185 |
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186 __NAKED__ void Imb() |
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187 { |
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188 // Instruction Memory Barrier |
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189 asm("push {r14}"); |
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190 asm("bl Dsb"); |
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191 asm("bl Isb"); |
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192 asm("pop {r14}"); |
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193 __JUMP(,lr); |
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194 } |
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195 |
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196 |
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197 #if 0 |
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198 __NAKED__ void SetIvaBrp(TUint /*aAddress*/, TBool /*aUseContextIdFive*/, TInt /*aRegister*/ ) |
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199 { |
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200 asm("cmp r1, #0"); |
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201 // r3 gets the BCR value |
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202 asm("ldreq r3, KIvaBcrLinkedToFour"); |
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203 asm("ldrne r3, KIvaBcrLinkedToFive"); |
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204 asm("b DoSetIvaBrp"); // DoSetIvaBrp handles the return |
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205 |
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206 asm("KIvaBcrLinkedToFour:"); |
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207 asm(".word 0x001401E5"); |
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208 asm("KIvaBcrLinkedToFive:"); |
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209 asm(".word 0x001501E5"); |
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210 } |
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211 |
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212 __NAKED__ void UnsetBrp(TInt /*aRegister*/) |
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213 { |
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214 asm("mov r2, r0"); |
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215 asm("mov r1, #0"); |
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216 asm("mov r0, #0"); |
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217 asm("ldr r3, KIvaBcrDisabled"); |
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218 asm("b DoSetIvaBrp"); |
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219 |
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220 asm("KIvaBcrDisabled:"); |
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221 asm(".word 0x001401E4"); |
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222 } |
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223 #endif |