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// Copyright (c) 2003-2009 Nokia Corporation and/or its subsidiary(-ies).
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// All rights reserved.
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// This component and the accompanying materials are made available
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// under the terms of the License "Eclipse Public License v1.0"
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// which accompanies this distribution, and is available
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// at the URL "http://www.eclipse.org/legal/epl-v10.html".
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//
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// Initial Contributors:
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// Nokia Corporation - initial contribution.
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//
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// Contributors:
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//
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// Description:
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// General register definitions for the SDIO controller
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//
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//
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/**
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@file sdiodefs.h
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@publishedPartner
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@released
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*/
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#ifndef __SDIODEFS_H__
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#define __SDIODEFS_H__
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//// Constants for Read/Write[Direct/Extended]
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const TUint32 KSdioCmdDataMask = 0x000000FF; // CMD52/CMD53 Direction
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const TUint32 KSdioCmdDirMask = 0x80000000; // CMD52/CMD53 Direction
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const TUint32 KSdioCmdRead = 0x00000000; // CMD52/CMD53 Direction : Read
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const TUint32 KSdioCmdWrite = 0x80000000; // CMD52/CMD53 Direction : Write
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const TUint32 KSdioCmdRAW = 0x08000000; // CMD52 Read-After-Write
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const TUint32 KSdioCmdByteMode = 0x00000000; // CMD53 Byte Mode
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const TUint32 KSdioCmdBlockMode = 0x08000000; // CMD53 Block Mode
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const TUint32 KSdioCmdAutoInc = 0x04000000; // CMD53 Incrementing Address
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const TUint32 KSdioCmdFIFO = 0x00000000; // CMD53 FIFO Mode
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const TUint32 KSdioCmdFunctionMask = 0x03;
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const TUint32 KSdioCmdFunctionShift = 28;
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const TUint32 KSdioCmdAddressMask = 0x1FFFF;
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const TUint32 KSdioCmdAddressShift = 9;
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const TUint32 KSdioCmdAddressMaskShifted = KSdioCmdAddressMask << KSdioCmdAddressShift;
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const TUint32 KSdioCmdAddressAIncVal = 1 << KSdioCmdAddressShift;
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const TUint32 KSdioCmdCountMask = 0x1FF;
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//// R4 Response Bitfields
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const TUint32 KSDIOMemoryPresent = KBit27; // 32bit SDIO R4 Response
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const TUint32 KSDIOFunctionCountMask = KBit28 | KBit29 | KBit30; // 32bit SDIO R4 Response
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const TUint32 KSDIOFunctionCountShift = 28; // 32bit SDIO R4 Response
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const TUint32 KSDIOReady = KBit31; // 32bit SDIO R4 Response
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const TUint32 KSDIOOCRMask = 0x00FFFFFF; // 32bit SDIO R4 Response
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//// Card Common Control Registers (CCCR)
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const TUint32 KCCCRRegSdioRevision = 0x00;
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const TUint32 KCCCRRegSdSpec = 0x01;
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const TUint32 KCCCRRegIoEnable = 0x02;
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const TUint32 KCCCRRegIoReady = 0x03;
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const TUint32 KCCCRRegIntEnable = 0x04;
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const TUint32 KCCCRRegIntPending = 0x05;
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const TUint32 KCCCRRegIoAbort = 0x06;
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const TUint32 KCCCRRegBusInterfaceControl = 0x07;
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const TUint32 KCCCRRegCardCapability = 0x08;
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const TUint32 KCCCRRegCisPtrLo = 0x09;
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const TUint32 KCCCRRegCisPtrMid = 0x0a;
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const TUint32 KCCCRRegCisPtrHi = 0x0b;
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const TUint32 KCCCRRegBusSuspend = 0x0c;
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const TUint32 KCCCRRegFunctionSelect = 0x0d;
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const TUint32 KCCCRRegExecFlags = 0x0e;
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const TUint32 KCCCRRegReadyFlags = 0x0f;
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const TUint32 KCCCRRegFN0BlockSizeLo = 0x10;
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const TUint32 KCCCRRegFN0BlockSizeHi = 0x11;
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const TUint32 KCCCRRegPowerControl = 0x12;
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const TUint32 KCCCRRegHighSpeed = 0x13;
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//// Bit definitions for KCCCRRegIntEnable
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const TUint8 KSDIOCardIntEnMaster = KBit0; // Master Interrupt Enable bit
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//// Bit definitions for KCCCRRegIntEnable
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const TUint8 KSDIOCardIntPendMask = 0xfe; // Pending interrupt mask
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//// Bit definitions for KCCCRRegCardCapability
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const TUint8 KSDIOCardCapsBit4BLS = KBit7; // 4-Bit mode supported for Low Speed devices
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const TUint8 KSDIOCardCapsBitLSC = KBit6; // Card is a Low Speed device
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const TUint8 KSDIOCardCapsBitE4MI = KBit5; // Enable interrupt between blocks in 4-bit mode
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const TUint8 KSDIOCardCapsBitS4MI = KBit4; // Supports interrups between blocks in 4-bit mode
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const TUint8 KSDIOCardCapsBitSBS = KBit3; // Supports Suspend/Resume
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const TUint8 KSDIOCardCapsBitSRW = KBit2; // Supports Read/Wait
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const TUint8 KSDIOCardCapsBitSMB = KBit1; // Supports Multi-Block
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const TUint8 KSDIOCardCapsBitSDC = KBit0; // Supports Direct Commands during Mult-Byte transfer
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//// Bit definitions for KCCCRRegIoAbort
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const TUint8 KSDIOCardIoAbortReset = KBit3; // IO Reset
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//// Bit definitions for KCCCRRegBusInterfaceControl
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const TUint8 KSDIOCardBicBitBusWidth4 = KBit1;
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const TUint8 KSDIOCardBicMaskBusWidth = KBit0 | KBit1;
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const TUint8 KSDIOCardBicBitCdDisable = KBit7;
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//// Bit definitions for KCCCRRegHighSpeed
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const TUint8 KSDIOCardHighSpeedSHS = KBit0;
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const TUint8 KSDIOCardHighSpeedEHS = KBit1;
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//// FBR Offsets
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const TUint32 KFBRFunctionOffset = 0x100;
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//// Function Basic Registers (FBR)
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const TUint8 KFBRRegInterfaceCode = 0x00;
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const TUint8 KFBRRegExtendedCode = 0x01;
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const TUint8 KFBRRegPowerFlags = 0x02;
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const TUint8 KFBRRegCisPtrLo = 0x09;
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const TUint8 KFBRRegCisPtrMid = 0x0a;
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const TUint8 KFBRRegCisPtrHi = 0x0b;
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const TUint8 KFBRRegCsaPtrLo = 0x0c;
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const TUint8 KFBRRegCsaPtrMid = 0x0d;
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const TUint8 KFBRRegCsaPtrHi = 0x0e;
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const TUint8 KFBRRegCsaWindow = 0x0f;
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const TUint8 KFBRRegIoBlockSizeLo = 0x10;
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const TUint8 KFBRRegIoBlockSizeHi = 0x11;
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//// FBR Register Bit Definitions
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const TUint8 KFBRRegInterfaceCodeMask = KBit0 | KBit1 | KBit2 | KBit3;
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const TUint8 KFBRRegSupportsCSA = KBit6;
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const TUint8 KFBRRegEnableCSA = KBit7;
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const TUint8 KFBRRegEnableHighPower = KBit2;
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const TUint8 KFBRRegPowerSupportMask = KBit0 | KBit1;
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const TUint8 KFBRRegStandardPower = 0x00;
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const TUint8 KFBRRegHighPowerSupported = KBit1;
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const TUint8 KFBRRegHighPowerRequired = KBit0 | KBit1;
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////
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const TUint32 KSDIOCccrLength = 0x14;
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// FBR only reads upto the CSA Data Pointer, it should never include the CSA Data Window
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const TUint32 KSDIOFbrLength = 0x0e;
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////
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const TUint32 KCommandSessionBlocked = KBit0;
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const TUint32 KDataSessionBlocked = KBit1;
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////
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const TUint32 KSDIOBusWidth1=0x00;
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const TUint32 KSDIOBusWidth4=0x02;
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const TUint32 KSDIOStatusBlockLength = 0x40;
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////
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#endif // #ifndef __SDIODEFS_H__
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