// Copyright (c) 1997-2009 Nokia Corporation and/or its subsidiary(-ies).

// All rights reserved.

// This component and the accompanying materials are made available

// under the terms of the License "Eclipse Public License v1.0"

// which accompanies this distribution, and is available

// at the URL "http://www.eclipse.org/legal/epl-v10.html".

//

// Initial Contributors:

// Nokia Corporation - initial contribution.

//

// Contributors:

//

// Description:

// e32\memmodel\epoc\multiple\x86\xmmu.cpp

// 

//

#include <x86_mem.h>

#include <mmubase.inl>

#include <ramcache.h>

#include "execs.h"

#include <defrag.h>

extern "C" void DoTotalInvalidateTLB();

// Constants for X86 MMU

const TUint32 KPdePtePresent=0x01;

const TUint32 KPdePteWrite=0x02;

const TUint32 KPdePteUser=0x04;

const TUint32 KPdePteWriteThrough=0x08;

const TUint32 KPdePteUncached=0x10;

const TUint32 KPdePteAccessed=0x20;

const TUint32 KPdePteDirty=0x40;

const TUint32 KPdeLargePage=0x80;						// Pentium and above, not 486

const TUint32 KPdePteGlobal=0x100;						// P6 and above, not 486 or Pentium

const TUint32 KPdePtePhysAddrMask=0xfffff000u;

const TUint32 KPdeLargePagePhysAddrMask=0xffc00000u;	// Pentium and above, not 486

const TPde KPdPdePerm=KPdePtePresent|KPdePteWrite;

const TPte KPdPtePerm=KPdePtePresent|KPdePteWrite;

const TPde KPtPdePerm=KPdePtePresent|KPdePteWrite;

const TPte KPtPtePerm=KPdePtePresent|KPdePteWrite;

const TPde KPtInfoPdePerm=KPdePtePresent|KPdePteWrite;

const TPte KPtInfoPtePerm=KPdePtePresent|KPdePteWrite;

const TPde KRomPdePerm=KPdePtePresent|KPdePteWrite|KPdePteUser;

const TPte KRomPtePerm=KPdePtePresent|KPdePteUser;

const TPde KShadowPdePerm=KPdePtePresent|KPdePteWrite|KPdePteUser;

const TPte KShadowPtePerm=KPdePtePresent|KPdePteWrite|KPdePteUser;	// unfortunately there's no RWRO

// Permissions for each chunk type

const TPde KStandardPtePerm=KPdePtePresent|KPdePteWrite|KPdePteUser;

const TPte KPdePermNONO=KPdePtePresent|KPdePteWrite|KPdePteUser;

const TPte KPdePermRONO=KPdePtePresent;

const TPte KPdePermRORO=KPdePtePresent|KPdePteUser;

const TPte KPdePermRWNO=KPdePtePresent|KPdePteWrite;

const TPte KPdePermRWRW=KPdePtePresent|KPdePteWrite|KPdePteUser;

LOCAL_D const TPte ChunkPtePermissions[ENumChunkTypes] =

	{

	KStandardPtePerm|KPdePteGlobal,		// EKernelData

	KStandardPtePerm|KPdePteGlobal,		// EKernelStack

	KPdePermRWNO|KPdePteGlobal,			// EKernelCode - loading

	KPdePermRWNO,						// EDll (used for global code) - loading

	KPdePermRORO,						// EUserCode

	KStandardPtePerm,					// ERamDrive

	KStandardPtePerm,					// EUserData

	KStandardPtePerm,					// EDllData

	KStandardPtePerm,					// EUserSelfModCode

	KStandardPtePerm,					// ESharedKernelSingle

	KStandardPtePerm,					// ESharedKernelMultiple

	KStandardPtePerm,					// ESharedIo

	KStandardPtePerm|KPdePteGlobal,		// ESharedKernelMirror

	KStandardPtePerm|KPdePteGlobal,		// EKernelMessage

	};

LOCAL_D const TPde ChunkPdePermissions[ENumChunkTypes] =

	{

	KPdePermRWNO,			// EKernelData

	KPdePermRWNO,			// EKernelStack

	KPdePermRWNO,			// EKernelCode

	KPdePermRWRW,			// EDll

	KPdePermRWRW,			// EUserCode

	KPdePermRWRW,			// ERamDrive

	KPdePermRWRW,			// EUserData

	KPdePermRWRW,			// EDllData

	KPdePermRWRW,			// EUserSelfModCode

	KPdePermRWRW,			// ESharedKernelSingle

	KPdePermRWRW,			// ESharedKernelMultiple

	KPdePermRWRW,			// ESharedIo

	KPdePermRWNO,			// ESharedKernelMirror

	KPdePermRWNO,			// EKernelMessage

	};

#if defined(KMMU)

extern "C" void __DebugMsgFlushTLB()

	{

	__KTRACE_OPT(KMMU,Kern::Printf("FlushTLB"));

	}

extern "C" void __DebugMsgLocalFlushTLB()

	{

	__KTRACE_OPT(KMMU,Kern::Printf("FlushTLB"));

	}

extern "C" void __DebugMsgTotalFlushTLB()

	{

	__KTRACE_OPT(KMMU,Kern::Printf("TotalFlushTLB"));

	}

extern "C" void __DebugMsgINVLPG(int a)

	{

	__KTRACE_OPT(KMMU,Kern::Printf("INVLPG(%08x)",a));

	}

#endif

// Inline functions for simple transformations

inline TLinAddr PageTableLinAddr(TInt aId)

	{

	return (KPageTableBase+(aId<<KPageTableShift));

	}

inline TPte* PageTable(TInt aId)

	{

	return (TPte*)(KPageTableBase+(aId<<KPageTableShift));

	}

inline TLinAddr PageDirectoryLinAddr(TInt aOsAsid)

	{

	return (KPageDirectoryBase+(aOsAsid<<KPageTableShift));

	}

extern "C" {

void __fastcall DoInvalidateTLBForPage(TLinAddr /*aLinAddr*/);

void DoInvalidateTLB();

void DoLocalInvalidateTLB();

}

#ifdef __SMP__

TSpinLock ShadowSpinLock(TSpinLock::EOrderGenericPreHigh0);	// Used when stopping other CPUs

class TTLBIPI : public TGenericIPI

	{

public:

	TTLBIPI();

	static void InvalidateForPagesIsr(TGenericIPI*);

	static void LocalInvalidateIsr(TGenericIPI*);

	static void TotalInvalidateIsr(TGenericIPI*);

	static void InvalidateIsr(TGenericIPI*);

	static void WaitAndInvalidateIsr(TGenericIPI*);

	void AddAddress(TLinAddr aAddr);

	void InvalidateList();

public:

	volatile TInt	iFlag;

	TInt			iCount;

	TLinAddr		iAddr[KMaxPages];

	};

TTLBIPI::TTLBIPI()

	:	iFlag(0), iCount(0)

	{

	}

void TTLBIPI::LocalInvalidateIsr(TGenericIPI*)

	{

	__KTRACE_OPT(KMMU2,Kern::Printf("TLBLocInv"));

	DoLocalInvalidateTLB();

	}

void TTLBIPI::TotalInvalidateIsr(TGenericIPI*)

	{

	__KTRACE_OPT(KMMU2,Kern::Printf("TLBTotInv"));

	DoTotalInvalidateTLB();

	}

void TTLBIPI::InvalidateIsr(TGenericIPI*)

	{

	__KTRACE_OPT(KMMU2,Kern::Printf("TLBInv"));

	DoInvalidateTLB();

	}

void TTLBIPI::WaitAndInvalidateIsr(TGenericIPI* aTLBIPI)

	{

	__KTRACE_OPT(KMMU2,Kern::Printf("TLBWtInv"));

	TTLBIPI& a = *(TTLBIPI*)aTLBIPI;

	while (!a.iFlag)

		{}

	if (a.iCount == 1)

		DoInvalidateTLBForPage(a.iAddr[0]);

	else

		DoInvalidateTLB();

	}

void TTLBIPI::InvalidateForPagesIsr(TGenericIPI* aTLBIPI)

	{

	TTLBIPI& a = *(TTLBIPI*)aTLBIPI;

	TInt i;

	for (i=0; i<a.iCount; ++i)

		{

		__KTRACE_OPT(KMMU2,Kern::Printf("TLBInv %08x", a.iAddr[i]));

		DoInvalidateTLBForPage(a.iAddr[i]);

		}

	}

void TTLBIPI::AddAddress(TLinAddr aAddr)

	{

	iAddr[iCount] = aAddr;

	if (++iCount == KMaxPages)

		InvalidateList();

	}

void TTLBIPI::InvalidateList()

	{

	NKern::Lock();

	InvalidateForPagesIsr(this);

	QueueAllOther(&InvalidateForPagesIsr);

	NKern::Unlock();

	WaitCompletion();

	iCount = 0;

	}

void LocalInvalidateTLB()

	{

	TTLBIPI ipi;

	NKern::Lock();

	DoLocalInvalidateTLB();

	ipi.QueueAllOther(&TTLBIPI::LocalInvalidateIsr);

	NKern::Unlock();

	ipi.WaitCompletion();

	}

void TotalInvalidateTLB()

	{

	TTLBIPI ipi;

	NKern::Lock();

	DoTotalInvalidateTLB();

	ipi.QueueAllOther(&TTLBIPI::TotalInvalidateIsr);

	NKern::Unlock();

	ipi.WaitCompletion();

	}

void InvalidateTLB()

	{

	TTLBIPI ipi;

	NKern::Lock();

	DoInvalidateTLB();

	ipi.QueueAllOther(&TTLBIPI::InvalidateIsr);

	NKern::Unlock();

	ipi.WaitCompletion();

	}

void InvalidateTLBForPage(TLinAddr aAddr)

	{

	TTLBIPI ipi;

	ipi.AddAddress(aAddr);

	ipi.InvalidateList();

	}

#else

#define	InvalidateTLBForPage(a)		DoInvalidateTLBForPage(a)

#define	LocalInvalidateTLB()		DoLocalInvalidateTLB()

#define	TotalInvalidateTLB()		TotalInvalidateTLB()

#define	InvalidateTLB()				DoInvalidateTLB()

#endif

TPte* SafePageTableFromPde(TPde aPde)

	{

	if (aPde&KPdePtePresent)

		{

		SPageInfo* pi = SPageInfo::SafeFromPhysAddr(aPde);

		if (pi)

			{

			TInt id=pi->Offset();	// assumes page table size = page size

			return PageTable(id);

			}

		}

	return 0;

	}

TPte* SafePtePtrFromLinAddr(TLinAddr aAddress, TInt aOsAsid=0)

	{

	TPde pde = PageDirectory(aOsAsid)[aAddress>>KChunkShift];

	TPte* pt = SafePageTableFromPde(pde);

	if(pt)

		pt += (aAddress>>KPageShift)&(KChunkMask>>KPageShift);

	return pt;

	}

TPte* PtePtrFromLinAddr(TLinAddr aAddress, TInt aOsAsid=0)

	{

	TPde pde = PageDirectory(aOsAsid)[aAddress>>KChunkShift];

	SPageInfo* pi = SPageInfo::FromPhysAddr(pde);

	TInt id = (pi->Offset()<<KPtClusterShift) | ((pde>>KPageTableShift)&KPtClusterMask);

	TPte* pt = PageTable(id);

	pt += (aAddress>>KPageShift)&(KChunkMask>>KPageShift);

	return pt;

	}

TInt X86Mmu::LinearToPhysical(TLinAddr aAddr, TInt aSize, TPhysAddr& aPhysicalAddress, TPhysAddr* aPhysicalPageList, TInt aOsAsid)

	{

	TPhysAddr physStart = LinearToPhysical(aAddr,aOsAsid);

	TInt pageShift = iPageShift;

	TUint32 page = aAddr>>pageShift<<pageShift;

	TUint32 lastPage = (aAddr+aSize-1)>>pageShift<<pageShift;

	TUint32* pageList = aPhysicalPageList;

	TUint32 nextPhys = LinearToPhysical(page,aOsAsid);

	TUint32 pageSize = 1<<pageShift;

	while(page<=lastPage)

		{

		TPhysAddr phys = LinearToPhysical(page,aOsAsid);

		if(pageList)

			*pageList++ = phys;

		if(phys!=nextPhys)

			nextPhys = KPhysAddrInvalid;

		else

			nextPhys += pageSize;

		page += pageSize;

		}

	if(nextPhys==KPhysAddrInvalid)

		{

		// Memory is discontiguous...

		aPhysicalAddress = KPhysAddrInvalid;

		return 1;

		}

	else

		{

		// Memory is contiguous...

		aPhysicalAddress = physStart;

		return KErrNone;

		}

	return KErrNone;

	}

TPhysAddr X86Mmu::LinearToPhysical(TLinAddr aLinAddr, TInt aOsAsid)

//

// Find the physical address corresponding to a given linear address in a specified OS

// address space. Call with system locked.

//

	{

	__KTRACE_OPT(KMMU2,Kern::Printf("X86Mmu::LinearToPhysical(%08x,%d)",aLinAddr,aOsAsid));

	TInt pdeIndex=aLinAddr>>KChunkShift;

	TPde pde=PageDirectory(aOsAsid)[pdeIndex];

	TPhysAddr pa=KPhysAddrInvalid;

	if (pde & KPdePtePresent)

		{

		SPageInfo* pi = SPageInfo::SafeFromPhysAddr(pde);

		if (pi)

			{

			TInt id=pi->Offset();	// assumes page table size = page size

			TPte* pPte=PageTable(id);

			TPte pte=pPte[(aLinAddr&KChunkMask)>>KPageShift];

			if (pte & KPdePtePresent)

				{

				pa=(pte&KPdePtePhysAddrMask)+(aLinAddr&KPageMask);

				__KTRACE_OPT(KMMU2,Kern::Printf("Mapped with page table - returning %08x",pa));

				}

			}

		}

	return pa;

	}

TInt X86Mmu::PreparePagesForDMA(TLinAddr /*aLinAddr*/, TInt /*aSize*/, TInt /*aOsAsid*/, TPhysAddr* /*aPhysicalPageList*/)

	{

	return KErrNotSupported;

	}

TInt X86Mmu::ReleasePagesFromDMA(TPhysAddr* /*aPhysicalPageList*/, TInt /*aPageCount*/)

	{

	return KErrNotSupported;

	}

static const TInt PermissionLookup[8]=

	{

	0,

	EMapAttrReadSup|EMapAttrExecSup,

	0,

	EMapAttrWriteSup|EMapAttrReadSup|EMapAttrExecSup,

	0,

	EMapAttrReadUser|EMapAttrExecUser,

	0,

	EMapAttrWriteUser|EMapAttrReadUser|EMapAttrExecUser

	};

TInt X86Mmu::PageTableId(TLinAddr aAddr, TInt aOsAsid)

	{

	TInt id=-1;

	__KTRACE_OPT(KMMU,Kern::Printf("X86Mmu::PageTableId(%08x,%d)",aAddr,aOsAsid));

	TInt pdeIndex=aAddr>>KChunkShift;

	TPde pde=PageDirectory(aOsAsid)[pdeIndex];

	if (pde & KPdePtePresent)

		{

		SPageInfo* pi = SPageInfo::SafeFromPhysAddr(pde);

		if (pi)

			id=pi->Offset();	// assumes page table size = page size

		}

	__KTRACE_OPT(KMMU,Kern::Printf("ID=%d",id));

	return id;

	}

// Used only during boot for recovery of RAM drive

TInt X86Mmu::BootPageTableId(TLinAddr aAddr, TPhysAddr& aPtPhys)

	{

	TInt id=KErrNotFound;

	__KTRACE_OPT(KMMU,Kern::Printf("X86Mmu:BootPageTableId(%08x,&)",aAddr));

	TPde* kpd=(TPde*)KPageDirectoryBase;	// kernel page directory

	TInt pdeIndex=aAddr>>KChunkShift;

	TPde pde = kpd[pdeIndex];

	if (pde & KPdePtePresent)

		{

		aPtPhys = pde & KPdePtePhysAddrMask;

		SPageInfo* pi = SPageInfo::SafeFromPhysAddr(pde);

		if (pi)

			{

			SPageInfo::TType type = pi->Type();

			if (type == SPageInfo::EPageTable)

				id=pi->Offset();	// assumes page table size = page size

			else if (type == SPageInfo::EUnused)

				id = KErrUnknown;

			}

		}

	__KTRACE_OPT(KMMU,Kern::Printf("ID=%d",id));

	return id;

	}

TBool X86Mmu::PteIsPresent(TPte aPte)

	{

	return aPte & KPdePtePresent;

	}

TPhysAddr X86Mmu::PtePhysAddr(TPte aPte, TInt /*aPteIndex*/)

	{

	return aPte & KPdePtePhysAddrMask;

	}

TPhysAddr X86Mmu::PdePhysAddr(TLinAddr aAddr)

	{

	TPde* kpd = (TPde*)KPageDirectoryBase;	// kernel page directory

	TPde pde = kpd[aAddr>>KChunkShift];

	if (pde & (KPdePtePresent|KPdeLargePage) == (KPdePtePresent|KPdeLargePage))

		return pde & KPdeLargePagePhysAddrMask;

	return KPhysAddrInvalid;

	}

void X86Mmu::Init1()

	{

	__KTRACE_OPT2(KBOOT,KMMU,Kern::Printf("X86Mmu::Init1"));

	TUint pge = TheSuperPage().iCpuId & EX86Feat_PGE;

	iPteGlobal = pge ? KPdePteGlobal : 0;	

	X86_UseGlobalPTEs = pge!=0;

	// MmuBase data

	iPageSize=KPageSize;

	iPageMask=KPageMask;

	iPageShift=KPageShift;

	iChunkSize=KChunkSize;

	iChunkMask=KChunkMask;

	iChunkShift=KChunkShift;

	iPageTableSize=KPageTableSize;

	iPageTableMask=KPageTableMask;

	iPageTableShift=KPageTableShift;

	iPtClusterSize=KPtClusterSize;

	iPtClusterMask=KPtClusterMask;

	iPtClusterShift=KPtClusterShift;

	iPtBlockSize=KPtBlockSize;

	iPtBlockMask=KPtBlockMask;

	iPtBlockShift=KPtBlockShift;

	iPtGroupSize=KChunkSize/KPageTableSize;

	iPtGroupMask=iPtGroupSize-1;

	iPtGroupShift=iChunkShift-iPageTableShift;

	//TInt* iPtBlockCount;		// dynamically allocated - Init2

	//TInt* iPtGroupCount;		// dynamically allocated - Init2

	iPtInfo=(SPageTableInfo*)KPageTableInfoBase;

	iPageTableLinBase=KPageTableBase;

	//iRamPageAllocator;		// dynamically allocated - Init2

	//iAsyncFreeList;			// dynamically allocated - Init2

	//iPageTableAllocator;		// dynamically allocated - Init2

	//iPageTableLinearAllocator;// dynamically allocated - Init2

	iPtInfoPtePerm=KPtInfoPtePerm|iPteGlobal;

	iPtPtePerm=KPtPtePerm|iPteGlobal;

	iPtPdePerm=KPtPdePerm;

	iUserCodeLoadPtePerm=KPdePermRWNO;

	iKernelCodePtePerm=KPdePermRONO|iPteGlobal;

	iTempAddr=KTempAddr;

	iSecondTempAddr=KSecondTempAddr;

	TUint pse = TheSuperPage().iCpuId & EX86Feat_PSE;

	iMapSizes = pse ? KPageSize|KChunkSize : KPageSize;

	iDecommitThreshold=0;		// no cache consistency issues on decommit

	iRomLinearBase = ::RomHeaderAddress;

	iRomLinearEnd = KRomLinearEnd;

	iShadowPtePerm = KShadowPtePerm;

	iShadowPdePerm = KShadowPdePerm;

	// Mmu data

	TInt total_ram=TheSuperPage().iTotalRamSize;

	iNumOsAsids=1024;

	iNumGlobalPageDirs=1;

	//iOsAsidAllocator;			// dynamically allocated - Init2

	iGlobalPdSize=KPageTableSize;

	iGlobalPdShift=KPageTableShift;

	iLocalPdSize=0;

	iLocalPdShift=0;

	iAsidGroupSize=KChunkSize/KPageTableSize;

	iAsidGroupMask=iAsidGroupSize-1;

	iAsidGroupShift=iChunkShift-iGlobalPdShift;

	iAliasSize=KPageSize;

	iAliasMask=KPageMask;

	iAliasShift=KPageShift;

	iUserLocalBase=KUserLocalDataBase;

	iUserSharedBase=KUserSharedDataBase;

	iAsidInfo=(TUint32*)KAsidInfoBase;

	iPdeBase=KPageDirectoryBase;

	iPdPtePerm=KPdPtePerm|iPteGlobal;

	iPdPdePerm=KPdPdePerm;

	iRamDriveMask=0x00f00000;

	iGlobalCodePtePerm=KPdePermRORO|iPteGlobal;