// Copyright (c) 2003-2009 Nokia Corporation and/or its subsidiary(-ies).

// All rights reserved.

// This component and the accompanying materials are made available

// under the terms of the License "Eclipse Public License v1.0"

// which accompanies this distribution, and is available

// at the URL "http://www.eclipse.org/legal/epl-v10.html".

//

// Initial Contributors:

// Nokia Corporation - initial contribution.

//

// Contributors:

//

// Description:

// e32test\math\t_vfp.cia

// 

//

#include "t_vfp.h"

#include <u32std.h>

#define __TEST_VFPV3

#define _DIE(x)	asm(".word %a0" : : "i" ((TInt)( 0xe7f000f0|((x)&0x0f)|(((x)&0xfff0)<<4) )));

#define DIE		_DIE(__LINE__);

/******************************************************************************

 * Control registers

 ******************************************************************************/

__NAKED__ TUint32 Vfp::Fpscr()

	{

	VFP_FMRX(,0,VFP_XREG_FPSCR);

	__JUMP(,lr);

	}

__NAKED__ void Vfp::SetFpscr(TUint32 /*aVal*/)

	{

	VFP_FMXR(,VFP_XREG_FPSCR,0);

	__JUMP(,lr);

	}

/******************************************************************************

 * Single precision operations

 ******************************************************************************/

__NAKED__ TInt32 Vfp::SRegInt(TInt /*aReg*/)

	{

	// fall through

	}

__NAKED__ TReal32 Vfp::SReg(TInt /*aReg*/)

	{

	asm("cmp r0, #31 ");

	asm("addls pc, pc, r0, lsl #3 ");

	DIE;

	VFP_FMRS(CC_AL,0,0);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,1);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,2);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,3);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,4);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,5);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,6);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,7);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,8);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,9);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,10);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,11);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,12);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,13);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,14);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,15);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,16);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,17);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,18);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,19);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,20);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,21);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,22);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,23);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,24);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,25);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,26);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,27);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,28);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,29);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,30);

	__JUMP(,lr);

	VFP_FMRS(CC_AL,0,31);

	__JUMP(,lr);

	}

__NAKED__ void Vfp::SetSReg(TInt32 /*aVal*/, TInt /*aReg*/)

	{

	// fall through

	}

__NAKED__ void Vfp::SetSReg(TReal32 /*aVal*/, TInt /*aReg*/)

	{

	asm("cmp r1, #31 ");

	asm("addls pc, pc, r1, lsl #3 ");

	DIE;

	VFP_FMSR(CC_AL,0,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,1,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,2,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,3,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,4,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,5,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,6,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,7,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,8,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,9,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,10,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,11,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,12,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,13,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,14,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,15,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,16,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,17,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,18,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,19,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,20,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,21,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,22,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,23,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,24,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,25,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,26,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,27,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,28,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,29,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,30,0);

	__JUMP(,lr);

	VFP_FMSR(CC_AL,31,0);

	__JUMP(,lr);

	}

__NAKED__ void Vfp::AbsS()

	{

	asm("nop ");			// so that RVCT doesn't complain about branches to non-code symbols

	VFP_FABSS(CC_AL,0,1);

	__JUMP(,lr);

	}

__NAKED__ void Vfp::AddS()

	{

	asm("nop ");			// so that RVCT doesn't complain about branches to non-code symbols

	VFP_FADDS(CC_AL,0,1,2);

	__JUMP(,lr);

	}

__NAKED__ void Vfp::CmpS()

	{

	VFP_FCMPS(CC_AL,0,1);

	__JUMP(,lr);

	}

__NAKED__ void Vfp::CmpES()

	{

	VFP_FCMPES(CC_AL,0,1);

	__JUMP(,lr);

	}

__NAKED__ void Vfp::CmpEZS()

	{

	VFP_FCMPEZS(CC_AL,0);

	__JUMP(,lr);

	}

__NAKED__ void Vfp::CmpZS()

	{

	VFP_FCMPZS(CC_AL,0);

	__JUMP(,lr);

	}

__NAKED__ void Vfp::Cpy0S(TInt /*aReg*/)

	{

	asm("cmp r0, #31 ");

	asm("addls pc, pc, r0, lsl #3 ");

	DIE;

	VFP_FCPYS(CC_AL,0,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,1);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,2);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,3);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,4);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,5);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,6);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,7);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,8);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,9);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,10);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,11);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,12);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,13);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,14);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,15);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,16);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,17);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,18);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,19);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,20);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,21);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,22);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,23);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,24);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,25);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,26);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,27);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,28);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,29);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,30);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,0,31);

	__JUMP(,lr);

	}

__NAKED__ void Vfp::CpyS0(TInt /*aReg*/)

	{

	asm("cmp r0, #31 ");

	asm("addls pc, pc, r0, lsl #3 ");

	DIE;

	VFP_FCPYS(CC_AL,0,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,1,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,2,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,3,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,4,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,5,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,6,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,7,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,8,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,9,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,10,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,11,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,12,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,13,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,14,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,15,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,16,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,17,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,18,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,19,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,20,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,21,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,22,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,23,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,24,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,25,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,26,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,27,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,28,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,29,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,30,0);

	__JUMP(,lr);

	VFP_FCPYS(CC_AL,31,0);

	__JUMP(,lr);

	}

__NAKED__ void Vfp::DivS()

	{

	asm("nop ");			// so that RVCT doesn't complain about branches to non-code symbols

	VFP_FDIVS(CC_AL,0,1,2);

	__JUMP(,lr);

	}

__NAKED__ void Vfp::MacS()

	{

	asm("nop ");			// so that RVCT doesn't complain about branches to non-code symbols

	VFP_FMACS(CC_AL,0,1,2);

	__JUMP(,lr);

	}

__NAKED__ void Vfp::MscS()

	{

	asm("nop ");			// so that RVCT doesn't complain about branches to non-code symbols

	VFP_FMSCS(CC_AL,0,1,2);

	__JUMP(,lr);

	}

__NAKED__ void Vfp::MulS()

	{

	asm("nop ");			// so that RVCT doesn't complain about branches to non-code symbols

	VFP_FMULS(CC_AL,0,1,2);

	__JUMP(,lr);

	}

__NAKED__ void Vfp::NegS()

	{

	asm("nop ");			// so that RVCT doesn't complain about branches to non-code symbols

	VFP_FNEGS(CC_AL,0,1);

	__JUMP(,lr);

	}

__NAKED__ void Vfp::NMacS()

	{

	asm("nop ");			// so that RVCT doesn't complain about branches to non-code symbols

	VFP_FNMACS(CC_AL,0,1,2);

	__JUMP(,lr);

	}

__NAKED__ void Vfp::NMscS()

	{

	asm("nop ");			// so that RVCT doesn't complain about branches to non-code symbols

	VFP_FNMSCS(CC_AL,0,1,2);

	__JUMP(,lr);

	}

__NAKED__ void Vfp::NMulS()

	{

	asm("nop ");			// so that RVCT doesn't complain about branches to non-code symbols

	VFP_FNMULS(CC_AL,0,1,2);

	__JUMP(,lr);

	}

__NAKED__ void Vfp::SqrtS()

	{

	asm("nop ");			// so that RVCT doesn't complain about branches to non-code symbols

	VFP_FSQRTS(CC_AL,0,1);

	__JUMP(,lr);

	}

__NAKED__ void Vfp::SubS()

	{

	asm("nop ");			// so that RVCT doesn't complain about branches to non-code symbols

	VFP_FSUBS(CC_AL,0,1,2);

	__JUMP(,lr);

	}

/******************************************************************************

 * Double precision operations

 ******************************************************************************/

__NAKED__ TInt64 Vfp::DRegInt(TInt /*aReg*/)

	{

	// fall through

	}

__NAKED__ TReal64 Vfp::DReg(TInt /*aReg*/)

	{

#ifdef __TEST_VFPV3

	asm("cmp r0, #31 ");

#else 

	asm("cmp r0, #15 ");

#endif 

	asm("addls r0, r0, r0, lsl #1 ");

	asm("addls pc, pc, r0, lsl #2 ");

	DIE;

	// test 

	// VFP_FLDD(CC_AL,4,5,0); 

	VFP_FMRDL(CC_AL,0,0);

	VFP_FMRDH(CC_AL,1,0);

	asm("b 0f ");

	VFP_FMRDL(CC_AL,0,1);

	VFP_FMRDH(CC_AL,1,1);

	asm("b 0f ");

	VFP_FMRDL(CC_AL,0,2);

	VFP_FMRDH(CC_AL,1,2);

	asm("b 0f ");

	VFP_FMRDL(CC_AL,0,3);

	VFP_FMRDH(CC_AL,1,3);

	asm("b 0f ");

	VFP_FMRDL(CC_AL,0,4);

	VFP_FMRDH(CC_AL,1,4);

	asm("b 0f ");

	VFP_FMRDL(CC_AL,0,5);

	VFP_FMRDH(CC_AL,1,5);

	asm("b 0f ");

	VFP_FMRDL(CC_AL,0,6);

	VFP_FMRDH(CC_AL,1,6);

	asm("b 0f ");

	VFP_FMRDL(CC_AL,0,7);

	VFP_FMRDH(CC_AL,1,7);

	asm("b 0f ");

	VFP_FMRDL(CC_AL,0,8);

	VFP_FMRDH(CC_AL,1,8);

	asm("b 0f ");

	VFP_FMRDL(CC_AL,0,9);

	VFP_FMRDH(CC_AL,1,9);

	asm("b 0f ");

	VFP_FMRDL(CC_AL,0,10);

	VFP_FMRDH(CC_AL,1,10);

	asm("b 0f ");

	VFP_FMRDL(CC_AL,0,11);

	VFP_FMRDH(CC_AL,1,11);

	asm("b 0f ");

	VFP_FMRDL(CC_AL,0,12);

	VFP_FMRDH(CC_AL,1,12);

	asm("b 0f ");

	VFP_FMRDL(CC_AL,0,13);

	VFP_FMRDH(CC_AL,1,13);

	asm("b 0f ");

	VFP_FMRDL(CC_AL,0,14);

	VFP_FMRDH(CC_AL,1,14);

	asm("b 0f ");

	VFP_FMRDL(CC_AL,0,15);

	VFP_FMRDH(CC_AL,1,15);

	asm("b 0f ");

#ifdef __TEST_VFPV3

	VFP_FMRDL(CC_AL,0,16);

	VFP_FMRDH(CC_AL,1,16);

	asm("b 0f ");

	VFP_FMRDL(CC_AL,0,17);

	VFP_FMRDH(CC_AL,1,17);

	asm("b 0f ");

	VFP_FMRDL(CC_AL,0,18);

	VFP_FMRDH(CC_AL,1,18);