// Copyright (c) 2005-2009 Nokia Corporation and/or its subsidiary(-ies).

// All rights reserved.

// This component and the accompanying materials are made available

// under the terms of the License "Eclipse Public License v1.0"

// which accompanies this distribution, and is available

// at the URL "http://www.eclipse.org/legal/epl-v10.html".

//

// Initial Contributors:

// Nokia Corporation - initial contribution.

//

// Contributors:

//

// Description:

// e32test\mmu\t_demandpaging.cpp

// Functional tests for demand paging. The test suite covers simple

// paging operations as well as HAL configuration and tuning functions.

// 001.01 DPTest::Attributes

// 001.02 DPTest::FlushCache

// 001.03 DPTest::CacheSize

// 001.04 DPTest::SetCacheSize

// 001.04.01 Changing size of flushed VM cache

// 001.04.02 Changing size of full VM cache

// 002 Loading test drivers

// 003 Test thread realtime state

// 003.01 Enable KREALTIME tracing

// 003.02 Test ERealtimeStateOff

// 003.03 Test ERealtimeStateOn

// 003.04 Test ERealtimeStateWarn

// 003.05 Test server with ERealtimeStateOff

// 003.06 Test server with ERealtimeStateOn

// 003.07 Test server with ERealtimeStateWarn

// 003.08 Disable KREALTIME tracing

// 004 Lock Test

// 005 Lock Test again

// 006 Test writing to paged ROM

// 007 Test IPC read from paged memory

// 007.01 Create server

// 007.02 IPC read from ROM

// 007.03 Stop server

// 008 Test contiguous RAM allocation reclaims paged memory

// 008.01 Start...

// 008.02 Contiguous RAM test: alloc size = 128K align = 16

// 008.03 Contiguous RAM test: alloc size = 128K align = 0

// 008.04 Contiguous RAM test: alloc size = 64K align = 15

// 008.05 Contiguous RAM test: alloc size = 64K align = 14

// 008.06 Contiguous RAM test: alloc size = 64K align = 13

// 008.07 Contiguous RAM test: alloc size = 64K align = 12

// 008.08 Contiguous RAM test: alloc size = 64K align = 0

// 008.09 Contiguous RAM test: alloc size = 8K align = 13

// 008.10 Contiguous RAM test: alloc size = 8K align = 12

// 008.11 Contiguous RAM test: alloc size = 8K align = 0

// 008.12 Contiguous RAM test: alloc size = 4K align = 13

// 008.13 Contiguous RAM test: alloc size = 4K align = 12

// 008.14 Contiguous RAM test: alloc size = 4K align = 0

// 009 Test no kernel faults when copying data from unpaged rom with mutex held

// 010 Close test driver

// 011 Test setting publish and subscribe properties from paged area

// 012 Rom Paging Benchmark

// 012.01 Benchmark ROM paging...

// 

//

//! @SYMTestCaseID			KBASE-T_DEMANDPAGING-0334

//! @SYMTestType			UT

//! @SYMPREQ				PREQ1110

//! @SYMTestCaseDesc		Demand Paging functional tests.

//! @SYMTestActions			001 Test HAL interface

//! @SYMTestExpectedResults All tests should pass.

//! @SYMTestPriority        High

//! @SYMTestStatus          Implemented

#define __E32TEST_EXTENSION__

#include <e32test.h>

#include <dptest.h>

#include <e32kpan.h>

#include <e32property.h>

#include <e32rom.h>

#include "d_memorytest.h"

#include "d_demandpaging.h"

#include "d_gobble.h"

#include "mmudetect.h"

#include "t_codepaging_dll.h"

#include "freeram.h"

RTest test(_L("T_DEMANDPAGING"));

_LIT(KTCodePagingDll4, "t_codepaging_dll4.dll");

const TInt KMinBufferSize = 16384;

const TInt KMaxIPCSize = 256*1024;

TInt PageSize = 0;

RDemandPagingTestLdd Ldd;

RLibrary PagedLibrary;

// A buffer containing paged memory, contents may or may not be paged in

const TUint8* LargeBuffer = NULL;

TInt LargeBufferSize = 0;

// A buffer containing paged memeory, contents always paged out before access

const TUint8* SmallBuffer = NULL;

TInt SmallBufferSize = 0;

// A shared buffer mapped to the global address range

TInt SharedBufferSize = KMaxIPCSize+4096;

TLinAddr SharedBufferAddr = 0;

TUint8* SharedBuffer = NULL;

// A descriptor whose header is in paged memory (actually just a pointer to a zero word)

TDesC8* PagedHeaderDes = NULL;

// A data paged chunk used as a buffer, if data paging is supported

_LIT(KChunkName, "t_demandpaging chunk");

RChunk DataPagedChunk;

TBool DataPagingSupported = EFalse;

TUint8* DataPagedBuffer = NULL;

TUint8 ReadByte(volatile TUint8* aPtr)

	{

	return *aPtr;

	}

#define READ(a) ReadByte((volatile TUint8*)(a))

void ThrashPaging(TUint aBytes)

	{

	TUint size = LargeBufferSize;

	if(size > aBytes)

		size = aBytes;

	TUint readCount = 5 * size/PageSize;

	test.Printf(_L("ThrashPaging %u %u\n"), size, readCount);

	TUint32 random=1;

	for(TUint i = 0 ; i < readCount ; ++i)

		{

		READ(LargeBuffer+((TInt64(random)*TInt64(size))>>32));

		random = random*69069+1;

		}

	}

void FragmentPagingCache(TUint aMaxBytes)

	{

	DPTest::FlushCache();

	TUint size = Min(LargeBufferSize, aMaxBytes);

	if(size<aMaxBytes)

		test.Printf(_L("WARNING: LargeBuffer not large enough!  Have you built a full test ROM?\n"));

	RChunk chunk;

	test(KErrNone==chunk.CreateDisconnectedLocal(0,0,size));

	TUint32 random = 0;

	for(TUint i=0; i<size; i += PageSize)

		{

		random = random*69069+1;

		if(random<0x40000000)

			chunk.Commit(i,PageSize); // to make paging cache fragmented

		READ(LargeBuffer + i);

		}

	CLOSE_AND_WAIT(chunk);

	UserSvr::HalFunction(EHalGroupKernel, EKernelHalSupervisorBarrier, 0, 0);

	}

void RomPagingBenchmark()

	{

	TInt r=DPTest::FlushCache();

	if(r!=KErrNone)

		return;

	test.Start(_L("Benchmark ROM paging..."));

	// change live list to be a small as possible

	test(KErrNone==DPTest::SetCacheSize(1,1));

	RTimer timer;

	test(KErrNone==timer.CreateLocal());

	TRequestStatus status;

	timer.After(status,1);

	User::WaitForRequest(status);

	TPckgBuf<DPTest::TEventInfo> events0;

	DPTest::EventInfo(events0);

	TInt KRunTime = 10*1000*1000;

	timer.After(status,KRunTime);

	while(status==KRequestPending)

		for(const TUint8* ptr=LargeBuffer; ptr<(LargeBuffer+LargeBufferSize); ptr+=PageSize)

			{

			READ(ptr);

			if(status!=KRequestPending)

				break;

			}

	TPckgBuf<DPTest::TEventInfo> events1;

	DPTest::EventInfo(events1);

	User::WaitForRequest(status);

	TUint pages = events1().iPageInReadCount-events0().iPageInReadCount;

	test.Printf(_L("%d pages in %d seconds = %d us/page\n"),pages,KRunTime/1000/1000,KRunTime/pages);

	// restore live list to default size...

	test(KErrNone==DPTest::SetCacheSize(0,0));

	test.End();

	}

TInt SetCacheSize(TUint aNewMin, TUint aNewMax)

	{

	// set cache size and test 'get' function returns expected values

	TInt r = DPTest::SetCacheSize(aNewMin, aNewMax);

	if (r == KErrNone)

		{

		TUint min, max, current;

		test_KErrNone(DPTest::CacheSize(min,max,current));

		test_Equal(aNewMin, min);

		test_Equal(aNewMax, max);

		test(current >= min && current <= max);

		}

	return r;

	}

void DoResizeCache(TUint min, TUint max, TInt result, TUint& sizeMin, TUint& sizeMax, TUint originalMin, TUint originalMax)

	{

	test.Printf(_L("DPTest::SetCacheSize min=%u, max=%u, expected result=%d\n"),min/PageSize,max/PageSize,result);

	TInt r=SetCacheSize(min,max);

	test_Equal(result, r);

	if(r==KErrNone)

		{

		// we've successfully changed the cache size...

		if(max)

			{

			sizeMin = min;

			sizeMax = max;

			}

		else

			{

			sizeMin = originalMin;

			sizeMax = originalMax;

			}

		}

	else if(r==KErrNoMemory)

		{

		// cache size after OOM is unpredictable, so reset our values

		test_KErrNone(SetCacheSize(sizeMin,sizeMax));

		}

	}

void TestResizeVMCache()

	{

	test.Start(_L("Test resizing VM cache"));

	TInt r = DPTest::SetCacheSize(0,0); // restore cache size to defaults

	test(r==KErrNone);

	TUint sizeMin = 0;

	TUint sizeMax = 0;

	TUint currentSize = 0;

	DPTest::CacheSize(sizeMin,sizeMax,currentSize);

	TUint originalMin = sizeMin;

	TUint originalMax = sizeMax;

	test.Printf(_L("original min=%u, original max=%u, current=%u\n"),

				originalMin/PageSize,originalMax/PageSize,currentSize/PageSize);

	int K = currentSize/PageSize+4;

	// Exercise the cache reszing code by testing all valid combinations of the relationships

	// between the current min size, current max size, new min size and new max size.

	//

	// This can be done using four cache size values.  Every assignment of these four values to the

	// four variables is generated, and invalid combinations rejected.  This repeats some

	// relationships but is simpler than calculating the minimum set of combinations exactly.

	const TUint combinations = 256;  // 4 ^ 4

	const TUint sizes[] = { K, K + 4, K + 8, K + 12, K + 16 };

	for (TUint perm = 0 ; perm < combinations ; ++perm)

		{

		TUint vars[4] = { sizes[ perm & 3 ],

						  sizes[ (perm >> 2) & 3 ],

						  sizes[ (perm >> 4) & 3 ],

						  sizes[ (perm >> 6) & 3 ]};

		if ((vars[0] == vars[2] && vars[1] == vars[3]) || // ensure current != new

			vars[0] > vars[1] ||                          // ensure current min <= current max

			vars[2] > vars[3])                            // ensure new min <= new max

			continue;

		test.Printf(_L("Test changing cache sizes from %u, %u to %u %u\n"),

					vars[0], vars[1], vars[2], vars[3]);

		test_KErrNone(SetCacheSize(PageSize * vars[0], PageSize * vars[1]));

		ThrashPaging(PageSize * vars[1]);

		test_KErrNone(SetCacheSize(PageSize * vars[2], PageSize * vars[3]));

		}

	test_KErrNone(SetCacheSize(originalMin, originalMax));

	// Now test some more specific resizings

	struct

		{

		TUint iMinPages;

		TUint iMaxPages;

		TInt iResult;

		}

	testArgs[] =

		{

			{	K,		K,		KErrNone},

			{	K-4,	K,		KErrNone},

			{	K,		K,		KErrNone},

			{	K,		K*2,	KErrNone},

			{	K,		K,		KErrNone},

			{	K-1,	K,		KErrNone},

			{	K,		K,		KErrNone},

			{	K,		K+1,	KErrNone},

			{	K,		K,		KErrNone},

			{	K+1,	K,		KErrArgument},

			{	K,		K-1,	KErrArgument},

			{	K,		K,		KErrNone},

			{	KMaxTInt,	KMaxTInt,	KErrNoMemory},

			{	K,		K,		KErrNone},

			{	0,		0,		KMaxTInt} // list end marker

		};

	for(TInt j=0; j<2; ++j)

		{

		if(!j)

			test.Next(_L("Changing size of empty VM cache"));

		else

			test.Next(_L("Changing size of full VM cache"));

		TInt i=0;

		while(testArgs[i].iResult!=KMaxTInt)

			{

			TUint min=testArgs[i].iMinPages*PageSize;

			TUint max=testArgs[i].iMaxPages*PageSize;

			TInt result=testArgs[i].iResult;

			if(!j)

				DPTest::FlushCache();

			else

				ThrashPaging(max);

			DoResizeCache(min, max, result, sizeMin, sizeMax, originalMin, originalMax);

			++i;

			}

		}

	test_KErrNone(SetCacheSize(originalMin, originalMax));

	test.End();

	}

void TestResizeVMCache2()

	{

	TUint originalMin = 0;

	TUint originalMax = 0;

	TUint currentSize = 0;

	test_KErrNone(DPTest::CacheSize(originalMax, originalMax, currentSize));

	test_KErrNone(DPTest::SetCacheSize(1, originalMax));

	TUint sizeMin = 0;

	TUint sizeMax = 0;

	test_KErrNone(DPTest::CacheSize(sizeMin, sizeMax, currentSize));

	test(sizeMin > 1);

	test_KErrNone(DPTest::SetCacheSize(originalMin, originalMax));

	}

void TestHAL()

	{

	test.Start(_L("DPTest::Attributes"));

	TUint32 attr=DPTest::Attributes();

	test.Printf(_L("Attributes = %08x\n"),attr);

	test.Next(_L("DPTest::FlushCache"));

	TInt r=DPTest::FlushCache();

	if(r==KErrNotSupported)

		test.Printf(_L("Not Supported\n"));

	else if(r<0)

		{

		test.Printf(_L("Error = %d\n"),r);

		test(0);

		}

	test.Next(_L("DPTest::CacheSize"));

	TUint oldMin = 0;

	TUint oldMax = 0;

	TUint currentSize = 0;

	r=DPTest::CacheSize(oldMin,oldMax,currentSize);

	if(r==KErrNotSupported)

		test.Printf(_L("Not Supported\n"));

	else if(r<0)

		{

		test.Printf(_L("Error = %d\n"),r);

		test(0);

		}

	else

		{

		test.Printf(_L("Size = %dk,%dk,%dk\n"),oldMin>>10,oldMax>>10,currentSize>>10);

		}

	test.Next(_L("DPTest::SetCacheSize"));

	r=DPTest::SetCacheSize(oldMin,oldMax);

	if(r==KErrNotSupported)

		test.Printf(_L("Not Supported\n"));

	else if(r<0)

		{

		test.Printf(_L("Error = %d\n"),r);

		test(0);

		}

	if(r==KErrNone)

		{

		TestResizeVMCache();

		TestResizeVMCache2();

		}

	test.End();

	}

// Test IPC and realtime state

enum TIpcDir

	{

	EServerRead,

	EServerWrite

	};

enum TIpcObjectPaged

	{

	ENothingPaged,

	EDesHeaderPaged,

	EDesContentPaged

	};

enum TRealtimeOutcome

	{

	ENoError,

	EBadDescriptor,

	EServerTerminated,

	ERealtimePanic

	};

class RTestSession : public RSessionBase

	{

public:

	TInt Create(RServer2 aServer)

		{

		return CreateSession(aServer,TVersion(),-1);

		}

	inline TInt Send(const TIpcArgs& aArgs)

		{

		return RSessionBase::SendReceive(0,aArgs);

		}

	};

RServer2 TestServer;

TInt IpcTestServerFunc(TAny* aArg)

	{

	TIpcDir dir = (TIpcDir)(((TInt)aArg) & 0xff);

	TIpcObjectPaged paged = (TIpcObjectPaged)((((TInt)aArg) >> 8) & 0xff);

	User::TRealtimeState realtime = (User::TRealtimeState)((((TInt)aArg) >> 16) & 0xff);

	User::TRealtimeState clientRealtime = (User::TRealtimeState)((((TInt)aArg) >> 24) & 0xff);

	TInt r;

	// We want the server to fault the client when it is realtime 

	// and accessing paged out memory.

	r = TestServer.CreateGlobal(KNullDesC, EIpcSession_Sharable, EServerRole_Default, EServerOpt_PinClientDescriptorsDisable);

	if (r != KErrNone)

		return r;

	RThread::Rendezvous(KErrNone);

	RMessage2 message;

	TestServer.Receive(message);

	if ((clientRealtime == User::ERealtimeStateOn) != message.ClientIsRealtime())

		return KErrGeneral;

	message.Complete(KErrNone); // complete connection request

	TRequestStatus s;

	TestServer.Receive(message,s);

	User::WaitForRequest(s);

	if (s != KErrNone)

		return s.Int();

	TInt32 unpagedContent;

	TPtr8 unpagedDes((TUint8*)&unpagedContent, 4, 4);

	TPtrC8 pagedContentBuf(SmallBuffer,sizeof(TInt));

	TPtr8* dataPagedHeaderDes = (TPtr8*)DataPagedBuffer;

	if (DataPagingSupported)

		new (dataPagedHeaderDes) TPtr8((TUint8*)&unpagedContent, 4);

	TPtr8 dataPagedContentDes(DataPagedBuffer + PageSize, 4);

	r = DPTest::FlushCache();

	if(r != KErrNone)

		return r;

	User::SetRealtimeState(realtime);

	if (dir == EServerRead)

		{

		switch (paged)

			{

			case ENothingPaged:

				r = message.Read(0,unpagedDes);

				break;

			case EDesHeaderPaged:

				r = DataPagingSupported ? message.Read(0,*dataPagedHeaderDes) : KErrNotSupported;

				break;

			case EDesContentPaged:

				r = DataPagingSupported ? message.Read(0,dataPagedContentDes) : KErrNotSupported;

				break;

			default:

				r = KErrArgument;