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; Copyright (c) 2003-2009 Nokia Corporation and/or its subsidiary(-ies).
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; All rights reserved.
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; This component and the accompanying materials are made available
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; under the terms of the License "Eclipse Public License v1.0"
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; which accompanies this distribution, and is available
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; at the URL "http://www.eclipse.org/legal/epl-v10.html".
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;
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; Initial Contributors:
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; Nokia Corporation - initial contribution.
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;
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; Contributors:
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;
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; Description:
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; e32\kernel\arm\bootmain.s
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; Bootstrap main program
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;
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GBLL __BOOTMAIN_S__
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INCLUDE bootcpu.inc
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;
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;*******************************************************************************
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;
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AREA |Boot$$Code|, CODE, READONLY, ALIGN=6
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;
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;*******************************************************************************
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;
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EXPORT TheRomHeader
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TheRomHeader ; this label represents the base of the ROM header
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IF CFG_CustomVectors
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INCLUDE custom_vectors.inc
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ELSE
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; Reset vector
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B ResetEntry
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IF CFG_MMDirect :LAND: (:LNOT: CFG_MMUPresent :LOR: CFG_UseBootstrapVectors)
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B . + KernelCodeOffset ; undef
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B . + KernelCodeOffset ; swi
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B . + KernelCodeOffset ; prefetch
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B . + KernelCodeOffset ; data
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B . + KernelCodeOffset ;
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B . + KernelCodeOffset ; irq
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B . + KernelCodeOffset ; fiq
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ELSE
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IF CFG_DebugBootRom
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IMPORT HandleUndef
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IMPORT HandleSwi
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IMPORT HandleAbtPrefetch
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IMPORT HandleAbtData
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IMPORT HandleRsvdVector
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IMPORT HandleIrq
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IMPORT HandleFiq
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B HandleUndef
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B HandleSwi
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B HandleAbtPrefetch
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B HandleAbtData
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B HandleRsvdVector
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B HandleIrq
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B HandleFiq
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ELSE
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FAULT
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FAULT
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FAULT
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FAULT
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FAULT
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FAULT
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FAULT
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ENDIF
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ENDIF
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ENDIF
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RestartPadBegin
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% 124 - (RestartPadBegin - TheRomHeader)
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; Restart vector - called to reboot under software control
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IMPORT RestartEntry
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B RestartEntry
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; Leave additional space for the rest of the ROM header
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% TRomHeader_sz - 128
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;***************************************************************************************
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; MAIN ENTRY POINT
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; Called on hardware reset
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;***************************************************************************************
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EXPORT ResetEntry
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ResetEntry
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GETCPSR r3 ; cpsr (r3) & r2 MUST be preserved for
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; entry into InitialiseHardware() to
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; allow pre-OS loaders to pass info to
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; bootstrap PSL
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IF :DEF: CFG_BootedInSecureState
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IMPORT SwitchToNonSecureState
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BL SwitchToNonSecureState ; corrupts r0,r1
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ENDIF
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MOV r0, r3
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BIC r0, r0, #0x1f
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ORR r0, r0, #0xd3 ; 32-bit SVC mode, no interrupts
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IF CFG_ARMV6 :LOR: CFG_ARMV7
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ORR r0, r0, #0x100 ; on V6 disable imprecise aborts
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ENDIF
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SETCPSR r0
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ADR r12, TheRomHeader
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;
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; The following call should, at a minimum
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; 1. Determine the hardware configuration
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; 2. Determine the reset reason. If it is wakeup from a low power mode, perform
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; whatever reentry sequence is required and jump back to the kernel.
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; 3. Set up the memory controller so that at least some RAM is available
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; 4. Set R10 to point to the super page or to a temporary version of the super page
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; with at least the following fields valid:
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; iBootTable, iCodeBase, iActiveVariant, iCpuId
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; and optionally:
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; iSmrData
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; 5. In debug builds initialise the debug serial port
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;
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; Enter with:
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; R2 = value as at entry to ResetEntry, preserved unmodified
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; R3 = value of cpsr on entry to ResetEntry
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; R12 = points to TRomHeader
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; NO STACK
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; R14 = return address (as usual)
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;
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; Leave with :
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; R10 = physical address of super page
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;
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; All registers may be modified by this call
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;
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IMPORT InitialiseHardware
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BL InitialiseHardware ; r0..r14 modified
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ADR r12, TheRomHeader
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ADD sp, r10, #CpuBootStackTop ; set up a boot stack
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LDR r0, [r12, #TRomHeader_iDebugPort]
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STR r0, [r10, #SSuperPageBase_iDebugPort] ; set the debug port in the super page
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DEBUG_INIT_STACKS ; r0..r2 modified (if)
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PRTLN "InitialiseHardware use of optional SuperPage fields:"
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IF :DEF: CFG_ENABLE_SMR_SUPPORT ; When defined the bootstrap PSL in InitialiseHardware()
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LDR r0, [r10, #SSuperPageBase_iSmrData] ; must set this field to a valid adderss of the SMRIB or
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; KSuperPageAddressFieldUndefined if no SMRIB found.
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DWORD r0, " SMR_SUPPORT Enabled - iSmrData"
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ELSE
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MVN r0, #0 ; Set iSmrData field to KSuperPageAddressFieldUndefined (-1)
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STR r0, [r10, #SSuperPageBase_iSmrData] ; when SMR feature not supported in ROM image. This is
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DWORD r0, " SMR_SUPPORT Disabled - iSmrData" ; done to ensure kernel-side code can tell if SMRIB exists.
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ENDIF
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IF CFG_BootLoader :LOR: :DEF: CFG_CopyRomToAddress
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; Copy the code to RAM
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PRTLN "Copy code to RAM"
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LDR r0, [r10, #SSuperPageBase_iCodeBase] ; source
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; Two methods of obtaining the destination physical address: either the
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; config.inc can define CFG_CopyRomToAddress as a numeric constant or it
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; will use the romlinearbase for bootloaders.
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IF :DEF: CFG_CopyRomToAddress
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LDR r1, =CFG_CopyRomToAddress ; destination defined in config.inc (must be physical address)
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ELSE
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LDR r1, [r12, #TRomHeader_iRomBase] ; destination defined in header.iby (must be physical address)
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ENDIF
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IF :DEF: CFG_SupportEmulatedRomPaging
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LDR r2, [r12, #TRomHeader_iUncompressedSize]; size of rom
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ELSE
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LDR r2, [r12, #TRomHeader_iPageableRomStart]; size of unpaged part of ROM
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CMP r2, #0
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LDREQ r2, [r12, #TRomHeader_iUncompressedSize]; size if not a pageable rom
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ENDIF
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ADD r2, r2, #0x3
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BIC r2, r2, #0x3 ; make 4byte aligned
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SUB r4, r1, r0 ; save offset destination - source
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DWORD r0, "Source"
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DWORD r1, "Dest"
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DWORD r2, "Size"
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DWORD r4, "Offset"
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ADR lr, ReturnHereAfterCopy
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ADD lr, lr, r4 ; lr = return address in RAM
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B WordMove ; copy the code, return to RAM copy
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LTORG ; Required when CFG_DebugBootRom is enabled
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; WordMove returns to here in RAM
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ReturnHereAfterCopy
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LDR r0, [r10, #SSuperPageBase_iCodeBase] ;
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ADD r0, r0, r4 ;
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STR r0, [r10, #SSuperPageBase_iCodeBase] ; fix up iCodeBase
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LDR r1, [r10, #SSuperPageBase_iBootTable] ;
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ADD r1, r1, r4 ;
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STR r1, [r10, #SSuperPageBase_iBootTable] ; fix up iBootTable
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ADD r12, r12, r4 ; fix up R12 (points to TRomHeader)
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DWORD r0, "New iCodeBase"
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DWORD r1, "New iBootTable"
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DWORD r12, "R12"
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DWORD pc, "PC"
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ENDIF
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LDR r0, [r12, #TRomHeader_iRomRootDirectoryList]
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STR r0, [r10, #SSuperPageBase_iRootDirList]
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LDR r7, [r10, #SSuperPageBase_iBootFlags] ; get boot flags
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BIC r7, r7, #0xff000000
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STR r7, [r10, #SSuperPageBase_iBootFlags] ; clear top 8 bits
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STR r12, [r10, #SSuperPageBase_iRomHeaderPhys]
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; Live registers here are R10, R12, R13
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; Determine the machine RAM configuration
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PRTLN "Determine RAM config"
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ADD r11, r10, #CpuRamTableOffset
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STR r11, [r10, #SSuperPageBase_iRamBootData]
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ADD r0, r10, #CpuRomTableOffset
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STR r0, [r10, #SSuperPageBase_iRomBootData]
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MOV r1, #CpuRamTableTop-CpuRomTableOffset
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MOV r2, #0
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BL WordFill ; zero-fill RAM boot data
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BOOTCALL BTF_RamBanks ; r0 points to list of possible RAM banks
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; in increasing physical address order
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MOV r9, r0 ; into r9
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TestRamBank1
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LDR r1, [r9], #4 ; r1 = physical address of bank
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LDR r8, [r9], #4 ; r8 = size of bank
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DWORD r1, "TRB Base"
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DWORD r8, "TRB Size"
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CMP r8, #0 ; reached end?
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BEQ TestRamBank_End ; branch if end
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TST r1, #RAM_VERBATIM ; if flag set, accept bank verbatim
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BIC r2, r1, #RAM_VERBATIM ; clear flag
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MOVNE r0, r11
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STRNE r2, [r0], #4 ; store base
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STRNE r8, [r0], #4 ; store size
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BNE TestRamBank3 ; do PC check and then next bank
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MVN r3, #0
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BOOTCALL BTF_SetupRamBank ; set width to 32
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BL FindRamBankWidth ; test for presence of RAM
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DWORD r3, "TRB ByteLane"
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CMP r3, #0 ;
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BEQ TestRamBank1 ; if no RAM, try next
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BOOTCALL BTF_SetupRamBank ; set width
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TestRamBank3
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MOV r0, pc ; check if PC is in RAM
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SUBS r0, r0, r1 ; PC - base
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CMPHS r8, r0 ; if PC>=base, check size>(PC-base)
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LDRHI r7, [r10, #SSuperPageBase_iBootFlags] ;
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ORRHI r7, r7, #KBootFlagRunFromRAM ; if so, we are running from RAM
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STRHI r7, [r10, #SSuperPageBase_iBootFlags] ; so set boot flag
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TST r1, #RAM_VERBATIM ; if flag set, accept bank verbatim
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ADDNE r0, r11, #8
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BNE TestRamBank4
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MOV r2, r8 ; r2 = max bank size
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MOV r0, r11 ; r0 = allocator data ptr
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BL FindRamBankConfig ; find blocks
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TestRamBank4
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IF CFG_DebugBootRom
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TestRamBank2
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LDR r1, [r11], #4
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DWORD r1, "Block base"
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LDR r1, [r11], #4
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DWORD r1, "Block size"
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CMP r11, r0
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BLO TestRamBank2
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ENDIF
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MOV r11, r0 ; save allocator data ptr
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B TestRamBank1 ; next bank
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TestRamBank_End
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; Determine the machine ROM configuration
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LDR r11, [r10, #SSuperPageBase_iRomBootData]
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LDR r0, [r10, #SSuperPageBase_iBootFlags]
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TST r0, #KBootFlagRunFromRAM
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BEQ TestRomBanks ; branch if running from ROM
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; ROM is actually in RAM
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PRTLN "Running from RAM"
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IF :DEF: CFG_SupportEmulatedRomPaging
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LDR r8, [r12, #TRomHeader_iUncompressedSize]; r8=size of ROM
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ELSE
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LDR r8, [r12, #TRomHeader_iPageableRomStart]; r8=size of unpaged part of ROM
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CMP r8, #0
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LDREQ r8, [r12, #TRomHeader_iUncompressedSize]; r8=size of ROM if not a pageable rom
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ENDIF
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MVN r2, #0 ; round this up to 64k
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ADD r8, r8, r2, lsr #(32 - CFG_RomSizeAlign)
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BIC r8, r8, r2, lsr #(32 - CFG_RomSizeAlign)
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LDR r9, [r10, #SSuperPageBase_iRamBootData]
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LDR r0, [r10, #SSuperPageBase_iCodeBase] ; running from RAM - ROM base = code base
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LDR r2, [r12, #TRomHeader_iRomBase] ; r2=linear base of ROM block
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MOV r1, r8 ; size of area to excise
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BL ExciseRamArea ; remove RAM which holds image from free list
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LDR r0, [r9, #SRamBank_iSize]
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CMP r0, #0
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BEQ RomInRam1 ; reached end of RAM list - no extension ROM
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LDR r0, [r9, #SRamBank_iBase] ; r0 = next RAM address after kernel ROM image
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BL CheckForExtensionRom ; check for extension ROM
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BEQ RomInRam1 ; skip if not present
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LDR r1, [r0, #TExtensionRomHeader_iUncompressedSize] ; else r1=extension ROM size
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MVN r2, #0 ; round this up to 64k
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ADD r1, r1, r2, lsr #(32 - CFG_RomSizeAlign)
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BIC r1, r1, r2, lsr #(32 - CFG_RomSizeAlign)
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ADD r8, r8, r1 ; accumulate ROM size
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LDR r2, [r0, #TExtensionRomHeader_iRomRootDirectoryList]
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STR r2, [r10, #SSuperPageBase_iRootDirList] ; and update root dir ptr
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LDR r2, [r0, #TExtensionRomHeader_iRomBase] ; r2=linear base of extension ROM block
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BL ExciseRamArea ; remove RAM which holds extension ROM image from free list
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RomInRam1
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B DoneRomBanks ; finished with ROM
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; ROM is actually in ROM or FLASH
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TestRomBanks
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PRTLN "Running from ROM/FLASH"
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BOOTCALL BTF_RomBanks ; r0 points to list of possible ROM banks
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; in increasing physical address order
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MOV r9, r0 ; R9 -> bank list
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MOV r11, #0
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BOOTCALL BTF_SetupRomBank ; do any setup prior to detection
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LDR r11, [r10, #SSuperPageBase_iRomBootData]
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; Walk through list of possible banks
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; Call a setup function for each one
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; This should set up width/wait states if not set by earlier initialisation.
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; It may also do detection of optional banks if required.
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TestRomBank1
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LDMIA r9!, {r1-r4}
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STMIA r11, {r1-r4}
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DWORD r1, "TROMB Base"
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DWORD r2, "TROMB Size"
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DWORD r4, "TROMB LinB"
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CMP r2, #0 ; end of list?
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BEQ CalcRomLinBases ; branch if so
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BOOTCALL BTF_SetupRomBank ; do detection if needed (for optional ROMs)
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LDMIA r11, {r1-r4}
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IF CFG_DebugBootRom
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DWORD r1, "TROMB PostDet Base"
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DWORD r2, "TROMB PostDet Size"
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DWORD r4, "TROMB PostDet LinB"
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ENDIF
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CMP r2, #0
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ADDNE r11, r11, #SRomBank_sz ; if bank present, increment r11
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B TestRomBank1
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CalcRomLinBases
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LDR r11, [r10, #SSuperPageBase_iRomBootData]
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MOV r8, #0 ; total ROM size
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CalcRomLinBases1
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LDMIA r11!, {r0,r2-r4} ; r0=phys base, r2=size, r4=lin base
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DWORD r0, "CRLB Base"
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DWORD r2, "CRLB Size"
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DWORD r4, "CRLB LinB"
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CMP r2, #0 ; reached end?
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BEQ CalcRomLinBases_End
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ADD r8, r8, r2 ; accumulate size
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IF CFG_MMUPresent
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CMP r4, #0 ; lin addr override?
|
|
378 |
MOVNE r9, r4 ; if so, take it
|
|
379 |
ELSE
|
|
380 |
MOV r9, r0 ; if no MMU, lin = phys
|
|
381 |
ENDIF
|
|
382 |
SUBS r1, r12, r0 ; check if this is boot block - R1=rom header phys-base
|
|
383 |
CMPHS r2, r1 ; if rom hdr phys>=base, compare size with rom header phys-base
|
|
384 |
IF CFG_MMUPresent
|
|
385 |
LDRHI r9, [r12, #TRomHeader_iRomBase] ; linear base of boot ROM (= lin addr of rom header)
|
|
386 |
SUBHI r9, r9, r1 ; calculate linear address corresponding to base of ROM block
|
|
387 |
ENDIF
|
|
388 |
BHI CalcRomLinBases2 ; skip if boot block
|
|
389 |
BL CheckForExtensionRom ; else check if this is extension ROM
|
|
390 |
BEQ CalcRomLinBases2 ; skip if not
|
|
391 |
IF CFG_MMUPresent
|
|
392 |
LDR r9, [r0, #TExtensionRomHeader_iRomBase] ; if it is, take linear address override
|
|
393 |
ENDIF
|
|
394 |
LDR r1, [r0, #TExtensionRomHeader_iRomRootDirectoryList]
|
|
395 |
STR r1, [r10, #SSuperPageBase_iRootDirList] ; and update root dir ptr
|
|
396 |
CalcRomLinBases2
|
|
397 |
DWORD r9, "CRLB Final Linear Base"
|
|
398 |
STR r9, [r11, #-4] ; write final linear base
|
|
399 |
IF CFG_MMUPresent
|
|
400 |
ADD r9, r9, r2 ; and step on by size
|
|
401 |
ENDIF
|
|
402 |
B CalcRomLinBases1 ; do next bank
|
|
403 |
CalcRomLinBases_End
|
|
404 |
|
|
405 |
DoneRomBanks
|
|
406 |
STR r8, [r10, #SSuperPageBase_iTotalRomSize] ; save total ROM size
|
|
407 |
|
|
408 |
; Support for areas?
|
|
409 |
; Put it here if needed.
|
|
410 |
|
|
411 |
; RAM reservation/pre-allocation section
|
|
412 |
;
|
|
413 |
; SSuperPageBase_iRamBootData member points to two arrays/lists that are
|
|
414 |
; used to initialise the kernel RAM Allocator. On entry to this section the
|
|
415 |
; list contains the free RAM regions and no pre-allocations:
|
|
416 |
; <free ram region><...><null entry><null entry>
|
|
417 |
;
|
|
418 |
; On exit from this section pre-allocated entries may have been added:
|
|
419 |
; <free ram region><><null entry><pre-allocated ram region><><null entry>
|
|
420 |
;
|
|
421 |
; - Setup R11 to point to free entry after first null entry in iRamBootData list
|
|
422 |
; - Reserve any SMRs in the SP SMRIB by adding them to the pre-allocation list
|
|
423 |
; - Call the bootstrap PSL to allow futher platform specific RAM reservation
|
|
424 |
;
|
|
425 |
|
|
426 |
; Point R11 to preallocated block list
|
|
427 |
LDR r11, [r10, #SSuperPageBase_iRamBootData]
|
|
428 |
3
|
|
429 |
LDMIA r11!, {r0,r1}
|
|
430 |
CMP r1, #0
|
|
431 |
BNE %BT3
|
|
432 |
|
|
433 |
; At this point in bootstrap:
|
|
434 |
; r10 = pointer to super page (SP)
|
|
435 |
; r11 = address of first pre-alloc SRamBank after first terminator entry
|
|
436 |
; r12 = pointer to ROM header
|
|
437 |
; r13 = stack pointer
|
|
438 |
|
|
439 |
; Reserve SMR memory blocks, if SMRIB valid in super page
|
|
440 |
|
|
441 |
MOV r6, #0 ; Setup r6 to count SMRIB entries for trace
|
|
442 |
LDR r5, [r10, #SSuperPageBase_iSmrData]
|
|
443 |
CMN r5, #1 ; Compare to KSuperPageAddressFieldUndefined
|
|
444 |
BCS NoSMRIB ; jump over if no SMRIB
|
|
445 |
PRTLN "Processing (any) SMRIB..."
|
|
446 |
4
|
|
447 |
LDMIA r5, {r0, r1} ; load iBase and iSize members
|
|
448 |
ADD r5, r5, #SSmrBank_sz ; Skip the two other members, inc R5 to next entry
|
|
449 |
CMP r1, #0
|
|
450 |
BEQ DoneSMRReservation ; Jump out of loop if no more SMRs
|
|
451 |
|
|
452 |
MVN r3, #0
|
|
453 |
ANDS r2, r1, r3, LSR #20
|
|
454 |
FAULT NE ; Fault if SMR Size is not multiple of 4Kb
|
|
455 |
|
|
456 |
STMIA r11!, {r0, r1} ; Add SMR to pre-alloc list
|
|
457 |
ADD r6, r6, #1
|
|
458 |
B %BT4
|
|
459 |
; No need to add null entry as the
|
|
460 |
DoneSMRReservation ; SRamBank area has been zero filled
|
|
461 |
|
|
462 |
CMP r6, #0
|
|
463 |
BNE %FT5
|
|
464 |
PRTLN "PSL created SMRIB of zero size!"
|
|
465 |
B NoSMRIB
|
|
466 |
5
|
|
467 |
DWORD r6, "PSL created SMRIB of X entries"
|
|
468 |
IF CFG_DebugBootRom
|
|
469 |
PRTLN "SMRIB Memory Dump:"
|
|
470 |
LDR r5, [r10, #SSuperPageBase_iSmrData]
|
|
471 |
MOV r6, r6, LSL #4
|
|
472 |
MEMDUMP r5, r6
|
|
473 |
ENDIF
|
|
474 |
|
|
475 |
NoSMRIB
|
|
476 |
|
|
477 |
; Here r11 points to the null terminator of the preallocated block list
|
|
478 |
|
|
479 |
; Reserve any platform-dependent extra physical memory here.
|
|
480 |
; Two methods are available:
|
|
481 |
; 1. ExciseRamArea - the kernel will then not treat the region as RAM
|
|
482 |
; 2. Add preallocation regions to the RAM bank list. R11 has been set
|
|
483 |
; to point to the first of these. List is terminated by a zero size.
|
|
484 |
; The kernel will treat these regions as RAM.
|
|
485 |
;
|
|
486 |
BOOTCALL BTF_Reserve
|
|
487 |
|
|
488 |
IF CFG_DebugBootRom
|
|
489 |
; In debug, dump ROM and RAM bank config
|
|
490 |
PRTLN "ROM and RAM config:"
|
|
491 |
LDR r11, [r10, #SSuperPageBase_iRomBootData]
|
|
492 |
MOV r1, #CpuRamTableTop-CpuRomTableOffset
|
|
493 |
MEMDUMP r11, r1
|
|
494 |
ENDIF
|
|
495 |
|
|
496 |
; Calculate total RAM size
|
|
497 |
LDR r11, [r10, #SSuperPageBase_iRamBootData]
|
|
498 |
MOV r9, #0
|
|
499 |
AccumulateRamSize
|
|
500 |
LDMIA r11!, {r0,r1}
|
|
501 |
ADD r9, r9, r1
|
|
502 |
CMP r1, #0
|
|
503 |
BNE AccumulateRamSize
|
|
504 |
DWORD r9, "TotalRamSize"
|
|
505 |
STR r9, [r10, #SSuperPageBase_iTotalRamSize]
|
|
506 |
|
|
507 |
; RAM reservation/pre-allocation section end
|
|
508 |
;
|
|
509 |
|
|
510 |
; find the kernel image and point R11 to it
|
|
511 |
PRTLN "Find primary"
|
|
512 |
BL FindPrimary
|
|
513 |
STR r11, [sp, #-4]!
|
|
514 |
|
|
515 |
IF CFG_MMDirect
|
|
516 |
; direct model - work out the end of the kernel memory area
|
|
517 |
LDR r8, [r12, #TRomHeader_iKernelLimit] ; end of kernel heap, rounded up to 4K
|
|
518 |
IF CFG_MMUPresent
|
|
519 |
GETPARAM BPR_PageTableSpace, DefaultPTAlloc ; get reserved space for page tables
|
|
520 |
ADD r8, r8, r0 ; add space for page tables
|
|
521 |
IF :LNOT: :DEF: CFG_MinimiseKernelHeap
|
|
522 |
MVN r1, #0
|
|
523 |
ADD r8, r8, r1, LSR #12
|
|
524 |
BIC r8, r8, r1, LSR #12 ; round up to 1Mb to give limit
|
|
525 |
ENDIF
|
|
526 |
ENDIF
|
|
527 |
STR r8, [r10, #SSuperPageBase_iKernelLimit]
|
|
528 |
DWORD r8, "Kernel Limit"
|
|
529 |
|
|
530 |
GETPARAM BPR_KernDataOffset, SuperCpuSize ; get kernel data offset into R0 with default
|
|
531 |
LDR r2, [r12, #TRomHeader_iKernDataAddress] ;
|
|
532 |
SUB r0, r2, r0 ; r0 = super page linear address
|
|
533 |
DWORD r0, "SuperPageLin"
|
|
534 |
|
|
535 |
IF CFG_BootLoader
|
|
536 |
|
|
537 |
; for bootloader calculate linear RAM base as:
|
|
538 |
; 1. TRomHeader::iKernDataAddress - KernDataOffset if BootLdr_ImgAddr > physical RAM base
|
|
539 |
; 2. TRomHeader::iKernDataAddress - KernDataOffset - X if BootLdr_ImgAddr = physical RAM base
|
|
540 |
; where X = amount of physical RAM preceding the super page in physical address order
|
|
541 |
; physical address of super page is chosen to allow BootLdr_ExtraRAM (usually 1Mb) of 'user' RAM
|
|
542 |
|
|
543 |
MOV r2, r0 ; r2 = super page lin
|
|
544 |
GETMPARAM BPR_BootLdrImgAddr ; R0 = image physical address
|
|
545 |
LDR r8, [r10, #SSuperPageBase_iRamBootData]
|
|
546 |
LDR r3, [r8, #0] ; r3 = physical RAM base
|
|
547 |
CMP r0, r3
|
|
548 |
MOV r0, r2 ;
|
|
549 |
BHI SuperPageAtBeginning ; if boot image not at RAM base, put super page there
|
|
550 |
LDR r1, [r12, #TRomHeader_iUserDataAddress] ; 'user' linear address
|
|
551 |
MOV r2, r0 ; r2 = super page lin
|
|
552 |
GETPARAM BPR_BootLdrExtraRAM, 0x100000 ; get extra RAM size into R0, default to 1M
|
|
553 |
ADD r1, r1, r0 ; linear top of RAM
|
|
554 |
SUB r1, r1, r2 ; r1 = total amount of RAM reserved at top
|
|
555 |
DWORD r1, "ReserveAtTop"
|
|
556 |
LDR r0, [r10, #SSuperPageBase_iTotalRamSize] ; r0 = total physical RAM size
|
|
557 |
SUB r0, r0, r1 ; r2 = physical RAM below super page
|
|
558 |
DWORD r0, "RamBelowSuperPage"
|
|
559 |
SUB r0, r2, r0 ; r0 = linear RAM base
|
|
560 |
|
|
561 |
ENDIF ; CFG_BootLoader
|
|
562 |
; for non-bootloader, iRamBase = TRomHeader::iKernDataAddress - KernDataOffset
|
|
563 |
SuperPageAtBeginning
|
|
564 |
STR r0, [r10, #SSuperPageBase_iRamBase]
|
|
565 |
DWORD r0, "iRamBase"
|
|
566 |
|
|
567 |
ENDIF
|
|
568 |
|
|
569 |
; initialise the RAM allocator
|
|
570 |
PRTLN "Init RAM allocator"
|
|
571 |
MOV r2, #BMA_Init
|
|
572 |
BOOTCALL BTF_Alloc
|
|
573 |
|
|
574 |
; get the final super page physical address
|
|
575 |
MOV r2, #BMA_SuperCPU
|
|
576 |
BOOTCALL BTF_Alloc
|
|
577 |
DWORD r0, "Final SuperPage Phys"
|
|
578 |
|
|
579 |
; if super page has moved, relocate it
|
|
580 |
CMP r0, r10
|
|
581 |
BLNE RelocateSuperPage
|
|
582 |
LDR r11, [sp], #4 ; recover kernel image pointer
|
|
583 |
|
|
584 |
IF CFG_MMUPresent
|
|
585 |
|
|
586 |
; initialise the memory mapping system
|
|
587 |
PRTLN "InitMemMapSystem"
|
|
588 |
BL InitMemMapSystem
|
|
589 |
|
|
590 |
; map the ROM
|
|
591 |
PRTLN "Map ROM"
|
|
592 |
LDR r9, [r10, #SSuperPageBase_iRomBootData]
|
|
593 |
|
|
594 |
MapRomBlock
|
|
595 |
LDR r0, [r9, #SRomBank_iLinBase] ; r0 = linear base
|
|
596 |
LDR r1, [r9, #SRomBank_iBase] ; r1 = physical base
|
|
597 |
LDR r3, [r9, #SRomBank_iSize] ; r3 = size
|
|
598 |
MOV r2, #BTP_Rom ; r2 = access permissions
|
|
599 |
MOV r4, #20 ; r4 = log2(max page size)
|
|
600 |
CMP r3, #0
|
|
601 |
BEQ MapRomDone ; branch out if reached end of list
|
|
602 |
BL MapContiguous
|
|
603 |
ADD r9, r9, #SRomBank_sz
|
|
604 |
B MapRomBlock
|
|
605 |
MapRomDone
|
|
606 |
|
|
607 |
|
|
608 |
IF CFG_MMDirect
|
|
609 |
|
|
610 |
; direct model - map all RAM in one block, starting at SSuperPageBase::iRamBase
|
|
611 |
; permissions are kernel up to the end of the kernel heap, user after
|
|
612 |
; also map non-kernel RAM at its physical address, uncached
|
|
613 |
PRTLN "Direct Map RAM"
|
|
614 |
LDR r8, [r10, #SSuperPageBase_iKernelLimit] ; top of kernel area (linear)
|
|
615 |
LDR r9, [r10, #SSuperPageBase_iRamBootData]
|
|
616 |
MOV r2, #BTP_Kernel ; start with kernel access permissions
|
|
617 |
MOV r4, #20
|
|
618 |
LDR r0, [r10, #SSuperPageBase_iRamBase] ; linear address
|
|
619 |
DWORD r0, "Direct Map RAM Base"
|
|
620 |
MapRamBlock
|
|
621 |
LDMIA r9!, {r1,r5} ; r1 = bank physical base, r5 = bank size
|
|
622 |
CMP r5, #0 ; reached end of list?
|
|
623 |
BEQ MapRamBlock_End ; jump if end
|
|
624 |
DWORD r1, "Bank base"
|
|
625 |
DWORD r5, "Bank size"
|
|
626 |
SUBS r3, r8, r0 ; r3 = kernel limit - base
|
|
627 |
MOVLO r3, r5 ; if base>=kernel limit, size to map = bank size
|
|
628 |
BLO MapUserRamBlock ; if base>=kernel limit, map user
|
|
629 |
CMP r3, r5 ; kernel area >= size?
|
|
630 |
MOVHS r3, r5 ; if so, size to map = bank size
|
|
631 |
BHS MapKernelRamBlock ; and map kernel block
|
|
632 |
BL MapContiguous ; else map size r3 as kernel
|
|
633 |
ADD r0, r0, r3 ; increment linear address
|
|
634 |
ADD r1, r1, r3 ; increment physical address
|
|
635 |
SUB r3, r5, r3 ; remaining size of bank
|
|
636 |
MapUserRamBlock
|
|
637 |
MOV r2, #BTP_User ; change to user permissions
|
|
638 |
BL MapContiguous ; Map bank
|
|
639 |
ADD r0, r0, r3 ; increment linear address
|
|
640 |
STMFD sp!, {r0} ; save linear address
|
|
641 |
MOV r0, r1 ; linear = physical
|
|
642 |
MOV r2, #BTP_Uncached ; map as uncached user
|
|
643 |
BL MapContiguous
|
|
644 |
LDMFD sp!, {r0} ; recover linear address
|
|
645 |
B MapRamBlock
|
|
646 |
MapKernelRamBlock
|
|
647 |
BL MapContiguous ; Map bank
|
|
648 |
ADD r0, r0, r3 ; increment linear address
|
|
649 |
B MapRamBlock
|
|
650 |
MapRamBlock_End
|
|
651 |
|
|
652 |
ELSE
|
|
653 |
|
|
654 |
; moving or multiple model
|
|
655 |
|
|
656 |
; map super page + CPU page
|
|
657 |
PRTLN "Map super/CPU pages"
|
|
658 |
MOV r0, #KSuperPageLinAddr ; linear
|
|
659 |
MOV r1, r10 ; physical
|
|
660 |
MOV r2, #BTP_SuperCPU ; permissions
|
|
661 |
MOV r3, #SuperCpuSize ; size
|
|
662 |
MOV r4, #12 ; map size
|
|
663 |
BL MapContiguous
|
|
664 |
|
|
665 |
; allocate one page for page table info and map it
|
|
666 |
PRTLN "Map PTINFO"
|
|
667 |
LDR r0, =KPageTableInfoBase ; linear
|
|
668 |
MOV r2, #BTP_PtInfo ; permissions
|
|
669 |
MOV r3, #0x1000 ; size
|
|
670 |
MOV r4, #12 ; map size
|
|
671 |
BL AllocAndMap
|
|
672 |
|
|
673 |
ENDIF ; CFG_MMDirect
|
|
674 |
|
|
675 |
IF CFG_MMMultiple
|
|
676 |
|
|
677 |
; on multiple model, map ASID info area
|
|
678 |
PRTLN "Map ASID info"
|
|
679 |
LDR r0, =KAsidInfoBase ; linear
|
|
680 |
MOV r2, #BTP_PtInfo ; permissions
|
|
681 |
MOV r3, #0x1000 ; size
|
|
682 |
MOV r4, #12 ; map size
|
|
683 |
BL AllocAndMap
|
|
684 |
|
|
685 |
ENDIF
|
|
686 |
|
|
687 |
IF CFG_MMFlexible
|
|
688 |
|
|
689 |
; on flexible model, map page array segment area
|
|
690 |
PRTLN "Map PageArrayGroup"
|
|
691 |
LDR r0, =KPageArraySegmentBase ; linear
|
|
692 |
MOV r2, #BTP_Kernel ; permissions
|
|
693 |
MOV r3, #0x1000 ; size
|
|
694 |
MOV r4, #12 ; map size
|
|
695 |
BL AllocAndMap
|
|
696 |
|
|
697 |
ENDIF
|
|
698 |
|
|
699 |
; map hardware
|
|
700 |
PRTLN "Map HW"
|
|
701 |
BOOTCALL BTF_HwBanks ; get pointer to list of HW banks into r0
|
|
702 |
MOV r9, r0 ; into r9
|
|
703 |
IF :LNOT: CFG_MMDirect
|
|
704 |
MOV r0, #KPrimaryIOBase ; linear address for HW
|
|
705 |
ENDIF
|
|
706 |
|
|
707 |
IF :DEF: CFG_HasL210Cache :LOR: :DEF: CFG_HasL220Cache :LOR: :DEF: CFG_HasPL310Cache
|
|
708 |
MOV r7, #0 ; Flag to indicate if H/W bank that matches SSuperPageBase::iArmL2CacheBase is found.
|
|
709 |
; When found, we should stop searching. (Otherwise could be fatal if linear address of
|
|
710 |
; External Cache Controller accidentally matches physical address of a H/W bank.)
|
|
711 |
ENDIF
|
|
712 |
MapHwBank
|
|
713 |
LDR r1, [r9], #4 ; get phys addr / size
|
|
714 |
DWORD r1, "HwBank Entry"
|
|
715 |
MVN r14, #0
|
|
716 |
ANDS r3, r1, #HW_SIZE_MASK ; r3 = bottom 8 bits = #pages
|
|
717 |
BEQ MapHwBank_End ; jump out if end of list (number of pages = 0)
|
|
718 |
MOV r3, r3, LSL #12 ; pages -> bytes
|
|
719 |
AND r4, r1, #HW_MULT_MASK
|
|
720 |
CMP r4, #HW_MULT_64K
|
|
721 |
MOVEQ r3, r3, LSL #4 ; if MULT_64K, multiply page count by 16
|
|
722 |
MOVEQ r4, #16 ; and use 64K pages
|
|
723 |
MOVHI r3, r3, LSL #8 ; if MULT_1M, multiply page count by 256
|
|
724 |
MOVHI r4, #20 ; and use 1M pages
|
|
725 |
MOVLO r4, #12 ; otherwise use 4K pages
|
|
726 |
TST r1, #HW_MAP_EXT2 ; linear address specified?
|
|
727 |
LDRNE r6, [r9], #4 ; if so get it from next descriptor word
|
|
728 |
TST r1, #HW_MAP_EXT ; extended mapping?
|
|
729 |
LDRNE r2, [r9], #4 ; if so, get permissions from next descriptor word
|
|
730 |
MOVEQ r2, #BTP_Hw ; else use standard HW permissions
|
|
731 |
TST r1, #HW_MAP_EXT2 ; linear address specified?
|
|
732 |
AND r1, r1, r14, LSL #12 ; r1 = top 20 bits = physical address
|
|
733 |
BNE MapHwBank2 ; branch if linear address specified
|
|
734 |
IF CFG_MMDirect
|
|
735 |
MOV r0, r1 ; linear = physical
|
|
736 |
ELSE
|
|
737 |
MVN r6, r14, LSL r4 ; r6 = 2^r4-1
|
|
738 |
ADD r0, r0, r6
|
|
739 |
BIC r0, r0, r6 ; round up linear address
|
|
740 |
ENDIF
|
|
741 |
|
|
742 |
IF :DEF: CFG_HasL210Cache :LOR: :DEF: CFG_HasL220Cache :LOR: :DEF: CFG_HasPL310Cache
|
|
743 |
CMP r7, #0
|
|
744 |
LDREQ r5, [r10, #SSuperPageBase_iArmL2CacheBase] ; get L2 cache controller base address from super page
|
|
745 |
CMPEQ r1,r5 ; if physical address matches ...
|
|
746 |
STREQ r0, [r10, #SSuperPageBase_iArmL2CacheBase] ; ...set linear address in super page
|
|
747 |
MOVEQ r7, #1 ; mark that L2CacheBase PhysToLinear transfer is completed
|
|
748 |
ENDIF
|
|
749 |
BL MapContiguous ; make mapping
|
|
750 |
ADD r0, r0, r3 ; increment linear address
|
|
751 |
B MapHwBank ; next bank
|
|
752 |
MapHwBank2
|
|
753 |
STR r0, [sp, #-4]! ; save default linear address
|
|
754 |
MOV r0, r6 ; r0 = specified linear address
|
|
755 |
|
|
756 |
IF :DEF: CFG_HasL210Cache :LOR: :DEF: CFG_HasL220Cache :LOR: :DEF: CFG_HasPL310Cache
|
|
757 |
CMP r7, #0
|
|
758 |
LDREQ r5, [r10, #SSuperPageBase_iArmL2CacheBase] ; get L2 cache controller base address from super page
|
|
759 |
CMPEQ r1,r5 ; if physical address matches ...
|
|
760 |
STREQ r0, [r10, #SSuperPageBase_iArmL2CacheBase] ; ...set linear address in super page
|
|
761 |
MOVEQ r7, #1 ; mark that L2CacheBase PhysToLinear transfer is completed
|
|
762 |
ENDIF
|
|
763 |
BL MapContiguous ; make mapping
|
|
764 |
LDR r0, [sp], #4 ; restore default linear address
|
|
765 |
B MapHwBank ; next bank
|
|
766 |
|
|
767 |
MapHwBank_End
|
|
768 |
|
|
769 |
; dummy uncached mapping
|
|
770 |
PRTLN "Setup dummy uncached"
|
|
771 |
IF CFG_MMDirect
|
|
772 |
GETMPARAM BPR_UncachedLin ; linear address into R0
|
|
773 |
MOV r3, #0x1000 ; 4K
|
|
774 |
MOV r4, #12 ; small page
|
|
775 |
ADD r1, r10, #0x2000 ; physical
|
|
776 |
ELSE
|
|
777 |
LDR r0, =KDummyUncachedAddr ; linear address into R0
|
|
778 |
MOV r3, #0x1000 ; 4K
|
|
779 |
MOV r4, #12 ; small page
|
|
780 |
MOV r1, r10 ; physical = super page physical
|
|
781 |
ENDIF
|
|
782 |
MOV r2, #BTP_Uncached ; permissions
|
|
783 |
STR r0, [r10, #SSuperPageBase_iUncachedAddress]
|
|
784 |
IF CFG_MMUPresent :LAND: :LNOT: CFG_MMDirect
|
|
785 |
BL AllocAndMap
|
|
786 |
ELSE
|
|
787 |
BL MapContiguous
|
|
788 |
ENDIF
|
|
789 |
|
|
790 |
IF CFG_MMDirect
|
|
791 |
IF SMP
|
|
792 |
|
|
793 |
; AP Boot Page
|
|
794 |
GETMPARAM BPR_APBootLin ; linear address into R0
|
|
795 |
DWORD r0, "APBootPageLin"
|
|
796 |
STR r0, [r10, #SSuperPageBase_iAPBootPageLin]
|
|
797 |
MOV r3, #0x1000 ; 4K
|
|
798 |
MOV r4, #12 ; small page
|
|
799 |
ADD r1, r10, #0x3000 ; physical
|
|
800 |
DWORD r1, "APBootPagePhys"
|
|
801 |
STR r1, [r10, #SSuperPageBase_iAPBootPagePhys]
|
|
802 |
MOV r2, #BTP_Uncached ; permissions
|
|
803 |
BL MapContiguous
|
|
804 |
MOV r0, r1
|
|
805 |
MOV r1, #0x1000
|
|
806 |
MOV r2, #0
|
|
807 |
BL WordFill ; clear AP Boot Page
|
|
808 |
ENDIF
|
|
809 |
ENDIF
|
|
810 |
|
|
811 |
IF CFG_MMDirect :LAND: CFG_UseBootstrapVectors
|
|
812 |
STR r12, [sp, #-4]! ; exc phys = ROM header phys
|
|
813 |
ELSE
|
|
814 |
LDR r0, [r11, #TRomImageHeader_iCodeAddress] ; r0 = kernel code base linear
|
|
815 |
DWORD r0, "KernCodeLin"
|
|
816 |
BL RomLinearToPhysical ; r0 = kernel code base physical
|
|
817 |
DWORD r0, "KernCodePhys"
|
|
818 |
STR r0, [sp, #-4]! ; save it
|
|
819 |
ENDIF
|
|
820 |
|
|
821 |
PRTLN "Switch to virtual"
|
|
822 |
BL SwitchToVirtual ; SWITCH TO VIRTUAL ADDRESSES
|
|
823 |
|
|
824 |
; map the exception vectors
|
|
825 |
PRTLN "Map vectors"
|
|
826 |
MRC p15, 0, r0, c1, c0, 0 ; R0 = MMUCR
|
|
827 |
TST r0, #MMUCR_V ; HIVECS?
|
|
828 |
MOV r0, #0 ; if not, linear = 0
|
|
829 |
SUBNE r0, r0, #0x10000 ; else linear = 0xFFFF0000
|
|
830 |
LDR r1, [sp], #4 ; physical
|
|
831 |
IF CFG_MMDirect
|
|
832 |
CMP r1, r0 ; in direct model, if lin = phys mapping is already there
|
|
833 |
BEQ SkipMapExcVectors
|
|
834 |
ENDIF
|
|
835 |
MOV r2, #BTP_Vector ; permissions
|
|
836 |
MOV r3, #0x1000 ; map size
|
|
837 |
MOV r4, #12 ; page size
|
|
838 |
BL MapContiguous
|
|
839 |
SkipMapExcVectors
|
|
840 |
|
|
841 |
ELSE ; CFG_MMUPresent
|
|
842 |
|
|
843 |
GETMPARAM BPR_UncachedLin ; address into R0
|
|
844 |
STR r0, [r10, #SSuperPageBase_iUncachedAddress]
|
|
845 |
|
|
846 |
ENDIF ; CFG_MMUPresent
|
|
847 |
|
|
848 |
; get initial thread stack size
|
|
849 |
MVN r9, #0
|
|
850 |
LDR r8, [r11, #TRomImageHeader_iStackSize] ; kernel stack size
|
|
851 |
ADD r8, r8, r9, LSR #20
|
|
852 |
BIC r8, r8, r9, LSR #20 ; round up to 4K
|
|
853 |
DWORD r8, "InitStackSize"
|
|
854 |
|
|
855 |
IF :LNOT: CFG_MMDirect
|
|
856 |
|
|
857 |
; calculate initial size of kernel heap, needs to be just enough to allow the device to
|
|
858 |
; boot past the point where the kernel heap is mutated to be growable.
|
|
859 |
LDR r3, [r10, #SSuperPageBase_iTotalRamSize] ; total RAM size
|
|
860 |
LDR r2, [r11, #TRomImageHeader_iHeapSizeMin] ; kernel heap size min
|
|
861 |
IF :DEF: CFG_MMFlexible
|
|
862 |
; Flexible memory model requires approx. 2 bytes per RAM page.
|
|
863 |
MOV r3, r3, LSR #11 ; Total RAM size in half pages
|
|
864 |
ELSE
|
|
865 |
; Other memory models require approx. 1 byte per RAM page.
|
|
866 |
MOV r3, r3, LSR #12 ; Total RAM size in pages
|
|
867 |
ENDIF
|
|
868 |
IF :DEF: CFG_KernelHeapMultiplier
|
|
869 |
LDR r0, =CFG_KernelHeapMultiplier ; multiplier * 16
|
|
870 |
MUL r3, r0, r3
|
|
871 |
MOV r3, r3, LSR #4
|
|
872 |
ENDIF
|
|
873 |
IF :DEF: CFG_KernelHeapBaseSize
|
|
874 |
LDR r0, =CFG_KernelHeapBaseSize
|
|
875 |
ADD r3, r3, r0 ; add base size specified in config.inc
|
|
876 |
ELSE
|
|
877 |
ADD r3, r3, #48*1024 ; add default base size of 48K
|
|
878 |
; was 24K on 15/07/09, increased after H2 test ROM exceed this
|
|
879 |
ENDIF
|
|
880 |
DWORD r3, "CalcInitHeap"
|
|
881 |
DWORD r2, "SpecInitHeap"
|
|
882 |
CMP r3, r2
|
|
883 |
MOVLS r3, r2 ; if ROMBUILD specified figure higher, use it
|
|
884 |
ADD r3, r3, r9, LSR #20
|
|
885 |
BIC r3, r3, r9, LSR #20 ; round up to 4K
|
|
886 |
DWORD r3, "preliminary InitHeap"
|
|
887 |
|
|
888 |
; map kernel .data/.bss, initial thread stack and kernel heap
|
|
889 |
LDR r7, [r12, #TRomHeader_iTotalSvDataSize] ; total size of kernel .data / .bss
|
|
890 |
ADD r7, r7, r9, LSR #20
|
|
891 |
BIC r7, r7, r9, LSR #20 ; round up to 4K
|
|
892 |
DWORD r7, "Rounded SvData"
|
|
893 |
LDR r0, [r12, #TRomHeader_iKernDataAddress] ; linear address
|
|
894 |
MOV r2, #BTP_Kernel ; permissions
|
|
895 |
ADD r3, r3, r8 ; size = heap size + stack size + data/bss size
|
|
896 |
ADD r3, r3, r7
|
|
897 |
IF :LNOT: :DEF: CFG_MinimiseKernelHeap
|
|
898 |
ADD r3, r3, r9, LSR #16
|
|
899 |
BIC r3, r3, r9, LSR #16 ; round total up to 64K
|
|
900 |
ENDIF
|
|
901 |
DWORD r3, "Total SvHeap"
|
|
902 |
SUB r4, r3, r8 ; subtract stack size
|
|
903 |
SUB r4, r4, r7 ; subtract data/bss size
|
|
904 |
STR r4, [r10, #SSuperPageBase_iInitialHeapSize] ; save in super page
|
|
905 |
DWORD r4, "InitHeap"
|
|
906 |
MOV r4, #16 ; use 64k pages, 1mb fails when converted to DChunk
|
|
907 |
PRTLN "Map stack/heap"
|
|
908 |
BL AllocAndMap
|
|
909 |
|
|
910 |
ELSE ; CFG_MMDirect
|
|
911 |
|
|
912 |
LDR r7, [r12, #TRomHeader_iTotalSvDataSize] ; total size of kernel .data / .bss
|
|
913 |
ADD r7, r7, r9, LSR #20
|
|
914 |
BIC r7, r7, r9, LSR #20 ; round up to 4K
|
|
915 |
DWORD r7, "Rounded SvData"
|
|
916 |
LDR r3, [r11, #TRomImageHeader_iHeapSizeMax] ; kernel heap max
|
|
917 |
STR r3, [r10, #SSuperPageBase_iInitialHeapSize] ; save in super page
|
|
918 |
DWORD r3, "InitHeap"
|
|
919 |
|
|
920 |
ENDIF ; CFG_MMDirect
|
|
921 |
|
|
922 |
; fill initial thread stack with 0xff
|
|
923 |
|
|
924 |
LDR r0, [r12, #TRomHeader_iKernDataAddress] ; linear address
|
|
925 |
ADD r0, r0, r7 ; = data address + size of data/bss
|
|
926 |
DWORD r0, "Initial stack base"
|
|
927 |
MOV r1, r8 ; size
|
|
928 |
MVN r2, #0 ; fill value
|
|
929 |
BL WordFill
|
|
930 |
|
|
931 |
; switch to initial thread stack
|
|
932 |
|
|
933 |
DWORD r0, "Initial SP"
|
|
934 |
MOV sp, r0
|
|
935 |
|
|
936 |
; initialise kernel .data and .bss
|
|
937 |
|
|
938 |
PRTLN "Init .data/.bss"
|
|
939 |
LDR r0, [r11, #TRomImageHeader_iDataAddress] ; source address
|
|
940 |
DWORD r0, "Kernel .data source"
|
|
941 |
LDR r1, [r12, #TRomHeader_iKernDataAddress] ; destination address
|
|
942 |
DWORD r1, "Kernel .data dest"
|
|
943 |
LDR r2, [r11, #TRomImageHeader_iDataSize] ; size of .data
|
|
944 |
DWORD r2, "Kernel .data size"
|
|
945 |
ADD r2, r2, #3
|
|
946 |
BIC r2, r2, #3 ; round to multiple of 4
|
|
947 |
ADD r4, r1, r2 ; base address of .bss
|
|
948 |
DWORD r4, "Kernel .bss dest"
|
|
949 |
DWORD r7, "TotalSvDataSize" ; total data/bss size rounded up to 4K
|
|
950 |
SUB r5, r7, r2 ; size of .bss
|
|
951 |
DWORD r5, "Kernel .bss size"
|
|
952 |
BL WordMove ; initialise .data
|
|
953 |
MOV r0, r4
|
|
954 |
MOV r1, r5
|
|
955 |
MOV r2, #0
|
|
956 |
BL WordFill ; initialise .bss
|
|
957 |
|
|
958 |
IF :LNOT: CFG_MMDirect
|
|
959 |
|
|
960 |
; allocate SPageInfo array
|
|
961 |
|
|
962 |
PRTLN "Map SPageInfo array start"
|
|
963 |
|
|
964 |
LDR r9, =KPageInfoMap
|
|
965 |
MOV r0, r9 ; linear
|
|
966 |
MOV r2, #BTP_Kernel ; permissions
|
|
967 |
MOV r3, #0x1000 ; size
|
|
968 |
MOV r4, #12 ; map size
|
|
969 |
MOV r5, r3
|
|
970 |
BL AllocAndMap
|
|
971 |
MOV r0, r9
|
|
972 |
MOV r1, r5
|
|
973 |
MOV r2, #0
|
|
974 |
BL WordFill ; zero memory
|
|
975 |
|
|
976 |
LDR r4, [r10, #SSuperPageBase_iRamBootData]
|
|
977 |
_page_info_map_make_outer
|
|
978 |
LDMIA r4!, {r5,r6} ; r5 = bank physical base, r6 = bank size
|
|
979 |
CMP r6, #0 ; reached end of list?
|
|
980 |
BEQ _page_info_map_make_end ; jump if end
|
|
981 |
ADD r6, r6, r5
|
|
982 |
SUB r6, r6, #1
|
|
983 |
MOV r5, r5, LSR #24-KPageInfoShift
|
|
984 |
MOV r6, r6, LSR #24-KPageInfoShift
|
|
985 |
CMP r5, r6
|
|
986 |
BHI _page_info_map_make_outer
|
|
987 |
MOV r7, #1
|
|
988 |
_page_info_map_make_inner
|
|
989 |
DWORD r5, "SPageInfo Page"
|
|
990 |
AND r1, r5, #7
|
|
991 |
MOV r1, r7, LSL r1
|
|
992 |
LDRB r0, [r9, r5, LSR #3]
|
|
993 |
ORR r0, r0, r1
|
|
994 |
STRB r0, [r9, r5, LSR #3]
|
|
995 |
CMP r5, r6
|
|
996 |
ADD r5, r5, #1
|
|
997 |
BNE _page_info_map_make_inner
|
|
998 |
B _page_info_map_make_outer
|
|
999 |
_page_info_map_make_end
|
|
1000 |
|
|
1001 |
MOV r5, #0
|
|
1002 |
_page_info_alloc_find_start
|
|
1003 |
AND r1, r5, #7
|
|
1004 |
MOV r1, r7, LSL r1
|
|
1005 |
LDRB r0, [r9, r5, LSR #3]
|
|
1006 |
TST r0, r1
|
|
1007 |
BNE _page_info_alloc_start_found
|
|
1008 |
ADD r5, r5, #1
|
|
1009 |
MOVS r0, r5, LSL #24-KPageInfoShift
|
|
1010 |
BNE _page_info_alloc_find_start
|
|
1011 |
B _page_info_alloc_end
|
|
1012 |
_page_info_alloc_start_found
|
|
1013 |
MOV r6, r5 ; r6 = page offset for start of region
|
|
1014 |
_page_info_alloc_find_end
|
|
1015 |
AND r1, r5, #7
|
|
1016 |
MOV r1, r7, LSL r1
|
|
1017 |
LDRB r0, [r9, r5, LSR #3]
|
|
1018 |
TST r0, r1
|
|
1019 |
BEQ _page_info_alloc_end_found
|
|
1020 |
ADD r5, r5, #1
|
|
1021 |
MOVS r0, r5, LSL #24-KPageInfoShift
|
|
1022 |
BNE _page_info_alloc_find_end
|
|
1023 |
_page_info_alloc_end_found
|
|
1024 |
; r6 = start page offset
|
|
1025 |
; r5 = end page offset
|
|
1026 |
SUB r0, r5, r6 ; r0 = number of pages to map
|
|
1027 |
MOV r3, r0, LSL #12 ; r3 = size to map
|
|
1028 |
LDR r0, =KPageInfoLinearBase
|
|
1029 |
ADD r0, r0, r6, LSL #12 ; r0 = address to map at
|
|
1030 |
MOV r2, #BTP_Kernel ; permissions
|
|
1031 |
MOV r4, #20 ; map size
|
|
1032 |
STMDB sp!, {r0,r3}
|
|
1033 |
BL AllocAndMap
|
|
1034 |
LDMIA sp!, {r0,r1}
|
|
1035 |
MOV r2, #0
|
|
1036 |
BL WordFill ; zero memory
|
|
1037 |
|
|
1038 |
MOVS r0, r5, LSL #24-KPageInfoShift
|
|
1039 |
BNE _page_info_alloc_find_start
|
|
1040 |
_page_info_alloc_end
|
|
1041 |
PRTLN "Map SPageInfo array end"
|
|
1042 |
|
|
1043 |
ENDIF ; CFG_MMDirect
|
|
1044 |
|
|
1045 |
|
|
1046 |
; allocate memory for IRQ, FIQ, UND & ABT stacks
|
|
1047 |
|
|
1048 |
PRTLN "Allocate IRQ, FIQ, UND & ABT stacks"
|
|
1049 |
|
|
1050 |
IF CFG_MMDirect
|
|
1051 |
ADD r5, r10, #SSuperPageBase_iStackInfo ; r5 <= offset SSuperPageBase_iStackInfo
|
|
1052 |
ADD r0, r10, #0x3000 ; r0 = stack base
|
|
1053 |
IF SMP
|
|
1054 |
ADD r0, r0, #0x1000 ; r0 = stack base
|
|
1055 |
ENDIF
|
|
1056 |
MOV r3, #0x1000 ; stack size
|
|
1057 |
DWORD r0, "IRQ stack base"
|
|
1058 |
STR r0, [r5, #TStackInfo_iIrqStackBase] ; save stack base in super page
|
|
1059 |
DWORD r3, "IRQ stack size"
|
|
1060 |
STR r3, [r5, #TStackInfo_iIrqStackSize] ; save stack size in super page
|
|
1061 |
ADD r0, r0, r3
|
|
1062 |
MOV r3, #0x400 ; stack size
|
|
1063 |
DWORD r0, "FIQ stack base"
|
|
1064 |
STR r0, [r5, #TStackInfo_iFiqStackBase] ; save in super page
|
|
1065 |
DWORD r3, "FIQ stack size"
|
|
1066 |
STR r3, [r5, #TStackInfo_iFiqStackSize] ; save in super page
|
|
1067 |
ADD r0, r0, r3
|
|
1068 |
DWORD r0, "UND stack base"
|
|
1069 |
STR r0, [r5, #TStackInfo_iUndStackBase] ; save in super page
|
|
1070 |
DWORD r3, "UND stack size"
|
|
1071 |
STR r3, [r5, #TStackInfo_iUndStackSize] ; save in super page
|
|
1072 |
ADD r0, r0, r3
|
|
1073 |
DWORD r0, "ABT stack base"
|
|
1074 |
STR r0, [r5, #TStackInfo_iAbtStackBase] ; save in super page
|
|
1075 |
DWORD r3, "ABT stack size"
|
|
1076 |
STR r3, [r5, #TStackInfo_iAbtStackSize] ; save in super page
|
|
1077 |
ADD r0, r0, r3
|
|
1078 |
DWORD r0, "i_Regs" ; address of SFullArmRegSet
|
|
1079 |
|
|
1080 |
ELSE
|
|
1081 |
MOV r2, #BTP_Kernel ; permissions
|
|
1082 |
MOV r4, #KPageShift ; page size
|
|
1083 |
ADD r5, r10, #SSuperPageBase_iStackInfo ; r5 <= offset SSuperPageBase_iStackInfo
|
|
1084 |
MVN r1, #0 ; fill value
|
|
1085 |
|
|
1086 |
; IRQ stack
|
|
1087 |
|
|
1088 |
LDR r0, =KExcptStacksLinearBase
|
|
1089 |
ADD r0, r0, #KPageSize ; leave space for guard page
|
|
1090 |
DWORD r0, "IRQ stack base"
|
|
1091 |
STR r0, [r5, #TStackInfo_iIrqStackBase] ; save stack base in super page
|
|
1092 |
LDR r3, =KIrqStackSize ; stack size
|
|
1093 |
DWORD r3, "IRQ stack size"
|
|
1094 |
STR r3, [r5, #TStackInfo_iIrqStackSize] ; save stack size in super page
|
|
1095 |
BL AllocAndMap
|
|
1096 |
|
|
1097 |
; FIQ stack
|
|
1098 |
|
|
1099 |
ADD r0, r0, r3 ; ro += stack_size
|
|
1100 |
ADD r0, r0, r1, LSR #32-KPageShift
|
|
1101 |
BIC r0, r0, r1, LSR #32-KPageShift ; round up to PageSize
|
|
1102 |
ADD r0, r0, #KPageSize ; ro += KPageSize
|
|
1103 |
DWORD r0, "FIQ stack base"
|
|
1104 |
STR r0, [r5, #TStackInfo_iFiqStackBase] ; save in super page
|
|
1105 |
LDR r3, =KFiqStackSize ; stack size
|
|
1106 |
DWORD r3, "FIQ stack size"
|
|
1107 |
STR r3, [r5, #TStackInfo_iFiqStackSize] ; save in super page
|
|
1108 |
BL AllocAndMap
|
|
1109 |
|
|
1110 |
; UND stack
|
|
1111 |
|
|
1112 |
ADD r0, r0, r3 ; ro += stack_size
|
|
1113 |
ADD r0, r0, r1, LSR #32-KPageShift
|
|
1114 |
BIC r0, r0, r1, LSR #32-KPageShift ; round up to PageSize
|
|
1115 |
ADD r0, r0, #KPageSize ; ro += KPageSize
|
|
1116 |
DWORD r0, "UND stack base"
|
|
1117 |
STR r0, [r5, #TStackInfo_iUndStackBase] ; save in super page
|
|
1118 |
LDR r3, =KUndStackSize ; stack size
|
|
1119 |
DWORD r3, "UND stack size"
|
|
1120 |
STR r3, [r5, #TStackInfo_iUndStackSize] ; save in super page
|
|
1121 |
BL AllocAndMap
|
|
1122 |
|
|
1123 |
; ABT stack
|
|
1124 |
|
|
1125 |
ADD r0, r0, r3 ; ro += stack_size
|
|
1126 |
ADD r0, r0, r1, LSR #32-KPageShift
|
|
1127 |
BIC r0, r0, r1, LSR #32-KPageShift ; round up to PageSize
|
|
1128 |
ADD r0, r0, #KPageSize ; ro += KPageSize
|
|
1129 |
DWORD r0, "ABT stack base"
|
|
1130 |
STR r0, [r5, #TStackInfo_iAbtStackBase] ; save in super page
|
|
1131 |
LDR r3, =KAbtStackSize ; stack size
|
|
1132 |
SUB r3, r3, #0x400 ; reserve 1KB for SFullArmRegSet
|
|
1133 |
DWORD r3, "ABT stack size"
|
|
1134 |
STR r3, [r5, #TStackInfo_iAbtStackSize] ; save in super page
|
|
1135 |
BL AllocAndMap
|
|
1136 |
|
|
1137 |
ENDIF
|
|
1138 |
|
|
1139 |
; fill IRQ, FIQ, UND, ABT stacks and set up banked stack pointers
|
|
1140 |
GETCPSR r4
|
|
1141 |
LDR r0, [r5, #TStackInfo_iIrqStackBase] ;
|
|
1142 |
LDR r1, [r5, #TStackInfo_iIrqStackSize] ;
|
|
1143 |
MOV r2, #0xAA
|
|
1144 |
ADD r2, r2, r2, lsl #8
|
|
1145 |
ADD r2, r2, r2, lsl #16
|
|
1146 |
BL WordFill
|
|
1147 |
BIC r3, r4, #0x1f
|
|
1148 |
ORR r3, r3, #0xd2 ; mode_irq
|
|
1149 |
SETCPSR r3
|
|
1150 |
MOV r13, r0 ; set up R13_irq
|
|
1151 |
SETCPSR r4
|
|
1152 |
LDR r0, [r5, #TStackInfo_iFiqStackBase] ;
|
|
1153 |
LDR r1, [r5, #TStackInfo_iFiqStackSize] ;
|
|
1154 |
MOV r2, #0xBB
|
|
1155 |
ADD r2, r2, r2, lsl #8
|
|
1156 |
ADD r2, r2, r2, lsl #16
|
|
1157 |
BL WordFill
|
|
1158 |
BIC r3, r4, #0x1f
|
|
1159 |
ORR r3, r3, #0xd1 ; mode_fiq
|
|
1160 |
SETCPSR r3
|
|
1161 |
MOV r13, r0 ; set up R13_fiq
|
|
1162 |
SETCPSR r4
|
|
1163 |
LDR r0, [r5, #TStackInfo_iUndStackBase] ;
|
|
1164 |
LDR r1, [r5, #TStackInfo_iUndStackSize] ;
|
|
1165 |
MOV r2, #0xDD
|
|
1166 |
ADD r2, r2, r2, lsl #8
|
|
1167 |
ADD r2, r2, r2, lsl #16
|
|
1168 |
BL WordFill
|
|
1169 |
BIC r3, r4, #0x1f
|
|
1170 |
ORR r3, r3, #0xdb ; mode_und
|
|
1171 |
SETCPSR r3
|
|
1172 |
MOV r13, r0 ; set up R13_und
|
|
1173 |
SETCPSR r4
|
|
1174 |
LDR r0, [r5, #TStackInfo_iAbtStackBase] ;
|
|
1175 |
LDR r1, [r5, #TStackInfo_iAbtStackSize] ;
|
|
1176 |
MOV r2, #0xDD
|
|
1177 |
ADD r2, r2, r2, lsl #8
|
|
1178 |
ADD r2, r2, r2, lsl #16
|
|
1179 |
BL WordFill
|
|
1180 |
BIC r3, r4, #0x1f
|
|
1181 |
ORR r3, r3, #0xd7 ; mode_abt
|
|
1182 |
SETCPSR r3
|
|
1183 |
MOV r13, r0 ; set up R13_abt
|
|
1184 |
SETCPSR r4
|
|
1185 |
MOV r1, #0x400
|
|
1186 |
MOV r2, #0
|
|
1187 |
BL WordFill ; zero fill SFullArmRegSet space
|
|
1188 |
IF CFG_MMDirect
|
|
1189 |
LDR r1, [r5, #TStackInfo_iIrqStackBase] ;
|
|
1190 |
SETCPSR r3
|
|
1191 |
SUB r14, r0, r1 ; total size of exception mode stacks + SFullArmRegSet
|
|
1192 |
SETCPSR r4
|
|
1193 |
ENDIF
|
|
1194 |
|
|
1195 |
IF SMP
|
|
1196 |
IF :LNOT: CFG_MMDirect
|
|
1197 |
; Allocate and map uncached AP Boot Page
|
|
1198 |
MOV r2, #BMA_Kernel ; type
|
|
1199 |
MOV r4, #12 ; size = 1 page
|
|
1200 |
BOOTCALL BTF_Alloc ; allocate page, physical address into R0
|
|
1201 |
DWORD r0, "APBootPagePhys"
|
|
1202 |
STR r0, [r10, #SSuperPageBase_iAPBootPagePhys]
|
|
1203 |
MOV r1, r0 ; physical
|
|
1204 |
LDR r0, =KAPBootPageLin ; virtual
|
|
1205 |
DWORD r0, "APBootPageLin"
|
|
1206 |
STR r0, [r10, #SSuperPageBase_iAPBootPageLin]
|
|
1207 |
MOV r2, #BTP_Uncached ; permissions
|
|
1208 |
MOV r3, #KPageSize ; size
|
|
1209 |
MOV r4, #12
|
|
1210 |
BL MapContiguous ; map the page
|
|
1211 |
MOV r1, #0x1000
|
|
1212 |
MOV r2, #0
|
|
1213 |
BL WordFill ; clear AP Boot Page
|
|
1214 |
ENDIF
|
|
1215 |
ENDIF
|
|
1216 |
|
|
1217 |
; do final hardware-dependent initialisation
|
|
1218 |
|
|
1219 |
PRTLN "Final platform dependent initialisation"
|
|
1220 |
BOOTCALL BTF_Final
|
|
1221 |
|
|
1222 |
; for bootloader work out address where image should go
|
|
1223 |
IF CFG_BootLoader
|
|
1224 |
GETMPARAM BPR_BootLdrImgAddr ; R0 = image physical address
|
|
1225 |
BL RamPhysicalToLinear
|
|
1226 |
MOV r9, r0 ; save linear in R9
|
|
1227 |
DWORD r9, "ImgAddrLin"
|
|
1228 |
ENDIF
|
|
1229 |
|
|
1230 |
; final diagnostics
|
|
1231 |
IF CFG_DebugBootRom
|
|
1232 |
|
|
1233 |
PRTLN "Super page and CPU page:"
|
|
1234 |
MOV r1, #SuperCpuSize
|
|
1235 |
MEMDUMP r10, r1 ; dump super page + CPU page
|
|
1236 |
|
|
1237 |
IF CFG_MMUPresent
|
|
1238 |
PRTLN "Page directory:"
|
|
1239 |
IF CFG_MMDirect
|
|
1240 |
GETPARAM BPR_PageTableSpace, DefaultPTAlloc ; get reserved space for page tables
|
|
1241 |
LDR r2, [r10, #SSuperPageBase_iPageDir] ;
|
|
1242 |
MOV r1, r0 ; size
|
|
1243 |
ADD r2, r2, #0x4000 ; end of page dir
|
|
1244 |
IF SMP
|
|
1245 |
ADD r2, r2, #0x4000 ; end of APBoot page dir
|
|
1246 |
ENDIF
|
|
1247 |
SUB r0, r2, r0 ; size includes page directory and tables
|
|
1248 |
ELSE
|
|
1249 |
LDR r0, [r10, #SSuperPageBase_iPageDir] ; page directory address
|
|
1250 |
MOV r1, #0x4000 ; page directory size
|
|
1251 |
ENDIF
|
|
1252 |
MEMDUMP r0, r1 ; dump page directory
|
|
1253 |
|
|
1254 |
IF :LNOT: CFG_MMDirect
|
|
1255 |
LDR r0, =KPageTableBase ; page table linear base
|
|
1256 |
SUB r2, r0, #4
|
|
1257 |
_CountPt
|
|
1258 |
LDR r1, [r2, #4]! ; get next PT0 entry
|
|
1259 |
CMP r1, #0 ; empty?
|
|
1260 |
BNE _CountPt ; if not, next
|
|
1261 |
SUB r1, r2, r0 ; 4*number of page tables
|
|
1262 |
MOV r1, r1, LSL #10 ; 1K per page table
|
|
1263 |
PRTLN "Page tables:"
|
|
1264 |
MEMDUMP r0, r1 ; dump page tables
|
|
1265 |
IF SMP
|
|
1266 |
LDR r0, [r10, #SSuperPageBase_iAPBootPageDirPhys]
|
|
1267 |
DWORD r0, "APBootPageDirPhys"
|
|
1268 |
PRTLN "APBoot PageDir/Tables:"
|
|
1269 |
LDR r0, =KAPBootPageDirLin ; r0 = page directory linear
|
|
1270 |
MOV r1, #0x5000 ; 16K page directory + page tables
|
|
1271 |
MEMDUMP r0, r1 ; dump page tables
|
|
1272 |
PRTLN "APBootPage"
|
|
1273 |
LDR r0, [r10, #SSuperPageBase_iAPBootPageLin]
|
|
1274 |
MOV r1, #0x1000
|
|
1275 |
MEMDUMP r0, r1 ; dump AP Boot Page
|
|
1276 |
ENDIF
|
|
1277 |
ENDIF
|
|
1278 |
|
|
1279 |
ENDIF ; CFG_MMUPresent
|
|
1280 |
ENDIF ; CFG_DebugBootRom
|
|
1281 |
|
|
1282 |
|
|
1283 |
IF :DEF: CFG_HasL210Cache
|
|
1284 |
;Enable L2 cache. Enabling L220 & PL310 is baseport specific due to security extension (TrustZone).
|
|
1285 |
LDR r0, [r10, #SSuperPageBase_iArmL2CacheBase]
|
|
1286 |
MOV r1, #1
|
|
1287 |
STR r1, [r0, #0x100]
|
|
1288 |
PRTLN "L2CACHE: Enabled"
|
|
1289 |
ENDIF
|
|
1290 |
|
|
1291 |
; boot the kernel
|
|
1292 |
|
|
1293 |
LDR r14, [r11, #TRomImageHeader_iEntryPoint] ; kernel entry point
|
|
1294 |
DWORD r14, "Jumping to OS at location"
|
|
1295 |
MOV r0, r12 ; pass address of ROM header
|
|
1296 |
MOV r1, r10 ; pass address of super page
|
|
1297 |
DWORD r0, "R0"
|
|
1298 |
DWORD r1, "R1"
|
|
1299 |
IF CFG_BootLoader
|
|
1300 |
STR r9, [r10, #SSuperPageBase_iCodeBase] ; for bootloader pass image address
|
|
1301 |
ENDIF
|
|
1302 |
IF CFG_DebugBootRom
|
|
1303 |
; pause to let tracing finish
|
|
1304 |
MOV r12, #0x00100000
|
|
1305 |
SUBS r12, r12, #1
|
|
1306 |
SUBNE pc, pc, #12
|
|
1307 |
ENDIF
|
|
1308 |
MOV pc, r14 ; jump to kernel entry point
|
|
1309 |
|
|
1310 |
|
|
1311 |
|
|
1312 |
|
|
1313 |
END
|