author | Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com> |
Tue, 31 Aug 2010 16:34:26 +0300 | |
branch | RCL_3 |
changeset 43 | c1f20ce4abcf |
parent 28 | 5b5d147c7838 |
permissions | -rw-r--r-- |
0 | 1 |
// Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies). |
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// All rights reserved. |
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// This component and the accompanying materials are made available |
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// under the terms of the License "Eclipse Public License v1.0" |
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// which accompanies this distribution, and is available |
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// at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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// |
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// Initial Contributors: |
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// Nokia Corporation - initial contribution. |
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// |
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// Contributors: |
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// |
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// Description: |
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// e32\klib\arm\cbma.cia |
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// Machine coded bitmap allocator for ARM |
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// This file is directly included in the test harness t_tbma |
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// |
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// |
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#include <kernel/kbma.h> |
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#include <cpudefs.h> |
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#include <e32cia.h> |
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#ifdef TBMA_TEST_CODE |
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#include <e32atomics.h> |
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#ifdef __MARM__ |
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#define __TBMA_MACHINE_CODED__ |
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#endif |
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#else |
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#include <kernel/kern_priv.h> |
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#endif |
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#ifdef __TBMA_MACHINE_CODED__ |
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extern void TBmaFault(TInt aLine); |
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#define ASM_FAULT_LINE(x) asm("ldr r0, [pc] "); asm("b " CSM_Z9TBmaFaulti ); asm(".word %a0" : : "i" (x)); |
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#define ASM_FAULT() ASM_FAULT_LINE(__LINE__) |
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#ifndef __EABI_CTORS__ |
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/** Construct a new TBitMapAllocator object |
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@param aSize The number of bit positions required |
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@param aState TRUE if all bit positions initially free |
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FALSE if all bit positions initially allocated |
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*/ |
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EXPORT_C __NAKED__ TBitMapAllocator::TBitMapAllocator(TInt /*aSize*/, TBool /*aState*/) |
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{ |
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asm("cmp r1, #0 "); |
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asm("ble 0f "); |
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asm("cmp r2, #0 "); |
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asm("movne r2, r1 "); // if aState r2=aSize else r2=0 |
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asm("str r2, [r0, #0] "); // iAvail=aState?aSize:0 |
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asm("add r12, r0, #12 "); // r12=&iMap[0] |
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asm("str r1, [r0, #8] "); // iSize=r1 |
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asm("add r3, r1, #31 "); |
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asm("bic r3, r3, #31 "); // r3=aSize rounded up to multiple of 32 |
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asm("sub r3, r3, #32 "); // r3=32*(number of map words-1) |
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asm("addeq r12, r12, r3, lsr #3 "); // if !aState r12=&iMap[nmapw-1] |
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asm("str r12, [r0, #4] "); // iCheckFirst=aState?&iMap[0]:&iMap[nmapw-1] |
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asm("mvnne r2, #0 "); // if aState r2=0xffffffff else r2=0 |
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asm("add r12, r0, #12 "); // r12=&iMap[0] |
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asm("1: "); |
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asm("str r2, [r12], #4 "); // fill map |
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asm("subs r1, r1, #32 "); |
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asm("bhi 1b "); |
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asm("rsbne r1, r1, #0 "); // if aSize not a multiple of 32, r1=number of tail bits to clear |
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asm("movne r2, r2, lsl r1 "); // clear unused bits |
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asm("strne r2, [r12, #-4] "); |
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__JUMP(,lr); |
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asm("0: "); |
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ASM_FAULT(); |
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} |
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#endif |
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/** Allocate the next available bit position |
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@return Number of position allocated, -1 if all positions occupied |
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*/ |
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EXPORT_C __NAKED__ TInt TBitMapAllocator::Alloc() |
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{ |
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asm("ldmia r0, {r1,r2} "); // r1=available, r2=check first address |
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asm("subs r1, r1, #1 "); // decrement free count |
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asm("mvnmi r0, #0 "); // if none free, return with r0=-1 |
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__JUMP(mi,lr); |
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asm("str r1, [r0] "); // store decremented free count |
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asm("alloc_1: "); |
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asm("ldr r3, [r2], #4 "); // check word |
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asm("cmp r3, #0 "); // any free entries? |
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asm("beq alloc_1 "); // if not, check next word |
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#ifdef __CPU_ARM_HAS_CLZ |
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CLZ(12, 3); |
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#else |
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asm("mov ip, #0 "); |
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asm("cmp r3, #0x00010000 "); // ip=number of leading zeros in r3 |
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asm("movlo r3, r3, lsl #16 "); |
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asm("addlo ip, ip, #16 "); |
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asm("cmp r3, #0x01000000 "); |
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asm("movlo r3, r3, lsl #8 "); |
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asm("addlo ip, ip, #8 "); |
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asm("cmp r3, #0x10000000 "); |
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asm("movlo r3, r3, lsl #4 "); |
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asm("addlo ip, ip, #4 "); |
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asm("cmp r3, #0x40000000 "); |
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asm("movlo r3, r3, lsl #2 "); |
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asm("addlo ip, ip, #2 "); |
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asm("cmp r3, #0x80000000 "); |
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asm("addlo ip, ip, #1 "); |
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#endif |
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asm("ldr r3, [r2, #-4]! "); |
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asm("mov r1, #0x80000000 "); |
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asm("bic r3, r3, r1, lsr ip "); // clear bit in allocator word |
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asm("str r3, [r2] "); |
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asm("str r2, [r0, #4] "); // update check first address |
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asm("sub r0, r2, r0 "); |
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asm("sub r0, r0, #12 "); // r0=offset of word from iMap[0] |
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asm("adds r0, ip, r0, lsl #3 "); // multiply by 8 and add bit position |
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__JUMP(,lr); |
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} |
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/** Free the specified bit position |
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@param aPos Number of bit position to be freed; must be currently allocated. |
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*/ |
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EXPORT_C __NAKED__ void TBitMapAllocator::Free(TInt /*aPos*/) |
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{ |
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asm("ldr r3, [r0, #8] "); // r3=iSize |
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asm("mov r2, r1, lsr #5 "); // r2=word index |
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asm("add r2, r0, r2, lsl #2 "); // r2=address of word-12 |
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asm("cmp r1, r3 "); |
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asm("bhs free_error "); |
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asm("and ip, r1, #0x1f "); // ip=bit number in word |
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asm("ldr r3, [r2, #12]! "); // r3=allocator word |
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asm("mov r1, #0x80000000 "); |
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asm("tst r3, r1, lsr ip "); // test bit |
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asm("bne free_error "); // if already free, error |
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asm("orr r3, r3, r1, lsr ip "); // set free bit |
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asm("str r3, [r2] "); |
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asm("ldmia r0, {r1,r3} "); // r1=available count, r3=first free address |
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asm("cmp r1, #1 "); // check original free count |
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asm("add r1, r1, #1 "); // increment available count |
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asm("str r1, [r0, #0] "); |
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asm("cmpcs r2, r3 "); // compare word address with first free |
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asm("strcc r2, [r0, #4] "); // if lower, update first free |
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__JUMP(,lr); |
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asm("free_error: "); |
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ASM_FAULT(); |
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} |
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/** Allocate a specific range of bit positions |
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Specified range must lie within the total range for this allocator and all |
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the positions must currently be free. |
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@param aStart First position to allocate |
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@param aLength Number of consecutive positions to allocate, must be >0 |
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*/ |
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EXPORT_C __NAKED__ void TBitMapAllocator::Alloc(TInt /*aStart*/, TInt /*aLength*/) |
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{ |
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asm("ldr ip, [r0, #8] "); |
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asm("str lr, [sp, #-4]! "); |
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asm("adds lr, r1, r2 "); |
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asm("bcs 0f "); |
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asm("cmp lr, ip "); |
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asm("bhi 0f "); |
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asm("mov r3, r1, lsr #5 "); |
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asm("ldr ip, [r0] "); |
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asm("and r1, r1, #0x1f "); |
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asm("add r3, r0, r3, lsl #2 "); |
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asm("sub ip, ip, r2 "); // reduce free count |
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asm("str ip, [r0] "); |
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asm("add ip, r2, r1 "); |
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asm("cmp ip, #32 "); |
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asm("bhi 1f "); |
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asm("mvn ip, #0 "); |
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asm("ldr r0, [r3, #12]! "); |
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asm("mvn ip, ip, lsr r2 "); |
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asm("mov ip, ip, lsr r1 "); |
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asm("orr lr, r0, ip "); |
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asm("cmp lr, r0 "); |
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asm("bne 0f "); |
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asm("bic r0, r0, ip "); |
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asm("str r0, [r3] "); |
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asm("ldr pc, [sp], #4 "); |
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asm("1: "); |
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asm("add r3, r3, #12 "); |
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asm("mvn r2, #0 "); |
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asm("mov r2, r2, lsr r1 "); |
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asm("2: "); |
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asm("ldr r1, [r3] "); |
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asm("orr lr, r1, r2 "); |
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asm("cmp lr, r1 "); |
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asm("bne 0f "); |
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asm("bic r1, r1, r2 "); |
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asm("str r1, [r3], #4 "); |
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asm("mvn r2, #0 "); |
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asm("subs ip, ip, #32 "); |
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asm("ldrls pc, [sp], #4 "); |
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asm("cmp ip, #32 "); |
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asm("mvncc r2, r2, lsr ip "); |
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asm("b 2b "); |
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asm("0: "); |
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ASM_FAULT(); |
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} |
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/** Free a specific range of bit positions |
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Specified range must lie within the total range for this allocator and all |
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the positions must currently be allocated. |
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@param aStart First position to free |
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@param aLength Number of consecutive positions to free, must be >0 |
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*/ |
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EXPORT_C __NAKED__ void TBitMapAllocator::Free(TInt /*aStart*/, TInt /*aLength*/) |
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{ |
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asm("ldr ip, [r0, #8] "); |
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asm("str lr, [sp, #-4]! "); |
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asm("adds lr, r1, r2 "); |
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asm("bcs 0f "); |
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asm("cmp lr, ip "); |
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asm("bhi 0f "); |
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asm("mov r3, r1, lsr #5 "); |
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asm("and r1, r1, #0x1f "); |
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asm("add r3, r0, r3, lsl #2 "); |
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asm("ldmia r0, {ip,lr} "); // ip=free count, lr=first check addr |
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asm("add r3, r3, #12 "); |
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asm("cmp ip, #1 "); // check original free count |
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asm("add ip, ip, r2 "); // increase free count |
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asm("cmpcs r3, lr "); // if none free originally, always update address |
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asm("str ip, [r0] "); |
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asm("strcc r3, [r0, #4] "); // update first check addr if necessary |
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asm("add lr, r2, r1 "); |
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asm("cmp lr, #32 "); |
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asm("bhi 1f "); |
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asm("mvn lr, #0 "); |
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asm("ldr r0, [r3] "); |
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asm("mvn lr, lr, lsr r2 "); |
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asm("mov lr, lr, lsr r1 "); |
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asm("tst r0, lr "); |
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asm("bne 0f "); |
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asm("orr r0, r0, lr "); |
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asm("str r0, [r3] "); |
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asm("ldr pc, [sp], #4 "); |
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asm("1: "); |
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asm("mvn r2, #0 "); |
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asm("mov r2, r2, lsr r1 "); |
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asm("2: "); |
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asm("ldr r1, [r3] "); |
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asm("tst r1, r2 "); |
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asm("bne 0f "); |
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asm("orr r1, r1, r2 "); |
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asm("str r1, [r3], #4 "); |
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asm("mvn r2, #0 "); |
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asm("subs lr, lr, #32 "); |
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asm("ldrls pc, [sp], #4 "); |
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asm("cmp lr, #32 "); |
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asm("mvncc r2, r2, lsr lr "); |
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asm("b 2b "); |
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asm("0: "); |
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ASM_FAULT(); |
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} |
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/** Free a specific range of bit positions |
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Specified range must lie within the total range for this allocator but it is |
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not necessary that all the positions are currently allocated. |
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@param aStart First position to free |
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@param aLength Number of consecutive positions to free, must be >0 |
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*/ |
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EXPORT_C __NAKED__ void TBitMapAllocator::SelectiveFree(TInt /*aStart*/, TInt /*aLength*/) |
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{ |
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asm("ldr r3, [r0, #8] "); |
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asm("stmfd sp!, {r4-r8,lr} "); |
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asm("adds lr, r1, r2 "); |
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asm("bcs 0f "); |
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asm("cmp lr, r3 "); |
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asm("bhi 0f "); |
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asm("mov r7, r0 "); // r7 -> this |
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asm("mov r4, r1, lsr #5 "); |
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asm("and r1, r1, #0x1f "); |
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asm("ldmia r7, {r6,r8} "); // r6=free count, r8=first check addr |
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asm("add r4, r7, r4, lsl #2 "); |
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asm("add r4, r4, #12 "); |
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asm("cmp r6, #1 "); // check original free count |
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asm("add r6, r6, r2 "); // r6=new free count assuming no positions already free |
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asm("cmpcs r4, r8 "); // if none free originally, always update address |
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asm("strcc r4, [r7, #4] "); // update first check addr if necessary |
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asm("add r8, r2, r1 "); |
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asm("cmp r8, #32 "); |
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asm("bhi sfree_cross_bdry "); |
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asm("mvn r8, #0 "); |
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asm("mvn r8, r8, lsr r2 "); |
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asm("mov r8, r8, lsr r1 "); |
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asm("ldr r1, [r4] "); |
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asm("ands r0, r1, r8 "); // r0 has 1's in positions which are already free |
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asm("orr r1, r1, r8 "); |
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asm("str r1, [r4] "); // store new bit mask |
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asm("beq sfree_0 "); // if none were already free, finished |
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asm("bl " CSM_CFUNC(__e32_bit_count_32)); |
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asm("sub r6, r6, r0 "); |
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asm("sfree_0: "); |
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asm("str r6, [r7] "); // store free count |
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asm("ldmfd sp!, {r4-r8,pc} "); // return |
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asm("sfree_cross_bdry: "); |
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asm("mvn r5, #0 "); |
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asm("mov r5, r5, lsr r1 "); |
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asm("sfree_cross_bdry_1: "); |
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asm("ldr r1, [r4] "); // original bit mask |
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asm("ands r0, r1, r5 "); // r0 has 1's in bit positions which are already free |
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asm("orr r1, r1, r5 "); |
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asm("str r1, [r4], #4 "); // store new bit mask |
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asm("beq sfree_2 "); // skip if none were already free |
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asm("bl " CSM_CFUNC(__e32_bit_count_32)); |
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asm("sub r6, r6, r0 "); |
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asm("sfree_2: "); |
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asm("mvn r5, #0 "); |
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asm("subs r8, r8, #32 "); |
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asm("bls sfree_0 "); |
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asm("cmp r8, #32 "); |
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asm("mvncc r5, r5, lsr r8 "); |
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asm("b sfree_cross_bdry_1 "); |
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asm("0: "); |
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ASM_FAULT(); |
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} |
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5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
339 |
/** Allocates a specific range of bit positions. |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
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|
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
341 |
The specified range must lie within the total range for this allocator but it is |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
342 |
not necessary that all the positions are currently free. |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
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343 |
|
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
344 |
@param aStart First position to allocate. |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
345 |
@param aLength Number of consecutive positions to allocate, must be >0. |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
346 |
@return The number of previously free positions that were allocated. |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
347 |
*/ |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
348 |
EXPORT_C __NAKED__ TUint TBitMapAllocator::SelectiveAlloc(TInt /*aStart*/, TInt /*aLength*/) |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
349 |
{ |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
350 |
asm("ldr r3, [r0, #%a0] " : : "i" _FOFF(TBitMapAllocator, iSize)); // r3->iSize |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
351 |
asm("stmfd sp!, {r4-r8,lr} "); |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
352 |
asm("adds r4, r1, r2 "); // r4 = aStart + aLength |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
353 |
asm("bcs 0f "); // if (aStart + aLength < aStart) |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
354 |
asm("cmp r4, r3 "); // if (aStart + aLength > iSize) |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
355 |
asm("bhi 0f "); |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
356 |
asm("mov r7, r0 "); // r7 = this |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
357 |
asm("mov r4, r1, lsr #5 "); // r4 = wix = aStart >> 5 |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
358 |
asm("and r1, r1, #0x1f "); // r1 = sbit = aStart & 31 |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
359 |
asm("ldr r6, [r7, #%a0] " : : "i" _FOFF(TBitMapAllocator, iAvail)); // r6 = iAvail |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
360 |
asm("add r4, r7, r4, lsl #2 "); |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
361 |
asm("add r4, r4, #%a0 " : : "i" _FOFF(TBitMapAllocator, iMap)); // r4 = iMap + wix |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
362 |
asm("sub r6, r6, r2 "); // r6 = iAvail -= aLength |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
363 |
asm("add r5, r2, r1 "); // r5 = ebit = sbit + aLength |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
364 |
asm("mvn r0, #0 "); |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
365 |
asm("mvn r0, r0, lsr r1 "); // r0 = b = ~(0xffffffff >> sbit) |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
366 |
asm("cmp r5, #32 "); |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
367 |
asm("mov r8, r2"); // r8 = aLength |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
368 |
asm("bhi salloc_cross_bdry "); // branch if (ebit >=32) |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
369 |
|
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
370 |
asm("mvn r5, #0 "); // r5 = 0xffffffff |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
371 |
asm("mov r5, r5, lsr r8 "); // r5 >> aLength |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
372 |
asm("mov r5, r5, lsr r1 "); // r5 >> sbit |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
373 |
asm("orr r5, r5, r0 "); // r5 = b = r0 | r5 |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
374 |
asm("ldr r0, [r4] "); // r0 = w = *pW |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
375 |
asm("and r1, r0, r5 "); // r1 = w & b, clear the positions to be allocated |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
376 |
asm("str r1, [r4] "); // *pW = r1, store new bit map word. |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
377 |
asm("mvn r0, r0"); // r0 = ~w |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
378 |
asm("mvn r5, r5"); // r5 = ~b |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
379 |
asm("and r0, r0, r5"); // r0 = ~w & ~b |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
380 |
asm("bl " CSM_CFUNC(__e32_bit_count_32)); |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
381 |
asm("add r6, r6, r0 "); // r6 = iAvail + allocated |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
382 |
asm("sub r0, r8, r0 "); // return aLength - allocated |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
383 |
asm("str r6, [r7] "); // iAvail += allocated, store free count |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
384 |
asm("ldmfd sp!, {r4-r8,pc} "); // return |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
385 |
|
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
386 |
asm("salloc_cross_bdry: "); // r0 = b, r8 = aLength, r7 = this, r5 = ebit |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
387 |
asm("ldr r2, [r4] "); // r2 = w = *pW |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
388 |
asm("and r1, r2, r0 "); // r1 = w & b |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
389 |
asm("str r1, [r4], #4 "); // *pW++ = r1, store new bit mask |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
390 |
asm("mvn r2, r2"); // r2 = ~w |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
391 |
asm("mvn r0, r0"); // r0 = ~b |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
392 |
asm("and r0, r0, r2"); // r0 = ~w & ~b |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
393 |
asm("bl " CSM_CFUNC(__e32_bit_count_32)); |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
394 |
asm("add r6, r6, r0 "); // r6 = iAvail += allocated |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
395 |
asm("sub r8, r8, r0 "); // r8 = aLength -= allocated |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
396 |
asm("subs r5, r5, #32 "); // r5 = ebit -= 32 |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
397 |
asm("bls salloc_return "); // ebit < 0 so return. |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
398 |
asm("cmp r5, #32 "); // if (ebit < 32) { |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
399 |
asm("mvnlt r0, #0 "); |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
400 |
asm("movlt r0, r0, lsr r5 "); // r0 = 0xffffffff >> ebit } |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
401 |
asm("movge r0, #0 "); // if (ebit >= 32) r0 = b = 0 |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
402 |
asm("b salloc_cross_bdry "); |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
403 |
|
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
404 |
asm("salloc_return: "); |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
405 |
asm("str r6, [r7] "); // iAvail += allocated, store free count |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
406 |
asm("mov r0, r8 "); // return aLength |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
407 |
asm("ldmfd sp!, {r4-r8,pc} "); // return |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
408 |
|
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
409 |
asm("0: "); |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
410 |
ASM_FAULT(); |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
411 |
} |
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
412 |
|
5b5d147c7838
Revision: 201021
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
413 |
|
0 | 414 |
/** Tests if a specific range of bit positions are all free |
415 |
Specified range must lie within the total range for this allocator. |
|
416 |
||
417 |
@param aStart First position to check |
|
418 |
@param aLength Number of consecutive positions to check, must be >0 |
|
419 |
@return FALSE if all positions free, TRUE if at least one is occupied. |
|
420 |
*/ |
|
421 |
EXPORT_C __NAKED__ TBool TBitMapAllocator::NotFree(TInt /*aStart*/, TInt /*aLength*/) const |
|
422 |
{ |
|
423 |
// Inverse logic - returns 0 if all positions free, nonzero otherwise |
|
424 |
asm("ldr r3, [r0, #8] "); |
|
425 |
asm("adds ip, r1, r2 "); |
|
426 |
asm("bcs 0f "); |
|
427 |
asm("cmp ip, r3 "); |
|
428 |
asm("bhi 0f "); |
|
429 |
asm("mov r3, r1, lsr #5 "); |
|
430 |
asm("and r1, r1, #0x1f "); |
|
431 |
asm("add r3, r0, r3, lsl #2 "); |
|
432 |
asm("add ip, r2, r1 "); |
|
433 |
asm("add r3, r3, #12 "); |
|
434 |
asm("cmp ip, #32 "); |
|
435 |
asm("bhi 1f "); |
|
436 |
asm("mvn ip, #0 "); |
|
437 |
asm("ldr r0, [r3] "); |
|
438 |
asm("mvn ip, ip, lsr r2 "); |
|
439 |
asm("mov ip, ip, lsr r1 "); |
|
440 |
asm("eor r0, r0, ip "); |
|
441 |
asm("ands r0, r0, ip "); |
|
442 |
__JUMP(,lr); |
|
443 |
asm("1: "); |
|
444 |
asm("mvn r2, #0 "); |
|
445 |
asm("mov r2, r2, lsr r1 "); |
|
446 |
asm("2: "); |
|
447 |
asm("ldr r1, [r3], #4 "); |
|
448 |
asm("eor r0, r1, r2 "); |
|
449 |
asm("ands r0, r0, r2 "); |
|
450 |
__JUMP(ne,lr); |
|
451 |
asm("mvn r2, #0 "); |
|
452 |
asm("subs ip, ip, #32 "); |
|
453 |
__JUMP(ls,lr); |
|
454 |
asm("cmp ip, #32 "); |
|
455 |
asm("mvncc r2, r2, lsr ip "); |
|
456 |
asm("b 2b "); |
|
457 |
||
458 |
asm("0: "); |
|
459 |
ASM_FAULT(); |
|
460 |
} |
|
461 |
||
462 |
||
463 |
/** Tests if a specific range of bit positions are all occupied |
|
464 |
Specified range must lie within the total range for this allocator. |
|
465 |
||
466 |
@param aStart First position to check |
|
467 |
@param aLength Number of consecutive positions to check, must be >0 |
|
468 |
@return FALSE if all positions occupied, TRUE if at least one is free. |
|
469 |
*/ |
|
470 |
EXPORT_C __NAKED__ TBool TBitMapAllocator::NotAllocated(TInt /*aStart*/, TInt /*aLength*/) const |
|
471 |
{ |
|
472 |
// Inverse logic - returns 0 if all positions allocated, nonzero otherwise |
|
473 |
asm("ldr r3, [r0, #8] "); |
|
474 |
asm("adds ip, r1, r2 "); |
|
475 |
asm("bcs 0f "); |
|
476 |
asm("cmp ip, r3 "); |
|
477 |
asm("bhi 0f "); |
|
478 |
asm("mov r3, r1, lsr #5 "); |
|
479 |
asm("and r1, r1, #0x1f "); |
|
480 |
asm("add r3, r0, r3, lsl #2 "); |
|
481 |
asm("add ip, r2, r1 "); |
|
482 |
asm("add r3, r3, #12 "); |
|
483 |
asm("cmp ip, #32 "); |
|
484 |
asm("bhi 1f "); |
|
485 |
asm("mvn ip, #0 "); |
|
486 |
asm("ldr r0, [r3] "); |
|
487 |
asm("mvn ip, ip, lsr r2 "); |
|
488 |
asm("ands r0, r0, ip, lsr r1 "); |
|
489 |
__JUMP(,lr); |
|
490 |
asm("1: "); |
|
491 |
asm("mvn r2, #0 "); |
|
492 |
asm("mov r2, r2, lsr r1 "); |
|
493 |
asm("2: "); |
|
494 |
asm("ldr r1, [r3], #4 "); |
|
495 |
asm("ands r0, r1, r2 "); |
|
496 |
__JUMP(ne,lr); |
|
497 |
asm("mvn r2, #0 "); |
|
498 |
asm("subs ip, ip, #32 "); |
|
499 |
__JUMP(ls,lr); |
|
500 |
asm("cmp ip, #32 "); |
|
501 |
asm("mvncc r2, r2, lsr ip "); |
|
502 |
asm("b 2b "); |
|
503 |
||
504 |
asm("0: "); |
|
505 |
ASM_FAULT(); |
|
506 |
} |
|
507 |
||
508 |
||
509 |
/** Allocate up to a specified number of available bit positions |
|
510 |
The allocated positions are not required to bear any relationship to |
|
511 |
each other. |
|
512 |
If the number of free positions is less than the number requested, |
|
513 |
allocate all currently free positions. |
|
514 |
||
515 |
@param aLength Maximum number of positions to allocate. |
|
516 |
@param aList Pointer to memory area where allocated bit numbers should be stored. |
|
517 |
@return The number of positions allocated |
|
518 |
*/ |
|
519 |
EXPORT_C __NAKED__ TInt TBitMapAllocator::AllocList(TInt /*aLength*/, TInt* /*aList*/) |
|
520 |
{ |
|
521 |
asm("ldmia r0, {r3,ip} "); // r3=iAvail, ip=first check word |
|
522 |
asm("stmfd sp!, {r4-r5,lr} "); |
|
523 |
asm("cmp r1, r3 "); |
|
524 |
asm("movgt r1, r3 "); // if aLength>iAvail, aLength=iAvail |
|
525 |
asm("movs r5, r1 "); // r5 counts allocations |
|
526 |
asm("beq 0f "); // if length 0, exit |
|
527 |
asm("sub r3, r3, r1 "); // reduce available count |
|
528 |
asm("sub r4, ip, r0 "); |
|
529 |
asm("sub r4, r4, #12 "); // r4=offset of first check word from iMap[0]; |
|
530 |
asm("str r3, [r0] "); |
|
531 |
asm("mov r4, r4, lsl #3 "); // r4=bit number of MSB of first check word |
|
532 |
asm("1: "); |
|
533 |
asm("ldr lr, [ip], #4 "); // lr=next word |
|
534 |
asm("cmp lr, #0 "); |
|
535 |
asm("addeq r4, r4, #32 "); // if word=0, increment bit number by 32 and check next word |
|
536 |
asm("beq 1b "); |
|
537 |
asm("mov r3, #1 "); |
|
538 |
asm("sub r4, r4, #1 "); |
|
539 |
asm("2: "); |
|
540 |
asm("mov r3, r3, ror #1 "); // shift mask right one |
|
541 |
asm("add r4, r4, #1 "); // and increment bit number |
|
542 |
asm("tst lr, r3 "); // check next bit |
|
543 |
asm("beq 2b "); |
|
544 |
asm("str r4, [r2], #4 "); // bit=1, so store bit number in list |
|
545 |
asm("subs r5, r5, #1 "); // check if we are finished |
|
546 |
asm("beq 4f "); // branch if we are |
|
547 |
asm("bics lr, lr, r3 "); // clear bit and see if word now empty |
|
548 |
asm("bne 2b "); // if word not empty, get next bit |
|
549 |
asm("str lr, [ip, #-4] "); // word empty - clear word |
|
550 |
asm("add r4, r4, #32 "); // word empty - step bit number on to next word |
|
551 |
asm("bic r4, r4, #31 "); |
|
552 |
asm("b 1b "); // and go to check next word |
|
553 |
asm("4: "); |
|
554 |
asm("bics lr, lr, r3 "); // clear bit |
|
555 |
asm("str lr, [ip, #-4] "); // we are finished - store modified word |
|
556 |
asm("subne ip, ip, #4 "); // if word not empty, first check=last read word |
|
557 |
asm("str ip, [r0, #4] "); // update first check word |
|
558 |
asm("0: "); |
|
559 |
asm("mov r0, r1 "); // return number of positions allocated |
|
560 |
asm("ldmfd sp!, {r4-r5,pc} "); |
|
561 |
} |
|
562 |
||
563 |
||
564 |
/** Find a set of consecutive bit positions with specified alignment, with |
|
565 |
support for chaining multiple allocators. |
|
566 |
Note that this function does not mark the positions as allocated. |
|
567 |
||
568 |
@param aLength number of consecutive bit positions to allocate |
|
569 |
@param aAlign logarithm to base 2 of the alignment required |
|
570 |
@param aBase the alignment of the first bit of this allocator - only significant modulo 2^aAlign |
|
571 |
@param aBestFit TRUE for best fit allocation strategy, FALSE for first fit |
|
572 |
@param aCarry carry in/carry out |
|
573 |
@param aRunLength Holds best run length found so far. This will be set to KMaxTInt when no |
|
574 |
suitable run length has been found. In best fit mode aCarry should also be |
|
575 |
checked as aRunLength will not be set if aCarry is the only suitable run length |
|
576 |
found. |
|
577 |
@param aOffset The bit position to start the search from, set to 0 to search all bit positions. |
|
578 |
aOffset will be aligned so all bits before an aligned aOffset will be |
|
579 |
ignored. This can only be non-zero if aCarry is zero as any carry in bits will be |
|
580 |
ignored if aOffset is non-zero. |
|
581 |
||
582 |
@return Start position if a suitable run was found |
|
583 |
@return KErrNotFound if no suitable run was found |
|
584 |
@return KErrOverflow, if all positions free and best fit mode, or if all positions free |
|
585 |
in first fit mode and length requested > number of positions available. |
|
586 |
||
587 |
@see TBitMapAllocator::AllocConsecutive(TInt aLength, TBool aBestFit) |
|
588 |
@see TBitMapAllocator::AllocAligned(TInt aLength, TInt aAlign, TInt aBase, TBool aBestFit) |
|
589 |
@see ..\bma.cpp for more details |
|
590 |
*/ |
|
591 |
EXPORT_C __NAKED__ TInt TBitMapAllocator::AllocAligned(TInt /*aLength*/, TInt /*aAlign*/, TInt /*aBase*/, |
|
592 |
TBool /*aBestFit*/, TInt& /*aCarry*/, TInt& /*aRunLength*/, |
|
593 |
TUint /*aOffset*/) const |
|
594 |
{ |
|
595 |
// r0=this, r1=aLength, r2=aAlign, r3=aBase, [sp+0]=aBestFit, [sp+4]=&aCarry, [sp+8]=&aRunLength |
|
596 |
// [sp+12] = aOffset. |
|
597 |
asm("ldr r12, [sp, #0] "); // r12=aBestFit |
|
598 |
asm("cmp r1, #0 "); |
|
599 |
asm("ble aa_inv "); // __ASSERT_ALWAYS(aLength>0, TBMA_FAULT()) |
|
600 |
asm("cmp r2, #31 "); |
|
601 |
asm("bhs aa_inv "); // __ASSERT_ALWAYS(TUint(aAlign)<31, TBMA_FAULT()) |
|
602 |
asm("stmfd sp!, {r4-r11,lr} "); |
|
603 |
asm("movs r8, r12 "); // |
|
604 |
asm("ldr r11, [sp, #40] "); // r11=&aCarry |
|
605 |
asm("mvnne r8, #0x80000000 "); // if (aBestFit) r8=7fffffff else r8=0 |
|
606 |
asm("ldmia r0!, {r4-r6} "); // r4=iAvail, r5=iCheckFirst, r6=iSize, r0->iMap[0] |
|
607 |
asm("ldr r12, [sp, #48] "); // r12 = aOffset; |
|
608 |
asm("cmp r6, r12 "); |
|
609 |
asm("bls aa_inv "); // __ASSERT_ALWAYS(aOffset < (TUint)iSize, TBMA_FAULT()) |
|
610 |
asm("ldr r9, [r11] "); // r9=aCarry |
|
611 |
asm("cmp r9, #0 "); |
|
612 |
asm("cmpne r12, #0 "); |
|
613 |
asm("bne aa_inv "); //__ASSERT_ALWAYS(!aCarry || !aOffset, TBMA_FAULT()) |
|
614 |
asm("mov r12, #1 "); |
|
615 |
asm("mov r12, r12, lsl r2 "); // r12=alignsize = 1<<aAlign |
|
616 |
asm("sub r2, r12, #1 "); // r2=alignmask = alignsize-1 |
|
617 |
asm("cmp r4, r6 "); // check for iAvail==iSize |
|
618 |
asm("beq aa_all_free "); // branch if so |
|
619 |
asm("rsbs r9, r9, #0 "); // r9=run start=-aCarry |
|
620 |
asm("movne r5, r0 "); // if carry, pW=iMap |
|
621 |
asm("sub r4, r5, r0 "); // r4=first check address - &iMap[0] |
|
622 |
asm("add r12, r6, #31 "); |
|
623 |
asm("mov r4, r4, lsl #3 "); // r4=bit number of first bit to check |
|
624 |
asm("bic r12, r12, #31 "); // r12=size rounded up to multiple of 32 |
|
625 |
asm("mvn r7, #0 "); // saved bit number (p) |
|
626 |
asm("add r10, r0, r12, lsr #3 "); // r10=end address of bitmap |
|
627 |
asm("str r7, [sp, #-4]! "); // saved bit number (p) onto stack |
|
628 |
asm("movs r11, r9 "); |
|
629 |
asm("mvnne r11, #0 "); // if (aCarry) r0=~0 else r0=0 |
|
630 |
||
631 |
// registers: r0=this->iMap, r1=aLength, r2=alignmask, r3=aBase, r4=current bit number, r5=word pointer |
|
632 |
// r6=iSize, r7=, r8=saved run length, r9=run start pos |
|
633 |
// r10=end address of bitmap, r11=state |
|
634 |
asm("ldr r7, [sp, #52] "); // r7 = aOffset; |
|
635 |
asm("cmp r7, #0 "); // if (aOffset) |
|
636 |
asm("beq aa_word "); |
|
637 |
asm("add r7, r7, r3 "); // r7 = aOffset + aBase |
|
638 |
asm("add r7, r7, r2 "); // r7 = aOffset + aBase + alignmask |
|
639 |
asm("bic r7, r7, r2 "); // r7 = (aOffset + aBase + alignmask) & ~alignmask |
|
640 |
asm("sub r7, r7, r3 "); // r7 -= aBase |
|
641 |
asm("mov r12, r7, lsr #5 "); // r12 = aOffset >> 5 (number of pointer increments required) |
|
642 |
asm("add r0, r0, r12, lsl #2 "); // r0 = offsetWord = iMap + (aOffset >> 5) (pointer add so shift=2) |
|
643 |
asm("cmp r0, r5 "); // if (offsetWord >= pW) |
|
644 |
asm("movpl r5, r0 "); // r5 = pW = offsetWord |
|
645 |
asm("andpl r4, r7, #0xffffffe0 "); // r4 = n = aOffset & 0xffffffe0 |
|
646 |
asm("andpl r7, r7, #31 "); // r7 = aOffset & 31 |
|
647 |
asm("mov r0, #0xffffffff "); // r0 = 0xffffffff |
|
648 |
asm("mov r7, r0, lsr r7 "); // r7 = offsetMask = 0xffffffff >> (aOffset & 31) |
|
649 |
||
650 |
// registers: r0=bit to check (b), r1=aLength, r2=alignmask, r3=aBase, r4=current bit number, r5=word pointer |
|
651 |
// r6=iSize, r7=offsetMask, r8=saved run length, r9=run start pos |
|
652 |
// r10=end address of bitmap, r11=state, r12=word |
|
653 |
asm("aa_word: "); // while (pW < pE) |
|
654 |
asm("cmp r5, r10 "); // reached end? |
|
655 |
asm("ldrlo r12, [r5], #4 "); // if not, r12=next word (=*pW++) |
|
656 |
asm("bhs aa_end_loop "); // if end, branch out |
|
657 |
||
658 |
asm("cmp r7, #0 "); // if (offsetMask) |
|
659 |
asm("andne r12, r12, r7 "); // r12 = word &= offsetMask |
|
660 |
asm("movne r7, #0 "); // offsetmask = 0; |
|
661 |
||
662 |
asm("eors r12, r12, r11 "); // r12=w^s, test if any of required bit present |
|
663 |
asm("addeq r4, r4, #32 "); // if not, increment bit # by 32 |
|
664 |
asm("beq aa_word "); // and do next word |
|
665 |
asm("mov r0, #0x80000000 "); // bit to check (b) |
|
666 |
||
667 |
asm("aa_bit: "); // if ((word ^ s) & b) |
|
668 |
asm("tst r12, r0 "); // does bit have required state? |
|
669 |
asm("bne aa_bit_found "); |
|
670 |
asm("aa_end_for: "); |
|
671 |
asm("add r4, r4, #1 "); // increment bit number |
|
672 |
asm("movs r0, r0, lsr #1 "); // next bit |
|
673 |
asm("bne aa_bit "); // if all bits not done, do next |
|
674 |
asm("b aa_word "); // else do next word |
|
675 |
||
676 |
asm("aa_bit_found: "); |
|
677 |
asm("mvns r12, r12 "); // Invert r12 to invert search bit |
|
678 |
asm("mvns r14, r11 "); // if (s) |
|
679 |
asm("cmpeq r4, r6 "); // && n==iSize |
|
680 |
asm("beq aa_end_loop "); // ... finished |
|
681 |
asm("mvns r11, r11 "); // else s=~s |
|
682 |
asm("movne r9, r4 "); // if (s) q=n (1 found so save position) |
|
683 |
asm("bne aa_end_for "); |
|
684 |
||
685 |
asm("sub r14, r4, r9 "); // r14 = run length = n - q |
|
686 |
asm("stmdb sp!, {r0,r12} "); // store b (r0) and word (r12) on stack |
|
687 |
asm("add r12, r9, r3 "); // r12 = q + aBase |
|
688 |
asm("add r12, r12, r2 "); // r12 = q + aBase + alignmask |
|
689 |
asm("bic r12, r12, r2 "); // r12 = (q + aBase + alignmask) & ~alignmask |
|
690 |
asm("sub r12, r12, r3 "); // r12 = alignedStartPos = r12 - aBase |
|
691 |
asm("sub r0, r12, r9 "); // r0 = lost = alignedStartPos - q |
|
692 |
asm("sub r0, r14, r0 "); // r0 = run length - lost |
|
693 |
asm("cmp r0, r1 "); // if (run length - lost >= aLength) |
|
694 |
asm("ldmltia sp!, {r0,r12} "); // if aligned length too short: r0 = b and r12 = word from stack |
|
695 |
asm("blt aa_end_for "); // (run length - lost) too short (must be signed comparison) |
|
696 |
||
697 |
// if (rl-lost>=aLength) |
|
698 |
||
699 |
asm("cmp r1, r14 "); // check for exact run length match (if (run length == aLength)) |
|
700 |
asm("cmpne r8, #0 "); // check for best fit (r8 only ever set if (aBestfit)) |
|
701 |
asm("beq aa_found_it "); // exact match or not in best fit mode |
|
702 |
||
703 |
// if (r1<minrl) |
|
704 |
asm("cmp r12, #0 "); |
|
705 |
asm("movmi r12, #0 "); // r12 = (alignedStartPos >= 0)? alignedStartPos : 0 |
|
706 |
asm("cmp r14, r8 "); // Compare run length with current minimum |
|
707 |
asm("movlo r8, r14 "); // if shorter, replace |
|
708 |
asm("strlo r12, [sp, #8] "); // save alignedStartPos (p = (alignedStartPos >= 0)? alignedStartPos : 0) |
|
709 |
asm("ldmia sp!, {r0,r12} "); // r0 = b and r12 = word from stack |
|
710 |
asm("b aa_end_for "); // next bit |
|
711 |
// end {if (r1<minrl)} |
|
712 |
||
713 |
// if (!aBestFit || run length == aLength) |
|
714 |
// registers: r12 = alignedStartPos, r14 = run length |
|
715 |
asm("aa_found_it: "); |
|
716 |
asm("ldr r1, [sp, #52] "); // r1=&aCarry |
|
717 |
asm("ldr r7, [sp, #56] "); // r7=&aRunLength |
|
718 |
asm("subs r0, r12, #0 "); // r0 = alignStartPos, alignedStartPos >= 0? |
|
719 |
asm("movmi r0, #0 "); // if alignedStartPos < 0 r0=0 |
|
720 |
asm("str r14, [r7] "); // aRunLength = run length |
|
721 |
asm("mov r14, #0 "); |
|
722 |
asm("strge r14, [r1] "); // if (alignedStartPos >= 0), aCarry=0 |
|
723 |
asm("ldmfd sp!, {r1-r11,pc} "); // return |
|
724 |
// end {if (!aBestFit || run length == aLength)} |
|
725 |
||
726 |
// end {if (rl-lost>=aLength)} |
|
727 |
||
728 |
asm("aa_end_loop: "); |
|
729 |
asm("ldr r10, [sp, #48] "); // r10=&aRunLength |
|
730 |
||
731 |
// registers: r2 = alignmask, r3 = aBase, r4=current bit number(n), |
|
732 |
// r9=run start pos(q), r10=&aRunLength, r11 = state(s), r14 = run length(rl) |
|
733 |
asm("cmp r8, r1 "); // compare min rl with aLength |
|
734 |
asm("beq aa_end_loop2 "); // if exact match, skip |
|
735 |
||
736 |
// if (minrl != aLength) |
|
737 |
asm("ldr r12, [sp, #44] "); // r12=&aCarry |
|
738 |
asm("mov r14, #0 "); // r14 = run length = 0 |
|
739 |
asm("cmp r11, #0 "); |
|
740 |
asm("beq aa_end_loop3 "); // if (!s) no final run |
|
741 |
asm("sub r14, r4, r9 "); // rl4 = run length = n-q |
|
742 |
asm("cmp r8, #0 "); // if (!aBestFit) (r8 only and always set when best fit mode) |
|
743 |
asm("bne aa_end_loop3 "); // if best fit, don't count final run |
|
744 |
||
745 |
// if (!aBestFit) |
|
746 |
asm("add r0, r9, r3 "); // r0 = q + aBase |
|
747 |
asm("add r0, r0, r2 "); // r0 = q + aBase + alignmask |
|
748 |
asm("bic r0, r0, r2 "); // r0 = (q + aBase + alignmask) & ~alignmask |
|
749 |
asm("sub r0, r0, r3 "); // r0 = alignedStartPos = r0 -= aBase |
|
750 |
asm("sub r2, r0, r9 "); // r2 = lost = alignedStartPos - q |
|
751 |
asm("sub r2, r14, r2 "); // r2 = run length - lost |
|
752 |
asm("cmp r2, r1 "); // if (run length - lost >= aLength) |
|
753 |
asm("blt aa_end_loop3 "); |
|
754 |
||
755 |
// if (run length - lost >= aLength) |
|
756 |
asm("mov r8, r14 "); // r8 = run length (ready to be stored in return) |
|
757 |
asm("mov r14, #0 "); // r14 = 0 (aCarry on return) |
|
758 |
asm("str r0, [sp, #0] "); // Save alignedStartPos on stack ready for return |
|
759 |
||
760 |
// end {if (run length - lost >= aLength)} |
|
761 |
// end {if (!aBestFit)} |
|
762 |
||
763 |
asm("aa_end_loop3: "); |
|
764 |
asm("str r14, [r12] "); // Save aCarry = run length = r14 |
|
765 |
// end {if (minrl != aLength)} |
|
766 |
||
767 |
asm("aa_end_loop2: "); |
|
768 |
asm("str r8, [r10] "); // aRunLength = minrl |
|
769 |
asm("ldmfd sp!, {r0,r4-r11,pc} "); // return saved pos |
|
770 |
||
771 |
// r1 = aLength r2 = alignmask, r3 = aBase, r4 = iAvail, r6 = iSize, r9 = aCarry, r11 = &aCarry |
|
772 |
asm("aa_all_free: "); |
|
773 |
asm("ldr r12, [sp, #48] "); // r12 = aOffset; |
|
774 |
asm("cmp r12, #0 "); // if (aOffset) |
|
775 |
asm("addne r12, r12, r3 "); // r12 = aOffset + aBase |
|
776 |
asm("addne r12, r12, r2 "); // r12 = aOffset + aBase + alignmask |
|
777 |
asm("bicne r12, r12, r2 "); // r12 = (aOffset + aBase + alignmask)&~alignmask |
|
778 |
asm("subne r12, r12, r3 "); // r12 = ((aOffset + aBase + alignmask)&~alignmask) - aBase |
|
779 |
asm("subs r10, r6, r12 "); // r10 = runLength = iSize - aOffset |
|
780 |
asm("movmi r10, #0 "); // if (aOffset < (TUint)iSize) runLength = 0; |
|
781 |
||
782 |
asm("movs r0, r8 "); // best fit? if not, r0=0 |
|
783 |
asm("bne aa_all_free2 "); // skip if best fit mode |
|
784 |
asm("sub r6, r12, r9 "); // r6=aOffset-aCarry |
|
785 |
asm("add r6, r6, r3 "); // r6=aOffset-aCarry+aBase |
|
786 |
asm("add r6, r6, r2 "); // r6=aOffset-aCarry+aBase+alignmask |
|
787 |
asm("bic r6, r6, r2 "); // r6=(aOffset-aCarry+aBase+alignmask)&~alignmask |
|
788 |
asm("sub r6, r6, r3 "); // r6 = alignedStartPos |
|
789 |
asm("sub r3, r12, r9 "); // r3 = aOffset - aCarry |
|
790 |
asm("sub r3, r6, r3 "); // r3 = lost = alignedStartPos - (aOffset - aCarry) |
|
791 |
asm("add r2, r10, r9 "); // r2 = aRunLength + aCarry |
|
792 |
asm("sub r2, r2, r3 "); // r2 -= lost |
|
793 |
asm("cmp r2, r1 "); // if (aRunLength + aCarry - lost >= aLength) |
|
794 |
asm("blt aa_all_free2 "); |
|
795 |
asm("cmp r6, #0 "); |
|
796 |
asm("ldr r5, [sp, #44] "); // r5 = &RunLength |
|
797 |
asm("str r10, [r5] "); // Save aRunLength (aRunLength = runLength) |
|
798 |
asm("movge r9, #0 "); // if (alignedStartPos >= 0) aCarry = 0; |
|
799 |
asm("str r9, [r11] "); // Save aCarry |
|
800 |
asm("movge r0, r6 "); // r0 = (alignedStartPos >= 0)? alignedStartPos : 0 |
|
801 |
asm("ldmfd sp!, {r4-r11,pc} "); // return r0 |
|
802 |
||
803 |
asm("aa_all_free2: "); |
|
804 |
asm("ldr r12, [sp, #48] "); // r12 = aOffset; |
|
805 |
asm("cmp r12, #0 "); // if (aOffset) |
|
806 |
asm("movne r9, r10 "); // r9 = aCarry = runLength |
|
807 |
asm("addeq r9, r9, r4 "); // r9 = aCarry + iAvail |
|
808 |
asm("str r9, [r11] "); // Save aCarry |
|
809 |
asm("ldr r5, [sp, #44] "); // r5 = &RunLength |
|
810 |
asm("mov r0, #%a0" : : "i" ((TInt)KMaxTInt)); |
|
811 |
asm("str r0, [r5] "); // aRunLength = KMaxTInt |
|
812 |
asm("mov r0, #%a0" : : "i" ((TInt)KErrOverflow)); |
|
813 |
asm("ldmfd sp!, {r4-r11,pc} "); // return KErrOverflow |
|
814 |
||
815 |
asm("aa_inv: "); |
|
816 |
ASM_FAULT(); |
|
817 |
} |
|
818 |
#endif |