author | Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com> |
Tue, 11 May 2010 17:28:22 +0300 | |
branch | RCL_3 |
changeset 26 | c734af59ce98 |
parent 22 | 2f92ad2dc5db |
permissions | -rw-r--r-- |
0 | 1 |
// Copyright (c) 1999-2009 Nokia Corporation and/or its subsidiary(-ies). |
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// All rights reserved. |
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// This component and the accompanying materials are made available |
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// under the terms of the License "Eclipse Public License v1.0" |
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// which accompanies this distribution, and is available |
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// at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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// |
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// Initial Contributors: |
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// Nokia Corporation - initial contribution. |
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// |
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// Contributors: |
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// |
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// Description: |
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// e32test\realtime\d_latncy.cpp |
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// |
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// |
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#include "platform.h" |
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#if defined(__MEIG__) |
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#include <cl7211.h> |
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#elif defined(__MAWD__) |
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#include <windermere.h> |
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#elif defined(__MISA__) |
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#include <sa1100.h> |
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#elif defined(__MCOT__) |
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#include <cotulla.h> |
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#elif defined(__MI920__) || defined(__NI1136__) |
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#include <integratorap.h> |
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//#define FREE_RUNNING_MODE // runs the millisecond timer in free running mode |
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#elif defined(__IS_OMAP1610__) |
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#include <omap_timer.h> |
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#include <omap_plat.h> |
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#elif defined(__IS_OMAP2420__) || defined(__WAKEUP_3430__) |
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#include <omap_hw.h> |
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#include <shared_instrtimer.h> |
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#elif defined(__EPOC32__) && defined(__CPU_X86) |
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#include <x86.h> |
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#include <x86pc.h> |
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#elif defined(__RVEMUBOARD__) |
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#include <rvemuboard.h> |
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#elif defined(__NE1_TB__) |
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#include <upd35001_timer.h> |
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#endif |
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#ifdef __CPU_ARM |
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#include <arm.h> |
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#endif |
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#include <kernel/kern_priv.h> //temporary |
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#include "d_latncy.h" |
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_LIT(KLddName,"Latency"); |
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_LIT(KThreadName,"LatencyThreadK"); |
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#if defined(__MEIG__) |
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const TInt KTickPeriodMs=2; |
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const TInt KTicksPerMillisecond=512; |
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#elif defined(__MAWD__) |
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const TInt KTickPeriodMs=1; |
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const TInt KTicksPerMillisecond=512; |
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#elif defined(__MISA__) || defined(__MCOT__) |
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const TInt KTicksPerMillisecond=3686; |
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const TInt KOstTicks=3685; // not quite 1ms, so it goes in and out of phase with ms timer |
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TUint TriggerTime; |
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#elif defined(__MI920__) || defined(__NI1136__) |
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const TInt KTickPeriodMs=1; |
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#if defined(__MI920__) || defined(__NI1136__) |
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#ifdef FREE_RUNNING_MODE |
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const TInt KTicksPerMillisecond=1500; |
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#else |
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const TInt KTicksPerMillisecond=24000; |
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#endif |
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#endif |
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#elif defined(__IS_OMAP1610__) |
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const TInt KTickPeriodMs=1; |
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TInt KTicksPerMillisecond = TOmapPlat::GetInputClk()/32000; |
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#elif defined(__IS_OMAP2420__) || defined(__WAKEUP_3430__) |
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const TInt KTickPeriodMs=1; // defined for compatibility but not used (ignored) |
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const TInt KTicksPerMillisecond = 12000; // Hard coded (12Mhz) |
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#elif defined(__EPOC32__) && defined(__CPU_X86) |
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const TInt KTickPeriodMs=1; |
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const TInt KTicksPerMillisecond=1193; |
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#elif defined(__RVEMUBOARD__) |
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const TInt KTickPeriodMs=1; |
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const TInt KTicksPerMillisecond=1000; |
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#elif defined(__NE1_TB__) |
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const TInt KTickPeriodMs=1; |
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const TInt KTicksPerMillisecond=66667; |
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2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
4
diff
changeset
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#elif defined(__MRAP__) |
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
4
diff
changeset
|
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const TInt KTickPeriodMs=1; |
2f92ad2dc5db
Revision: 201013
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
4
diff
changeset
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const TInt KTicksPerMillisecond=1000; |
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#endif |
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#ifdef _DEBUG |
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const TInt KFudgeFactor=1; |
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#else |
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const TInt KFudgeFactor=1; |
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#endif |
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class DDeviceLatency : public DLogicalDevice |
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{ |
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public: |
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DDeviceLatency(); |
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virtual TInt Install(); |
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virtual void GetCaps(TDes8& aDes) const; |
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virtual TInt Create(DLogicalChannelBase*& aChannel); |
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}; |
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class DLatencyPowerHandler : public DPowerHandler |
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{ |
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public: // from DPOwerHandler |
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void PowerUp(); |
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void PowerDown(TPowerState); |
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public: |
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DLatencyPowerHandler(DLatency* aChannel); |
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public: |
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DLatency* iChannel; |
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}; |
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inline TUint DLatency::Ticks() |
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{ |
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#if defined(__MEIG__) |
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return KTicksPerMillisecond-(*(volatile TUint*)(KEigerTimer2Data16+KEigerBaseAddress)&0xffff); |
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#elif defined(__MAWD__) |
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return KTicksPerMillisecond-(*(volatile TUint*)(KWindTimer2Value16+KWindBaseAddress)&0xffff); |
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#elif defined(__MISA__) || defined(__MCOT__) |
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return *(volatile TUint*)KHwRwOstOscr-iTriggerTime; |
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#elif defined(__MI920__) || defined(__NI1136__) |
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return KTicksPerMillisecond-(*(volatile TUint*)(KHwCounterTimer2+KHoTimerValue)&0xffff); |
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#elif defined(__IS_OMAP1610__) |
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return KTicksPerMillisecond - *(volatile TUint*)(KHwBaseOSTimer1Reg+KHoOSTimer_READ_TIM); |
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#elif defined(__IS_OMAP2420__) || defined(__WAKEUP_3430__) |
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return (*(volatile TUint*)(iTimerInfo.iAddress + KHoGpTimer_TCRR)) - iTimerLoadValue; |
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#elif defined(__X86PC__) |
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return 1194 - __HwTimer(); |
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#elif defined(__RVEMUBOARD__) |
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return KTicksPerMillisecond-(*(volatile TUint*)(KHwCounterTimer1+KHoTimerValue)&0xffff); |
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#elif defined(__NE1_TB__) |
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return NETimer::Timer(0).iTimerCount; // counts up, reset timer + interrupt on match |
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#endif |
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} |
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#if !defined(__SMP__) |
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#if !defined(__EPOC32__) || !defined(__CPU_X86) |
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extern TUint IntStackPtr(); |
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#endif |
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#endif |
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DECLARE_STANDARD_LDD() |
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{ |
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return new DDeviceLatency; |
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} |
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DDeviceLatency::DDeviceLatency() |
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// |
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// Constructor |
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// |
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{ |
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//iParseMask=0; |
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//iUnitsMask=0; |
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iVersion=TVersion(1,0,1); |
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} |
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TInt DDeviceLatency::Install() |
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// |
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// Install the device driver. |
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// |
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{ |
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TInt r=SetName(&KLddName); |
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return r; |
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} |
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void DDeviceLatency::GetCaps(TDes8& aDes) const |
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// |
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// Return the Comm capabilities. |
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// |
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{ |
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} |
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TInt DDeviceLatency::Create(DLogicalChannelBase*& aChannel) |
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// |
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// Create a channel on the device. |
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// |
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{ |
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aChannel=new DLatency; |
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return aChannel?KErrNone:KErrNoMemory; |
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} |
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DLatency::DLatency() |
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: iMsCallBack(MsCallBack,this), |
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iMsDfc(MsDfc,this,NULL,1) |
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// |
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// Constructor |
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// |
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{ |
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#if !defined(__SMP__) |
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#if !defined(__EPOC32__) || !defined(__CPU_X86) |
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iIntStackTop=(TUint*)IntStackPtr(); |
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#endif |
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#endif |
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#if defined(__MISA__) || defined(__MCOT__) |
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iTickIncrement=KOstTicks*KFudgeFactor; |
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#endif |
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#if defined(__IS_OMAP2420__) || defined(__WAKEUP_3430__) |
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iTimerInfo.iAddress = 0; |
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#endif |
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} |
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DLatency::~DLatency() |
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// |
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// Destructor |
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// |
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{ |
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iOff = (TUint8)ETrue; |
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StopTimer(); |
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iMsDfc.Cancel(); |
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if (iRtDfcQ) |
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iRtDfcQ->Destroy(); |
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if (iPowerHandler) |
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{ |
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iPowerHandler->Remove(); |
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delete iPowerHandler; |
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} |
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Kern::SafeClose((DObject*&)iClient, NULL); |
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} |
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TInt DLatency::DoCreate(TInt /*aUnit*/, const TDesC8* /*anInfo*/, const TVersion& aVer) |
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// |
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// Create the channel from the passed info. |
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// |
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{ |
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if (!Kern::QueryVersionSupported(TVersion(1,0,1),aVer)) |
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return KErrNotSupported; |
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// create the power handler |
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iPowerHandler = new DLatencyPowerHandler(this); |
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if (!iPowerHandler) |
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return KErrNoMemory; |
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iPowerHandler->Add(); |
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// Allocate a kernel thread to run the DFC |
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TInt r = Kern::DynamicDfcQCreate(iRtDfcQ, KNumPriorities-1,KThreadName); |
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if (r != KErrNone) |
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4
56f325a607ea
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
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return r; |
56f325a607ea
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
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|
56f325a607ea
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
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#ifdef CPU_AFFINITY_ANY |
56f325a607ea
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
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NKern::ThreadSetCpuAffinity((NThread*)(iRtDfcQ->iThread), KCpuAffinityAny); |
56f325a607ea
Revision: 200951
Dremov Kirill (Nokia-D-MSW/Tampere) <kirill.dremov@nokia.com>
parents:
0
diff
changeset
|
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#endif |
0 | 256 |
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iMsDfc.SetDfcQ(iRtDfcQ); |
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iClient=&Kern::CurrentThread(); |
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iClient->Open(); |
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Kern::SetThreadPriority(KNumPriorities-2); |
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return KErrNone; |
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} |
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#if defined(__MISA__) |
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// For SA1100/SA1110 use a separate timer on a FIQ interrupt (OST match 0) |
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TInt DLatency::StartTimer() |
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{ |
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TInt r=Interrupt::Bind(KIntIdOstMatchGeneral,MsCallBack,this); |
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if (r==KErrNone) |
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{ |
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TSa1100::ModifyIntLevels(0,KHtIntsOstMatchGeneral); // route new timer interrupt to FIQ |
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TSa1100::SetOstMatchEOI(KHwOstMatchGeneral); |
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TUint oscr=TSa1100::OstData(); |
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iTriggerTime=oscr+KOstTicks*KFudgeFactor; |
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TSa1100::SetOstMatch(KHwOstMatchGeneral,iTriggerTime); |
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TSa1100::EnableOstInterrupt(KHwOstMatchGeneral); |
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Interrupt::Enable(KIntIdOstMatchGeneral); |
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} |
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return r; |
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} |
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#elif defined(__MCOT__) |
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// For Cotulla use a separate timer on a FIQ interrupt (OST match 0) |
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TInt DLatency::StartTimer() |
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{ |
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TInt r=Interrupt::Bind(KIntIdOstMatchGeneral,MsCallBack,this); |
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if (r==KErrNone) |
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{ |
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TCotulla::ModifyIntLevels(0,KHtIntsOstMatchGeneral); // route new timer interrupt to FIQ |
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TCotulla::SetOstMatchEOI(KHwOstMatchGeneral); |
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TUint oscr=TCotulla::OstData(); |
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iTriggerTime=oscr+KOstTicks*KFudgeFactor; |
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TCotulla::SetOstMatch(iTriggerTime,KHwOstMatchGeneral); |
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TCotulla::EnableOstInterrupt(KHwOstMatchGeneral); |
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Interrupt::Enable(KIntIdOstMatchGeneral); |
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} |
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return r; |
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} |
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#elif defined(__IS_OMAP2420__) || defined(__WAKEUP_3430__) |
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TInt DLatency::StartTimer() |
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/* |
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* For OMAP2420 initialise a new timer to generate an interrupt every 1ms |
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*/ |
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{ |
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__ASSERT_ALWAYS(!iTimerInfo.iAddress, Kern::Fault("D_Latncy: timer allocated twice.", |
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iTimerInfo.iAddress)); |
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// Get an available Timer from the system |
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TInt r = OmapTimerMgr::GetTimer(iGPTimerId, iTimerInfo); |
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if (KErrNone != r) |
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{ |
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return r; |
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} |
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// Configure the timer |
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r = ConfigureTimer(); |
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if (KErrNone != r) |
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{ |
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DisableTimer(); |
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return r; |
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} |
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// Bind to timer interrupt |
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r = Interrupt::Bind(iTimerInfo.iInterruptId, MsCallBack, this); |
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if (KErrNone != r) |
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{ |
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DisableTimer(); |
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return r; |
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} |
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// Unmask timer IT in interrupt controller |
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r = Interrupt::Enable(iTimerInfo.iInterruptId); |
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if (KErrNone != r) |
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{ |
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Interrupt::Unbind(iTimerInfo.iInterruptId); |
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DisableTimer(); |
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return r; |
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} |
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// Start timer |
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TOmap::ModifyRegister32(iTimerInfo.iAddress + KHoGpTimer_TCLR, KClear32, |
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KHtGpTimer_TCLR_St); |
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return KErrNone; |
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} |
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void DLatency::DisableTimer() |
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/* |
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* Disable the interface and functional clock and mark the timer as available |
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*/ |
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{ |
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// Stop timer |
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TOmap::ModifyRegister32(iTimerInfo.iAddress + KHoGpTimer_TCLR, |
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KHtGpTimer_TCLR_St, KClear32); |
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#if defined(__WAKEUP_3430__) |
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// Disable Timer clocks using Timer framework instead of using TPRcm direct calls for 3430 |
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TInt r = OmapTimerMgr::DisableClocks(iGPTimerId); |
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if (r != KErrNone) |
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__ASSERT_ALWAYS(r, Kern::Fault("Timer clocks disable failed", 0)) ; |
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#else |
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// Disable timer interface clock in PRCM |
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TPrcm::InterfaceClkCtrl(iTimerInfo.iPrcmDeviceId, EFalse); |
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// Disable timer functional clock in PRCM |
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TPrcm::FunctionalClkCtrl(iTimerInfo.iPrcmDeviceId, EFalse); |
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#endif |
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// Release the timer |
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OmapTimerMgr::ReleaseTimer(iGPTimerId); |
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iTimerInfo.iAddress = 0; |
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} |
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TInt DLatency::ConfigureTimer() |
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/* |
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* This method will configure a timer to: |
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* - run at the system clock (12Mhz) |
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* - no prescaler (disable TCLR[PRE]) |
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* - autoreload and overflow interrupt enabled (TLDR will contain a |
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* value to generate an interrupt every 1000microsec) |
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*/ |
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{ |
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#if defined(__WAKEUP_3430__) |
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// Enable Timer clocks using timer framework instead of TPrcm direct calls for 3430 |
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TInt r = OmapTimerMgr::EnableClocks(iGPTimerId); |
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if (r != KErrNone) |
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__ASSERT_ALWAYS(r, Kern::Fault("Timer Clocks enable failed", 0)) ; |
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// Select the input clock to be system clock |
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r = OmapTimerMgr::SetTimerClkSrc(iGPTimerId, ESysClk); |
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#else |
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// Enable timer interface clock in PRCM |
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TPrcm::InterfaceClkCtrl(iTimerInfo.iPrcmDeviceId, ETrue, ETrue); |
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// Enable timer functional clock in PRCM |
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TPrcm::FunctionalClkCtrl(iTimerInfo.iPrcmDeviceId, ETrue, ETrue); |
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// Select the input clock to be system clock |
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TInt r = OmapTimerMgr::SetTimerClkSrc(iGPTimerId, ESysClk); |
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#endif |
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if (KErrNone != r) |
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return r; |
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// Timer OCP configuration: - software reset |
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TOmap::SetRegister32( iTimerInfo.iAddress + KHoGpTimerTIOCP_CFG, |
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KHtGpTimer_TIOCP_CFG_SoftReset); |
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// Wait for reset to be complete |
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TUint16 timeOut = 1000; |
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while ( !(TOmap::Register32(iTimerInfo.iAddress + KHoGpTimer_TISTAT) & |
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KHtGpTimer_TISTAT_ResetComplete) |
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&& --timeOut); |
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// Check if the timer has been reset or we hit the timeout |
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__ASSERT_ALWAYS((TOmap::Register32(iTimerInfo.iAddress + KHoGpTimer_TISTAT) & |
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KHtGpTimer_TISTAT_ResetComplete), Kern::Fault("D_Latncy: failed to reset timer.", |
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iGPTimerId)); |
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||
421 |
// Set PRE to be 0, PTV value is ignored, AutoReload is enabled |
|
422 |
TOmap::SetRegister32(iTimerInfo.iAddress + KHoGpTimer_TCLR, KHtGpTimer_TCLR_AR ); |
|
423 |
||
424 |
//PTV argument is 0 because of TCLR[PRE] = 0 (prescaling disabled) |
|
425 |
TInt timerPTV = 0; |
|
426 |
||
427 |
// Calculate clock frequence from the ticks per ms |
|
428 |
TInt timerClkSrcFreq = KTicksPerMillisecond * 1000; |
|
429 |
||
430 |
iTimerLoadValue = OmapTimerMgr::TimerLoadValue(/*microsecs*/1000, timerClkSrcFreq, timerPTV); |
|
431 |
||
432 |
// First, load value in TCRR and TLDR registers |
|
433 |
TOmap::SetRegister32(iTimerInfo.iAddress + KHoGpTimer_TCRR, iTimerLoadValue); |
|
434 |
TOmap::SetRegister32(iTimerInfo.iAddress + KHoGpTimer_TLDR, iTimerLoadValue); |
|
435 |
||
436 |
// Enable overflow interrupt |
|
437 |
TOmap::SetRegister32(iTimerInfo.iAddress + KHoGpTimer_TIER, |
|
438 |
KHtGpTimer_TIER_OverFlow); |
|
439 |
||
440 |
return KErrNone; |
|
441 |
} |
|
442 |
#else |
|
443 |
TInt DLatency::StartTimer() |
|
444 |
{ |
|
445 |
iMsCallBack.OneShot(KTickPeriodMs*KFudgeFactor); |
|
446 |
return KErrNone; |
|
447 |
} |
|
448 |
#endif |
|
449 |
||
450 |
#if defined(__MISA__) |
|
451 |
// For SA1100/SA1110 use a separate timer on a FIQ interrupt (OST match 0) |
|
452 |
void DLatency::StopTimer() |
|
453 |
{ |
|
454 |
TSa1100::ModifyIntLevels(KHtIntsOstMatchGeneral,0); |
|
455 |
TSa1100::DisableOstInterrupt(KHwOstMatchGeneral); |
|
456 |
Interrupt::Disable(KIntIdOstMatchGeneral); |
|
457 |
Interrupt::Unbind(KIntIdOstMatchGeneral); |
|
458 |
TSa1100::SetOstMatchEOI(KHwOstMatchGeneral); |
|
459 |
} |
|
460 |
#elif defined(__MCOT__) |
|
461 |
// For Cotulla use a separate timer on a FIQ interrupt (OST match 0) |
|
462 |
void DLatency::StopTimer() |
|
463 |
{ |
|
464 |
TCotulla::ModifyIntLevels(KHtIntsOstMatchGeneral,0); |
|
465 |
TCotulla::DisableOstInterrupt(KHwOstMatchGeneral); |
|
466 |
Interrupt::Disable(KIntIdOstMatchGeneral); |
|
467 |
Interrupt::Unbind(KIntIdOstMatchGeneral); |
|
468 |
TCotulla::SetOstMatchEOI(KHwOstMatchGeneral); |
|
469 |
} |
|
470 |
#elif defined(__IS_OMAP2420__) || defined(__WAKEUP_3430__) |
|
471 |
void DLatency::StopTimer() |
|
472 |
{ |
|
473 |
Interrupt::Disable(iTimerInfo.iInterruptId); |
|
474 |
Interrupt::Unbind(iTimerInfo.iInterruptId); |
|
475 |
DisableTimer(); |
|
476 |
} |
|
477 |
#else |
|
478 |
void DLatency::StopTimer() |
|
479 |
{ |
|
480 |
iMsCallBack.Cancel(); |
|
481 |
} |
|
482 |
#endif |
|
483 |
||
484 |
TInt DLatency::Request(TInt aFunction, TAny* a1, TAny* a2) |
|
485 |
// |
|
486 |
// Client requests |
|
487 |
// |
|
488 |
{ |
|
489 |
// Kern::Printf("DLatency::Request() 0x%x)\n", aFunction); |
|
490 |
TInt r=KErrNone; |
|
491 |
switch (aFunction) |
|
492 |
{ |
|
493 |
case RLatency::EControlStart: |
|
494 |
iStarted = (TUint8)ETrue; |
|
495 |
StartTimer(); |
|
496 |
break; |
|
497 |
case RLatency::EControlTicksPerMs: |
|
498 |
r=KTicksPerMillisecond; |
|
499 |
break; |
|
500 |
case RLatency::EControlGetResults: |
|
501 |
iResults.iUserThreadTicks = Ticks(); |
|
502 |
kumemput32(a1, &iResults, sizeof(SLatencyResults)); |
|
503 |
break; |
|
504 |
default: |
|
505 |
r = KErrNotSupported; |
|
506 |
break; |
|
507 |
} |
|
508 |
return(r); |
|
509 |
} |
|
510 |
||
511 |
#ifdef __CAPTURE_EXTRAS |
|
512 |
extern void CaptureExtras(SLatencyResults&); |
|
513 |
#endif |
|
514 |
||
515 |
#if !defined(__MISA__) && !defined(__MCOT__) |
|
516 |
void DLatency::MsCallBack(TAny* aPtr) |
|
517 |
{ |
|
518 |
DLatency* pL = (DLatency*)aPtr; |
|
519 |
#if defined(__IS_OMAP2420__) || defined(__WAKEUP_3430__) |
|
520 |
pL->iResults.iIntTicks = pL->Ticks(); |
|
521 |
TOmap::SetRegister32(pL->iTimerInfo.iAddress + KHoGpTimer_TISR, KHtGpTimer_TISR_OverFlow); |
|
522 |
#else |
|
523 |
pL->iResults.iIntTicks = Ticks(); |
|
524 |
#endif |
|
525 |
#ifdef __CAPTURE_EXTRAS |
|
526 |
CaptureExtras(pL->iResults); |
|
527 |
#endif |
|
528 |
#if defined(__EPOC32__) && defined(__CPU_X86) |
|
529 |
pL->iResults.iIntRetAddr = X86::IrqReturnAddress(); |
|
530 |
#elif defined(__CPU_ARM) && defined(__SMP__) |
|
531 |
pL->iResults.iIntRetAddr = Arm::IrqReturnAddress(); |
|
532 |
#else |
|
533 |
pL->iResults.iIntRetAddr=(pL->iIntStackTop)[-1]; |
|
534 |
#endif |
|
535 |
if (!pL->iOff) |
|
536 |
{ |
|
537 |
pL->iMsCallBack.Again(KTickPeriodMs*KFudgeFactor); |
|
538 |
pL->iMsDfc.Add(); |
|
539 |
} |
|
540 |
} |
|
541 |
#endif |
|
542 |
||
543 |
void DLatency::MsDfc(TAny* aPtr) |
|
544 |
{ |
|
545 |
DLatency* pL = (DLatency*)aPtr; |
|
546 |
pL->iResults.iKernThreadTicks=pL->Ticks(); |
|
547 |
NKern::ThreadRequestSignal(&pL->iClient->iNThread); |
|
548 |
} |
|
549 |
||
550 |
DLatencyPowerHandler::DLatencyPowerHandler(DLatency* aChannel) |
|
551 |
: DPowerHandler(KLddName), |
|
552 |
iChannel(aChannel) |
|
553 |
{ |
|
554 |
} |
|
555 |
||
556 |
void DLatencyPowerHandler::PowerUp() |
|
557 |
{ |
|
558 |
iChannel->iOff = (TUint8)EFalse; |
|
559 |
if (iChannel->iStarted) |
|
560 |
iChannel->StartTimer(); |
|
561 |
PowerUpDone(); |
|
562 |
} |
|
563 |
||
564 |
void DLatencyPowerHandler::PowerDown(TPowerState) |
|
565 |
{ |
|
566 |
iChannel->iOff = (TUint8)ETrue; |
|
567 |
iChannel->StopTimer(); |
|
568 |
PowerDownDone(); |
|
569 |
} |
|
570 |
||
571 |
||
572 |