0
|
1 |
// Copyright (c) 1994-2009 Nokia Corporation and/or its subsidiary(-ies).
|
|
2 |
// All rights reserved.
|
|
3 |
// This component and the accompanying materials are made available
|
|
4 |
// under the terms of the License "Eclipse Public License v1.0"
|
|
5 |
// which accompanies this distribution, and is available
|
|
6 |
// at the URL "http://www.eclipse.org/legal/epl-v10.html".
|
|
7 |
//
|
|
8 |
// Initial Contributors:
|
|
9 |
// Nokia Corporation - initial contribution.
|
|
10 |
//
|
|
11 |
// Contributors:
|
|
12 |
//
|
|
13 |
// Description:
|
|
14 |
// e32\memmodel\epoc\multiple\arm\xkernel.cpp
|
|
15 |
//
|
|
16 |
//
|
|
17 |
|
|
18 |
#include "arm_mem.h"
|
|
19 |
|
|
20 |
|
|
21 |
/********************************************
|
|
22 |
* Thread
|
|
23 |
********************************************/
|
|
24 |
|
|
25 |
TInt DArmPlatThread::SetupContext(SThreadCreateInfo& aInfo)
|
|
26 |
{
|
|
27 |
switch(iThreadType)
|
|
28 |
{
|
|
29 |
case EThreadSupervisor:
|
|
30 |
case EThreadMinimalSupervisor:
|
|
31 |
case EThreadInitial:
|
|
32 |
case EThreadAPInitial:
|
|
33 |
break;
|
|
34 |
case EThreadUser:
|
|
35 |
#ifndef __SMP__
|
|
36 |
iNThread.iSpare3 /*iUserContextType*/ = NThread::EContextUndefined;
|
|
37 |
#endif
|
|
38 |
break;
|
|
39 |
}
|
|
40 |
iNThread.SetAddressSpace(iOwningProcess);
|
|
41 |
iNThread.SetAttributes(KThreadAttAddressSpace);
|
|
42 |
iAliasPdePtr = &PageDirectory(((DMemModelProcess*)iOwningProcess)->iOsAsid)[KIPCAlias>>KChunkShift];
|
|
43 |
return KErrNone;
|
|
44 |
}
|
|
45 |
|
|
46 |
/********************************************
|
|
47 |
* Process
|
|
48 |
********************************************/
|
|
49 |
|
|
50 |
DArmPlatProcess::DArmPlatProcess()
|
|
51 |
{
|
|
52 |
iAddressCheckMaskR=0x000fffffu; // addresses<0xA0000000 OK
|
|
53 |
iAddressCheckMaskW=0x0000ffffu; // addresses<0x80000000 OK
|
|
54 |
}
|
|
55 |
|
|
56 |
void FlushTLBs();
|
|
57 |
DArmPlatProcess::~DArmPlatProcess()
|
|
58 |
{
|
|
59 |
__KTRACE_OPT(KMMU,Kern::Printf("DArmPlatProcess destruct"));
|
|
60 |
FlushTLBs();
|
|
61 |
DMemModelProcess::Destruct();
|
|
62 |
}
|
|
63 |
|
|
64 |
TInt DArmPlatProcess::GetNewChunk(DMemModelChunk*& aChunk, SChunkCreateInfo& aInfo)
|
|
65 |
{
|
|
66 |
aChunk=NULL;
|
|
67 |
DArmPlatChunk* pC=new DArmPlatChunk;
|
|
68 |
if (!pC)
|
|
69 |
return KErrNoMemory;
|
|
70 |
aChunk=pC;
|
|
71 |
TChunkType type = aInfo.iType;
|
|
72 |
pC->iChunkType=type;
|
|
73 |
TInt r=pC->SetAttributes(aInfo);
|
|
74 |
if(r==KErrNone)
|
|
75 |
{
|
|
76 |
if(type==ESharedKernelSingle || type==ESharedKernelMultiple || type==ESharedIo)
|
|
77 |
{
|
|
78 |
DArmPlatChunk* pM=new DArmPlatChunk;
|
|
79 |
if (!pM)
|
|
80 |
return KErrNoMemory;
|
|
81 |
pC->iKernelMirror = pM;
|
|
82 |
pM->iChunkType = ESharedKernelMirror;
|
|
83 |
r=pM->SetAttributes(aInfo);
|
|
84 |
}
|
|
85 |
}
|
|
86 |
return r;
|
|
87 |
}
|
|
88 |
|
|
89 |
TInt DArmPlatChunk::SetAttributes(SChunkCreateInfo& aInfo)
|
|
90 |
{
|
|
91 |
switch(iChunkType)
|
|
92 |
{
|
|
93 |
case EKernelData:
|
|
94 |
iAttributes = EAddressFixed|EMapTypeGlobal|EPrivate;
|
|
95 |
break;
|
|
96 |
case ERamDrive:
|
|
97 |
iAttributes = EAddressFixed|EMapTypeGlobal|EPrivate;
|
|
98 |
break;
|
|
99 |
case EKernelStack:
|
|
100 |
iAttributes = EAddressKernel|EMapTypeGlobal|EPrivate;
|
|
101 |
break;
|
|
102 |
case EKernelCode:
|
|
103 |
iAttributes = EAddressKernel|EMapTypeGlobal|EPrivate|ECode;
|
|
104 |
break;
|
|
105 |
case EDll:
|
|
106 |
case EUserCode:
|
|
107 |
if (aInfo.iGlobal)
|
|
108 |
iAttributes = EAddressUserGlobal|EMapTypeGlobal|ECode;
|
|
109 |
else
|
|
110 |
iAttributes = EAddressFixed|EMapTypeLocal|EPrivate|ECode;
|
|
111 |
break;
|
|
112 |
case EUserData:
|
|
113 |
if (aInfo.iGlobal)
|
|
114 |
iAttributes = EAddressShared|EMapTypeShared;
|
|
115 |
else
|
|
116 |
iAttributes = EAddressLocal|EMapTypeLocal|EPrivate;
|
|
117 |
break;
|
|
118 |
case EDllData:
|
|
119 |
iAttributes = EAddressFixed|EMapTypeLocal|EPrivate;
|
|
120 |
break;
|
|
121 |
case EUserSelfModCode:
|
|
122 |
if (aInfo.iGlobal)
|
|
123 |
iAttributes = EAddressShared|EMapTypeShared|ECode;
|
|
124 |
else
|
|
125 |
iAttributes = EAddressLocal|EMapTypeLocal|EPrivate|ECode;
|
|
126 |
break;
|
|
127 |
case ESharedKernelSingle:
|
|
128 |
case ESharedKernelMultiple:
|
|
129 |
case ESharedIo:
|
|
130 |
iAttributes = EAddressShared|EMapTypeShared;
|
|
131 |
break;
|
|
132 |
case ESharedKernelMirror:
|
|
133 |
iAttributes = EAddressKernel|EMapTypeGlobal|EPrivate;
|
|
134 |
break;
|
|
135 |
case EKernelMessage:
|
|
136 |
iAttributes = EAddressKernel|EMapTypeGlobal|EPrivate;
|
|
137 |
break;
|
|
138 |
default:
|
|
139 |
FAULT();
|
|
140 |
}
|
|
141 |
return KErrNone;
|
|
142 |
}
|
|
143 |
|
|
144 |
/********************************************
|
|
145 |
* Chunk
|
|
146 |
********************************************/
|
|
147 |
|
|
148 |
DArmPlatChunk::DArmPlatChunk()
|
|
149 |
{}
|
|
150 |
|
|
151 |
DArmPlatChunk::~DArmPlatChunk()
|
|
152 |
{
|
|
153 |
DMemModelChunk::Destruct();
|
|
154 |
}
|
|
155 |
|
|
156 |
TInt DArmPlatChunk::SetupPermissions()
|
|
157 |
{
|
|
158 |
Mmu& m=Mmu::Get();
|
|
159 |
if(iChunkType==ESharedKernelSingle || iChunkType==ESharedKernelMultiple || iChunkType==ESharedIo || iChunkType==ESharedKernelMirror)
|
|
160 |
{
|
|
161 |
// override map attributes for shared kernel chunks
|
|
162 |
TUint ma = (iMapAttr &~ EMapAttrAccessMask) | (iChunkType==ESharedKernelMirror?EMapAttrSupRw:EMapAttrUserRw);
|
|
163 |
TInt r = m.PdePtePermissions(ma, iPdePermissions, iPtePermissions);
|
|
164 |
if (r != KErrNone)
|
|
165 |
return r;
|
|
166 |
iMapAttr = ma;
|
|
167 |
}
|
|
168 |
else
|
|
169 |
{
|
|
170 |
iPtePermissions=m.PtePermissions(iChunkType);
|
|
171 |
iPdePermissions=m.PdePermissions(iChunkType,EFalse);
|
|
172 |
}
|
|
173 |
|
|
174 |
__KTRACE_OPT(KMMU,Kern::Printf("Chunk permissions PTE=%08x PDE=%08x",iPtePermissions,iPdePermissions));
|
|
175 |
return KErrNone;
|
|
176 |
}
|
|
177 |
|
|
178 |
TIpcExcTrap::TExcLocation TIpcExcTrap::ExcLocation(DThread* aThread, TAny* aContext)
|
|
179 |
{
|
|
180 |
TArmExcInfo& info=*(TArmExcInfo*)aContext;
|
|
181 |
if (info.iExcCode==EArmExceptionDataAbort)
|
|
182 |
{
|
|
183 |
TLinAddr va=(TLinAddr)info.iFaultAddress;
|
|
184 |
|
|
185 |
TLinAddr aliasAddr = ((DMemModelThread*)aThread)->iAliasLinAddr;
|
|
186 |
TBool remoteError;
|
|
187 |
if(aliasAddr)
|
|
188 |
remoteError = TUint(va^aliasAddr)<TUint(KPageSize);
|
|
189 |
else
|
|
190 |
// The second clause in the statement below was "va < iRemoteBase + iSize".
|
|
191 |
// iRemoteBase + iSize might conceivably wrap round.
|
|
192 |
// The usual fix for this is to change
|
|
193 |
// va >= base && va < base + size
|
|
194 |
// to va >= base && (va - base) < size
|
|
195 |
// but this requires the first clause (va >= base) so that va-base doesn't wrap negative.
|
|
196 |
// Since the first clause in this expression is va >= (iRemoteBase & ~3)
|
|
197 |
// we have to re-write the expression as follows:
|
|
198 |
// Let base' = iRemoteBase & ~3
|
|
199 |
// so base = base' + (base & 3)
|
|
200 |
// then we have va >= base' && va < base' + (base & 3) + iSize
|
|
201 |
// (effectively the & ~3 on the first clause extends the range downwards by base & 3)
|
|
202 |
remoteError = va>=(iRemoteBase&~3) &&
|
|
203 |
(va - (iRemoteBase & ~3)) < iSize + (iRemoteBase & 3);
|
|
204 |
if (remoteError)
|
|
205 |
return EExcRemote;
|
|
206 |
|
|
207 |
// Third clause was va < iLocalBase + iSize, fixed as in the "remoteError =" line above
|
|
208 |
if (iLocalBase && va>=(iLocalBase&~3) &&
|
|
209 |
(va - (iLocalBase & ~3)) < iSize + (iLocalBase & 3))
|
|
210 |
return EExcLocal;
|
|
211 |
}
|
|
212 |
return EExcUnknown;
|
|
213 |
}
|