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1 // Copyright (c) 2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: This is the header file for the PCI driver test , so far implemented |
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14 // only on the Naviengine platform |
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15 |
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16 #ifndef __TPCI_TEST_H |
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17 #define __TPCI_TEST_H |
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18 |
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19 #ifndef __KERNEL_MODE__ |
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20 #define __E32TEST_EXTENSION__ |
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21 #include <e32test.h> |
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22 #include <e32def_private.h> |
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23 #endif // __KERNEL_MODE__ |
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24 |
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25 _LIT(KPciLdd, "d_pci.ldd"); |
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26 _LIT(KPciLddFactory, "PCI_test_factory"); |
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27 _LIT(KPciTest, "PCI Test LDD"); |
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28 |
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29 /** |
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30 Test driver op-codes |
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31 */ |
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32 enum TPciTestCmd |
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33 { |
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34 EGetTestInfo, |
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35 EAccessConfigSpace, |
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36 EAccessMemorySpace, |
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37 EOpenPciDChunk, |
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38 EOpenPciPlatHwChunk, |
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39 EOpenPciMappedChunk, |
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40 EOpenPciWindowChunk, |
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41 ERunUnitTests |
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42 }; |
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43 |
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44 /** |
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45 Identifies a PCI Function (device) on the system |
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46 */ |
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47 struct TPciDevice |
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48 { |
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49 TPciDevice() |
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50 :iVendorId(0xFFFFFFFF), iDeviceId(0xFFFFFFFF), iInstance(0) {} |
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51 |
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52 TPciDevice(TUint aVendorId, TUint aDeviceId, TInt aInstance=0) |
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53 :iVendorId(aVendorId), iDeviceId(aDeviceId), iInstance(aInstance) {} |
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54 |
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55 TUint iVendorId; |
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56 TUint iDeviceId; |
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57 TInt iInstance; ///< Unit to open (there could be multiple devices on system) |
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58 }; |
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59 |
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60 /** |
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61 Used to send chunk size and recieve |
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62 PCI address |
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63 */ |
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64 struct TPciChunkCreateInfo |
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65 { |
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66 TPciChunkCreateInfo() |
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67 :iSize(0), iPciAddress(NULL) |
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68 { |
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69 } |
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70 |
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71 TPciChunkCreateInfo(TInt aSize, TUint& aPciAddress, TRequestStatus* aStatus=NULL) |
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72 :iSize(aSize), iPciAddress(&aPciAddress), iStatus(aStatus) |
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73 { |
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74 } |
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75 TInt iSize; |
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76 TUint* iPciAddress; |
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77 TRequestStatus* iStatus; |
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78 }; |
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79 |
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80 /** |
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81 Information about the PSL required by the |
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82 user side test |
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83 */ |
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84 struct TPciTestInfo |
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85 { |
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86 TPciDevice iDevice; ///< Probe for this |
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87 |
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88 /** |
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89 Supplies the necessary information to test Read, Write, and |
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90 Modify for a word of PCI memory or configuration space |
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91 */ |
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92 struct TAddrSpaceTest |
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93 { |
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94 TAddrSpaceTest() |
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95 :iOffset(0), iExpectedValue(0), iReadOnlyMask(0) |
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96 {} |
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97 |
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98 TAddrSpaceTest(TUint aOffset, TUint aExpectedValue, TUint aReadOnlyMask) |
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99 :iOffset(aOffset), iExpectedValue(aExpectedValue), iReadOnlyMask(aReadOnlyMask) |
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100 {} |
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101 |
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102 /** |
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103 Returns a specified sub byte, or word from the whole dword |
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104 */ |
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105 inline TUint Expected(TInt aBitWidth, TInt aExtraOffset) const |
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106 { |
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107 //the right shift required to get field to bit 0 |
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108 const TInt shift = 8 *((aExtraOffset + iOffset) % 4); |
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109 |
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110 const TUint mask = 0xFFFFFFFF >> (32-aBitWidth); |
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111 return (iExpectedValue >> shift) & mask; |
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112 } |
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113 |
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114 const TUint iOffset; |
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115 const TUint iExpectedValue; ///< The initial value of word |
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116 const TUint iReadOnlyMask; ///< Mask of unwritable bits |
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117 //Future work, memory spaces should state a bar index |
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118 }; |
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119 |
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120 |
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121 TAddrSpaceTest iCfgSpaceRead; |
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122 TAddrSpaceTest iCfgSpaceWrite; |
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123 |
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124 TUint iMemSpaceIndex; ///< Memory space to select |
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125 TAddrSpaceTest iMemSpaceRead; |
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126 TAddrSpaceTest iMemSpaceWrite; |
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127 |
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128 TInt iNumberOfBars; ///< Number of simultaneous mappings into PCI space |
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129 }; |
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130 |
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131 class RPci; |
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132 class TAddrSpace; |
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133 /** |
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134 This class encapsulates all the various read/write/and modify commands |
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135 that can be carried out on a PCI memory space. The command is stored user |
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136 side, and then executed on kernel side when KRun() is called. |
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137 */ |
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138 class TUserPciSpace |
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139 { |
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140 public: |
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141 TUserPciSpace() |
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142 :iPci(NULL), iOperation(EInvalid), iBitWidth(0), iOffset(0), |
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143 iWriteValue(0), iClearMask(0), iSetMask(0) |
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144 {} |
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145 TUserPciSpace(RPci& aPci); |
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146 |
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147 /** |
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148 Perform the encapsulated read/write/or modify |
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149 @note Only run on kernel side |
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150 */ |
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151 TUint KRun(TAddrSpace& aAddrSpace); |
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152 |
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153 /** |
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154 Clone method is required so that multiple threads may |
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155 have their own copy of a TUserPciSpace (without knowing |
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156 its runtime type) |
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157 */ |
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158 virtual TUserPciSpace* Clone() const = 0; |
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159 |
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160 TUint Read(TInt aBitWidth, TUint aOffset) |
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161 { |
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162 iOffset = aOffset; |
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163 iOperation = ERead; |
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164 iBitWidth = aBitWidth; |
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165 |
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166 return Call(); |
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167 } |
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168 |
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169 void Write(TInt aBitWidth, TUint aOffset, TUint aValue) |
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170 { |
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171 iOffset = aOffset; |
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172 iOperation = EWrite; |
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173 iBitWidth = aBitWidth; |
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174 |
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175 iWriteValue = aValue; |
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176 Call(); |
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177 } |
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178 |
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179 void Modify(TInt aBitWidth, TUint aOffset, TUint aClearMask, TUint aSetMask) |
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180 { |
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181 iOffset = aOffset; |
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182 iOperation = EModify; |
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183 iBitWidth = aBitWidth; |
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184 |
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185 iClearMask = aClearMask; |
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186 iSetMask = aSetMask; |
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187 Call(); |
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188 } |
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189 |
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190 protected: |
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191 /** |
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192 Makes a request to iPci and passes a copy of this object to |
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193 the kernel side. |
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194 */ |
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195 virtual TUint Call() =0; |
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196 |
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197 enum TOperation {EInvalid, ERead, EWrite, EModify}; |
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198 |
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199 /** |
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200 Pointer to a PCI device handle |
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201 */ |
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202 RPci* iPci; |
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203 |
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204 TOperation iOperation; //!< Type of access to perform |
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205 TInt iBitWidth; |
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206 |
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207 TUint iOffset; |
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208 TUint32 iWriteValue; |
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209 TUint32 iClearMask; |
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210 TUint32 iSetMask; |
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211 }; |
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212 |
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213 /** |
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214 Grants access to a PCI device's (identified |
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215 by aPci) config space from user side |
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216 */ |
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217 class TUserConfigSpace : public TUserPciSpace |
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218 { |
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219 public: |
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220 TUserConfigSpace() |
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221 :TUserPciSpace() |
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222 {} |
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223 TUserConfigSpace(RPci& aPci); |
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224 |
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225 virtual TUserPciSpace* Clone() const; |
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226 private: |
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227 TUint Call(); |
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228 }; |
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229 |
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230 /** |
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231 Grants access to some region of a PCI |
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232 device's memory space. A PCI device(or function) |
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233 may have up to 8 distinct memory spaces |
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234 */ |
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235 class TUserMemorySpace : public TUserPciSpace |
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236 { |
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237 public: |
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238 TUserMemorySpace() |
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239 :TUserPciSpace(), iBarIndex(-1) |
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240 {} |
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241 |
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242 TUserMemorySpace(RPci& aPci, TInt aBarIndex); |
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243 |
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244 virtual TUserPciSpace* Clone() const; |
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245 |
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246 inline TInt BarIndex() {return iBarIndex;} |
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247 |
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248 private: |
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249 TUint Call(); |
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250 |
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251 TInt iBarIndex; ///< Each PCI function may have up to 8 memory spaces |
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252 }; |
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253 |
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254 #endif //__TPCI_TEST_H |