91 inline TCounter TIMER() |
91 inline TCounter TIMER() |
92 { return *(volatile TUint*)(KHwCounterTimer1+KHoTimerValue)&0xffff;} |
92 { return *(volatile TUint*)(KHwCounterTimer1+KHoTimerValue)&0xffff;} |
93 #endif |
93 #endif |
94 #ifdef __NE1_TB__ |
94 #ifdef __NE1_TB__ |
95 inline TCounter TIMER() |
95 inline TCounter TIMER() |
96 { return NETimer::Timer(5).iTimerCount; } |
96 { return NETimer::Timer(2).iTimerCount; } |
97 #endif |
97 #endif |
98 #ifdef __MRAP__ |
98 #ifdef __MRAP__ |
99 inline TCounter TIMER() |
99 inline TCounter TIMER() |
100 { TRap::SetRegister32(1, KRapRegRTC001_TRIGGER); |
100 { TRap::SetRegister32(1, KRapRegRTC001_TRIGGER); |
101 return TRap::Register32(KRapRegRTC001_LONGCOUNT); } |
101 return TRap::Register32(KRapRegRTC001_LONGCOUNT); } |
197 #endif |
197 #endif |
198 #if defined(__MAWD__) || defined(__MEIG__) |
198 #if defined(__MAWD__) || defined(__MEIG__) |
199 return aTicks*500; // 2kHz tick |
199 return aTicks*500; // 2kHz tick |
200 #endif |
200 #endif |
201 #if defined(__NE1_TB__) |
201 #if defined(__NE1_TB__) |
202 NETimer& T5 = NETimer::Timer(5); |
202 NETimer& T2 = NETimer::Timer(2); |
203 TUint prescale = __e32_find_ms1_32(T5.iPrescaler & 0x3f); |
203 TUint prescale = __e32_find_ms1_32(T2.iPrescaler & 0x3f); |
204 TInt f = 66666667 >> prescale; |
204 TInt f = 66666667 >> prescale; |
205 TInt64 x = I64LIT(1000000); |
205 TInt64 x = I64LIT(1000000); |
206 x *= TInt64(aTicks); |
206 x *= TInt64(aTicks); |
207 x += TInt64(f>>1); |
207 x += TInt64(f>>1); |
208 x /= TInt64(f); |
208 x /= TInt64(f); |
282 TRvEmuBoard::SetTimerMode(KHwCounterTimer1, TRvEmuBoard::ETimerModeFreeRunning); |
282 TRvEmuBoard::SetTimerMode(KHwCounterTimer1, TRvEmuBoard::ETimerModeFreeRunning); |
283 TRvEmuBoard::SetTimerPreScale(KHwCounterTimer1, TRvEmuBoard::ETimerPreScaleDiv256);// 3.90625kHz wrap 16.777s |
283 TRvEmuBoard::SetTimerPreScale(KHwCounterTimer1, TRvEmuBoard::ETimerPreScaleDiv256);// 3.90625kHz wrap 16.777s |
284 TRvEmuBoard::EnableTimer(KHwCounterTimer1, TRvEmuBoard::EEnable); |
284 TRvEmuBoard::EnableTimer(KHwCounterTimer1, TRvEmuBoard::EEnable); |
285 #endif |
285 #endif |
286 #if defined(__NE1_TB__) |
286 #if defined(__NE1_TB__) |
287 // set up timer 5 |
287 // nothing to do since variant has already set up timer |
288 NETimer& T5 = NETimer::Timer(5); |
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289 |
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290 T5.iTimerCtrl = 0; // stop and reset timer 5 |
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291 T5.iGTICtrl = 0; // disable timer 5 capture modes |
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292 __e32_io_completion_barrier(); |
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293 T5.iPrescaler = KNETimerPrescaleBy32; // Timer 5 prescaled by 32 (=2.0833MHz) |
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294 __e32_io_completion_barrier(); |
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295 T5.iGTInterruptEnable = 0; |
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296 __e32_io_completion_barrier(); |
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297 T5.iGTInterrupt = KNETimerGTIInt_All; |
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298 __e32_io_completion_barrier(); |
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299 T5.iTimerCtrl = KNETimerCtrl_CE; // deassert reset for timer 5, count still stopped |
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300 __e32_io_completion_barrier(); |
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301 T5.iTimerReset = 0xffffffffu; // timer 5 wraps after 2^32 counts |
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302 __e32_io_completion_barrier(); |
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303 T5.iTimerCtrl = KNETimerCtrl_CE | KNETimerCtrl_CAE; // start timer 5 |
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304 __e32_io_completion_barrier(); |
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305 #endif |
288 #endif |
306 #if defined(__EPOC32__) && defined(__CPU_X86) |
289 #if defined(__EPOC32__) && defined(__CPU_X86) |
307 // Set up timer channel 2 as free running counter at 14318180/12 Hz |
290 // Set up timer channel 2 as free running counter at 14318180/12 Hz |
308 SetUpTimerChannel2(); |
291 SetUpTimerChannel2(); |
309 #endif |
292 #endif |