321 |
321 |
322 #else |
322 #else |
323 #define FLUSH_ICACHE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c5, 0 "); /**< @internalTechnology */ |
323 #define FLUSH_ICACHE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c5, 0 "); /**< @internalTechnology */ |
324 #endif // else !(__CPU_ARM1136_ERRATUM_411920_FIXED) && (__CPU_ARM1136__ || __CPU_ARM1176__) |
324 #endif // else !(__CPU_ARM1136_ERRATUM_411920_FIXED) && (__CPU_ARM1136__ || __CPU_ARM1176__) |
325 #if defined(__CPU_ARM1136_ERRATUM_371025_FIXED) || !defined(__CPU_ARM1136__) |
325 #if defined(__CPU_ARM1136_ERRATUM_371025_FIXED) || !defined(__CPU_ARM1136__) |
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326 |
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327 #if !defined(__CPU_ARM1176_ERRATUM_720013_FIXED) && defined(__CPU_ARM1176__) |
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328 #define FLUSH_ICACHE_LINE(cc,r,tmp) asm("mcr"#cc" p15, 0, "#r", c7, c5, 1 "); \ |
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329 asm("mcr"#cc" p15, 0, "#r", c7, c5, 1 "); /**< @internalTechnology */ |
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330 #else |
326 #define FLUSH_ICACHE_LINE(cc,r,tmp) asm("mcr"#cc" p15, 0, "#r", c7, c5, 1 "); /**< @internalTechnology */ |
331 #define FLUSH_ICACHE_LINE(cc,r,tmp) asm("mcr"#cc" p15, 0, "#r", c7, c5, 1 "); /**< @internalTechnology */ |
327 #else // workaround for erratum 371025... |
332 #endif // !defined(__CPU_ARM1176_ERRATUM_720013_FIXED) && defined(__CPU_ARM1176__) |
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333 |
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334 #else // workaround for erratum 371025 of 1136... |
328 /** @internalTechnology */ |
335 /** @internalTechnology */ |
329 #define FLUSH_ICACHE_LINE(cc,r,tmp) asm("orr"#cc" "#tmp", "#r", #0xC0000000 "); \ |
336 #define FLUSH_ICACHE_LINE(cc,r,tmp) asm("orr"#cc" "#tmp", "#r", #0xC0000000 "); \ |
330 asm("bic"#cc" "#tmp", "#tmp", #1 "); \ |
337 asm("bic"#cc" "#tmp", "#tmp", #1 "); \ |
331 asm("mcr"#cc" p15, 0, "#tmp", c7, c5, 2 "); \ |
338 asm("mcr"#cc" p15, 0, "#tmp", c7, c5, 2 "); \ |
332 asm("sub"#cc" "#tmp", "#tmp", #0x40000000 "); \ |
339 asm("sub"#cc" "#tmp", "#tmp", #0x40000000 "); \ |
334 asm("sub"#cc" "#tmp", "#tmp", #0x40000000 "); \ |
341 asm("sub"#cc" "#tmp", "#tmp", #0x40000000 "); \ |
335 asm("mcr"#cc" p15, 0, "#tmp", c7, c5, 2 "); \ |
342 asm("mcr"#cc" p15, 0, "#tmp", c7, c5, 2 "); \ |
336 asm("sub"#cc" "#tmp", "#tmp", #0x40000000 "); \ |
343 asm("sub"#cc" "#tmp", "#tmp", #0x40000000 "); \ |
337 asm("mcr"#cc" p15, 0, "#tmp", c7, c5, 2 "); |
344 asm("mcr"#cc" p15, 0, "#tmp", c7, c5, 2 "); |
338 #endif //else (__CPU_ARM1136_ERRATUM_371025_FIXED) || !(__CPU_ARM1136__) |
345 #endif //else (__CPU_ARM1136_ERRATUM_371025_FIXED) || !(__CPU_ARM1136__) |
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346 |
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347 #if !defined(__CPU_ARM1176_ERRATUM_720013_FIXED) && defined(__CPU_ARM1176__) |
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348 // It is commented out to ensure it is not used on 1176 cores with 720013 erratum |
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349 // #define FLUSH_ICACHE_INDEX(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c5, 2 "); |
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350 #else |
339 #define FLUSH_ICACHE_INDEX(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c5, 2 "); /**< @internalTechnology */ |
351 #define FLUSH_ICACHE_INDEX(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c5, 2 "); /**< @internalTechnology */ |
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352 #endif //!defined(__CPU_ARM1176_ERRATUM_720013_FIXED) && defined(__CPU_ARM1176__) |
340 #define PURGE_DCACHE_LINE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c6, 1 "); /**< @internalTechnology */ |
353 #define PURGE_DCACHE_LINE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c6, 1 "); /**< @internalTechnology */ |
341 #define PURGE_DCACHE_INDEX(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c6, 2 "); /**< @internalTechnology */ |
354 #define PURGE_DCACHE_INDEX(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c6, 2 "); /**< @internalTechnology */ |
342 #define CLEAN_DCACHE_LINE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c10, 1 "); /**< @internalTechnology */ |
355 #define CLEAN_DCACHE_LINE(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c10, 1 "); /**< @internalTechnology */ |
343 |
356 |
344 #define CLEAN_DCACHE_INDEX(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c10, 2 "); /**< @internalTechnology */ |
357 #define CLEAN_DCACHE_INDEX(cc,r) asm("mcr"#cc" p15, 0, "#r", c7, c10, 2 "); /**< @internalTechnology */ |