40 #endif//else defined(__CPU_ARMV7) |
40 #endif//else defined(__CPU_ARMV7) |
41 |
41 |
42 const TInt KCacheInfoI=0; // InternalCache info for ICache. On ARMv7, this applies to the point-of-unification. |
42 const TInt KCacheInfoI=0; // InternalCache info for ICache. On ARMv7, this applies to the point-of-unification. |
43 const TInt KCacheInfoD=1; // InternalCache info for DCache. On ARMv7, this applies to the point-of-coherency. |
43 const TInt KCacheInfoD=1; // InternalCache info for DCache. On ARMv7, this applies to the point-of-coherency. |
44 const TInt KCacheInfoD_PoU=2; // InternalCache info for ARMv7 DCache for the point-of-unification. |
44 const TInt KCacheInfoD_PoU=2; // InternalCache info for ARMv7 DCache for the point-of-unification. |
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45 |
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46 #if !defined(__CPU_MEMORY_TYPE_REMAPPING) && defined(__CPU_ARM) |
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47 // These constants must be dthe same as DefaultPRRR & DefaultNMRR in bootcpu.inc |
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48 const TUint32 KDefaultPrimaryRegionRemapRegister = 0x000a00a4; |
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49 const TUint32 KDefaultNormalMemoryRemapRegister = 0x00400040; |
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50 #endif |
45 |
51 |
46 /* |
52 /* |
47 * Cache info of particular cache type or level. |
53 * Cache info of particular cache type or level. |
48 */ |
54 */ |
49 struct SCacheInfo |
55 struct SCacheInfo |
98 static TUint32 TypeRegister(); |
104 static TUint32 TypeRegister(); |
99 |
105 |
100 /* |
106 /* |
101 * @return Internal and external cache attributes (orred TMappingAttributes enums) |
107 * @return Internal and external cache attributes (orred TMappingAttributes enums) |
102 * that match aType memory type. |
108 * that match aType memory type. |
103 * @panic: If aType 4-7 is specified on platform with no __CPU_MEMORY_TYPE_REMAPPING. |
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104 */ |
109 */ |
105 static TUint32 TypeToCachingAttributes(TMemoryType aType); |
110 static TUint32 TypeToCachingAttributes(TMemoryType aType); |
106 |
111 |
107 #if defined(__CPU_ARMV7) |
112 #if defined(__CPU_ARMV7) |
108 |
113 |
321 * A primitive that parses the content of cache type MMU register. |
326 * A primitive that parses the content of cache type MMU register. |
322 */ |
327 */ |
323 static void ParseCacheSizeInfo(TUint32 aValue, SCacheInfo& aInfo); |
328 static void ParseCacheSizeInfo(TUint32 aValue, SCacheInfo& aInfo); |
324 #endif |
329 #endif |
325 |
330 |
326 #if defined(__CPU_MEMORY_TYPE_REMAPPING) |
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327 /* |
331 /* |
328 * @return The content of Primary Region Remap Register. |
332 * @return The content of Primary Region Remap Register. |
329 */ |
333 */ |
330 static TUint32 PrimaryRegionRemapRegister(); |
334 static TUint32 PrimaryRegionRemapRegister(); |
331 |
335 |
332 /* |
336 /* |
333 * @return The content of Normal Memory Remap Register. |
337 * @return The content of Normal Memory Remap Register. |
334 */ |
338 */ |
335 static TUint32 NormalMemoryRemapRegister(); |
339 static TUint32 NormalMemoryRemapRegister(); |
336 #endif // defined(__CPU_MEMORY_TYPE_REMAPPING) |
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337 |
340 |
338 #if defined(__CPU_ARMV7) |
341 #if defined(__CPU_ARMV7) |
339 static TInt DmaBufferAlignementLog2; // Holds the alignement requirement for DMA buffers. |
342 static TInt DmaBufferAlignementLog2; // Holds the alignement requirement for DMA buffers. |
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343 #endif |
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344 |
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345 #if !defined(__CPU_MEMORY_TYPE_REMAPPING) && defined(__CPU_ARM) |
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346 /** |
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347 * On platforms with no memory type remapping, we have to simulate TMemoryType values 4-7 |
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348 */ |
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349 static TUint32 iPrimaryRegionRemapRegister; |
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350 static TUint32 iNormalMemoryRemapRegister; |
340 #endif |
351 #endif |
341 }; |
352 }; |
342 |
353 |
343 #ifdef __HAS_EXTERNAL_CACHE__ |
354 #ifdef __HAS_EXTERNAL_CACHE__ |
344 //ARM External Cache register offsets |
355 //ARM External Cache register offsets |