equal
deleted
inserted
replaced
46 { |
46 { |
47 // Third phase MMU initialisation |
47 // Third phase MMU initialisation |
48 Mmu& m=Mmu::Get(); |
48 Mmu& m=Mmu::Get(); |
49 m.Init3(); |
49 m.Init3(); |
50 } |
50 } |
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51 |
|
52 void M::Init4() |
|
53 { |
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54 // Fourth phase MMU initialisation - Not required on this memory model. |
|
55 } |
51 |
56 |
52 TInt M::InitSvHeapChunk(DChunk* aChunk, TInt aSize) |
57 TInt M::InitSvHeapChunk(DChunk* aChunk, TInt aSize) |
53 { |
58 { |
54 TInt r; |
59 TInt r; |
55 TLinAddr base = TheRomHeader().iKernDataAddress; |
60 TLinAddr base = TheRomHeader().iKernDataAddress; |