79 asm(".word %a0" : : "i" ((TInt)&InternalCache::Info[KCacheInfoI])); |
79 asm(".word %a0" : : "i" ((TInt)&InternalCache::Info[KCacheInfoI])); |
80 } |
80 } |
81 |
81 |
82 __NAKED__ void InternalCache::IMB_CacheLine(TLinAddr /*aAddr*/) |
82 __NAKED__ void InternalCache::IMB_CacheLine(TLinAddr /*aAddr*/) |
83 { |
83 { |
84 asm("mov r1, #0 "); //will need zero reg for coprocessor instructions |
84 //--Determine base address of cache line--// |
85 //--Round the address down to the start of line--// |
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86 asm("ldr r2, __DCacheInfoPoU "); |
85 asm("ldr r2, __DCacheInfoPoU "); |
87 asm("ldrh r3, [r2, #%a0]" : : "i" _FOFF(SCacheInfo,iLineLength)); |
86 asm("ldrh r3, [r2, #%a0]" : : "i" _FOFF(SCacheInfo,iLineLength)); |
88 asm("sub ip, r3, #1 "); // ip=mask for offset within line |
87 asm("sub ip, r3, #1"); // ip=mask for offset within line |
89 asm("bic r0, r0, ip "); // r0 = cache line base |
88 asm("bic r2, r0, ip"); // r2 = cache line base |
90 |
89 |
91 DCCMVAU(r0); // Clean DCache line to Point-of-Unification |
90 DCCMVAU(r2); // Clean DCache line to Point-of-Unification |
92 ARM_DSBSY; |
91 ARM_DSBSY; // Data Sync Barrier (system) |
93 ICIMVAU(r0); |
92 ICIMVAU(r2); // Invalidate Instruction cache line to Point-of-Unification |
94 BPIMVA(r0); |
93 BPIMVA(r0); // Invalidate aAddr from Branch Predictor Array |
95 ARM_DSBSH; |
94 asm("add r0, r0, #2"); |
96 ARM_ISBSY; |
95 BPIMVA(r0); // Invalidate possible THUMB instuction at aAddr+2 from Branch Predictor Array |
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96 ARM_DSBSH; // Data Sync Barrier (system) |
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97 ARM_ISBSY; // Instruction Sync Barrier |
97 __JUMP(,lr); |
98 __JUMP(,lr); |
98 } |
99 } |
99 |
100 |
100 __NAKED__ void InternalCache::Invalidate_ICache_Region(TLinAddr /*aBase*/, TUint /*aSize*/) |
101 __NAKED__ void InternalCache::Invalidate_ICache_Region(TLinAddr /*aBase*/, TUint /*aSize*/) |
101 { |
102 { |