equal
deleted
inserted
replaced
126 { |
126 { |
127 r = DPlatChunkHw::New(iBufs[aIdx].iChunk, phys, aSize, EMapAttrSupRw | EMapAttrFullyBlocking); |
127 r = DPlatChunkHw::New(iBufs[aIdx].iChunk, phys, aSize, EMapAttrSupRw | EMapAttrFullyBlocking); |
128 if (r != KErrNone) |
128 if (r != KErrNone) |
129 Epoc::FreePhysicalRam(phys, aSize); |
129 Epoc::FreePhysicalRam(phys, aSize); |
130 iBufs[aIdx].iSize = aSize; |
130 iBufs[aIdx].iSize = aSize; |
|
131 |
|
132 __KTRACE_OPT(KDMA, Kern::Printf("TBufferMgr::Alloc buffer %d linAddr=0x%08x, physAddr=0x%08x, size=%d", |
|
133 aIdx, Addr(aIdx), PhysAddr(aIdx), Size(aIdx))); |
131 } |
134 } |
132 NKern::ThreadLeaveCS(); |
135 NKern::ThreadLeaveCS(); |
133 return r; |
136 return r; |
134 } |
137 } |
135 |
138 |
153 } |
156 } |
154 } |
157 } |
155 |
158 |
156 #endif |
159 #endif |
157 |
160 |
|
161 |
|
162 #ifndef DMA_APIV2 |
158 static TInt FragmentCount(DDmaRequest* aRequest) |
163 static TInt FragmentCount(DDmaRequest* aRequest) |
159 { |
164 { |
160 TInt count = 0; |
165 TInt count = 0; |
161 for (SDmaDesHdr* pH = aRequest->iFirstHdr; pH != NULL; pH = pH->iNext) |
166 for (SDmaDesHdr* pH = aRequest->iFirstHdr; pH != NULL; pH = pH->iNext) |
162 count++; |
167 count++; |
163 return count; |
168 return count; |
164 } |
169 } |
|
170 #endif |
|
171 |
165 |
172 |
166 ////////////////////////////////////////////////////////////////////////////// |
173 ////////////////////////////////////////////////////////////////////////////// |
167 |
174 |
168 class DDmaTestChannel : public DLogicalChannelBase |
175 class DDmaTestChannel : public DLogicalChannelBase |
169 { |
176 { |
319 TUint8* p = iBufMgr.Addr(i); |
326 TUint8* p = iBufMgr.Addr(i); |
320 TUint8* end = p + iBufMgr.Size(i); |
327 TUint8* end = p + iBufMgr.Size(i); |
321 while (p < end) |
328 while (p < end) |
322 if (*p++ != val) |
329 if (*p++ != val) |
323 { |
330 { |
324 __KTRACE_OPT(KDMA, Kern::Printf("Check DMA buffer failed offset: %d value: %d", |
331 #ifdef _DEBUG |
325 p-iBufMgr.Addr(i)-1, *(p-1))); |
332 const TUint8 prevValue = *(p-1); |
|
333 #endif |
|
334 __KTRACE_OPT(KDMA, Kern::Printf("Check DMA buffer number %d failed at offset: %d value: %d(%c)", |
|
335 i, p-iBufMgr.Addr(i)-1, prevValue, prevValue)); |
326 return EFalse; |
336 return EFalse; |
327 } |
337 } |
328 return ETrue; |
338 return ETrue; |
329 } |
339 } |
330 case RTestDma::EFragment: |
340 case RTestDma::EFragment: |
359 return iChannel->FailNext((TInt)a1); |
369 return iChannel->FailNext((TInt)a1); |
360 case RTestDma::EFragmentCount: |
370 case RTestDma::EFragmentCount: |
361 { |
371 { |
362 TInt reqIdx = (TInt)a1; |
372 TInt reqIdx = (TInt)a1; |
363 __ASSERT_DEBUG(0 <= reqIdx && reqIdx < KMaxRequests, Kern::PanicCurrentThread(KClientPanicCat, __LINE__)); |
373 __ASSERT_DEBUG(0 <= reqIdx && reqIdx < KMaxRequests, Kern::PanicCurrentThread(KClientPanicCat, __LINE__)); |
|
374 #ifdef DMA_APIV2 |
|
375 return iRequests[reqIdx]->FragmentCount(); |
|
376 #else |
364 return FragmentCount(iRequests[reqIdx]); |
377 return FragmentCount(iRequests[reqIdx]); |
|
378 #endif |
365 } |
379 } |
366 case RTestDma::EMissInterrupts: |
380 case RTestDma::EMissInterrupts: |
367 return iChannel->MissNextInterrupts((TInt)a1); |
381 return iChannel->MissNextInterrupts((TInt)a1); |
368 default: |
382 default: |
369 Kern::PanicCurrentThread(KClientPanicCat, __LINE__); |
383 Kern::PanicCurrentThread(KClientPanicCat, __LINE__); |
374 |
388 |
375 TInt DDmaTestChannel::Execute(const TDesC8& aDes) |
389 TInt DDmaTestChannel::Execute(const TDesC8& aDes) |
376 { |
390 { |
377 TBuf8<64> cmd; |
391 TBuf8<64> cmd; |
378 Kern::KUDesGet(cmd, aDes); |
392 Kern::KUDesGet(cmd, aDes); |
|
393 __KTRACE_OPT(KDMA, Kern::Printf("DDmaTestChannel::Execute cmd=%S", &cmd)); |
|
394 |
379 const TText8* p = cmd.Ptr(); |
395 const TText8* p = cmd.Ptr(); |
380 const TText8* pEnd = p + cmd.Length(); |
396 const TText8* pEnd = p + cmd.Length(); |
381 while (p<pEnd) |
397 while (p<pEnd) |
382 { |
398 { |
383 TText8 opcode = *p++; |
399 TText8 opcode = *p++; |