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157 } |
157 } |
158 |
158 |
159 #endif |
159 #endif |
160 |
160 |
161 |
161 |
162 #ifndef DMA_APIV2 |
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163 static TInt FragmentCount(DDmaRequest* aRequest) |
162 static TInt FragmentCount(DDmaRequest* aRequest) |
164 { |
163 { |
165 TInt count = 0; |
164 TInt count = 0; |
166 for (SDmaDesHdr* pH = aRequest->iFirstHdr; pH != NULL; pH = pH->iNext) |
165 for (SDmaDesHdr* pH = aRequest->iFirstHdr; pH != NULL; pH = pH->iNext) |
167 count++; |
166 count++; |
168 return count; |
167 return count; |
169 } |
168 } |
170 #endif |
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171 |
169 |
172 |
170 |
173 ////////////////////////////////////////////////////////////////////////////// |
171 ////////////////////////////////////////////////////////////////////////////// |
174 |
172 |
175 class DDmaTestChannel : public DLogicalChannelBase |
173 class DDmaTestChannel : public DLogicalChannelBase |
388 return iChannel->FailNext((TInt)a1); |
386 return iChannel->FailNext((TInt)a1); |
389 case RTestDma::EFragmentCount: |
387 case RTestDma::EFragmentCount: |
390 { |
388 { |
391 TInt reqIdx = (TInt)a1; |
389 TInt reqIdx = (TInt)a1; |
392 __ASSERT_DEBUG(0 <= reqIdx && reqIdx < KMaxRequests, Kern::PanicCurrentThread(KClientPanicCat, __LINE__)); |
390 __ASSERT_DEBUG(0 <= reqIdx && reqIdx < KMaxRequests, Kern::PanicCurrentThread(KClientPanicCat, __LINE__)); |
393 #ifdef DMA_APIV2 |
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394 return iRequests[reqIdx]->FragmentCount(); |
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395 #else |
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396 return FragmentCount(iRequests[reqIdx]); |
391 return FragmentCount(iRequests[reqIdx]); |
397 #endif |
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398 } |
392 } |
399 case RTestDma::EMissInterrupts: |
393 case RTestDma::EMissInterrupts: |
400 return iChannel->MissNextInterrupts((TInt)a1); |
394 return iChannel->MissNextInterrupts((TInt)a1); |
401 default: |
395 default: |
402 Kern::PanicCurrentThread(KClientPanicCat, __LINE__); |
396 Kern::PanicCurrentThread(KClientPanicCat, __LINE__); |