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1 // Copyright (c) 2007-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // e32\drivers\trace\arm\btracex_impl.cia |
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15 // |
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16 // |
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17 |
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18 // adjust a0 for timestamp(s) |
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19 #ifdef BTRACE_INCLUDE_TIMESTAMPS |
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20 #ifdef USE_TIMESTAMP2 |
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21 asm("add r0, r0, #8 "); |
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22 asm("orr r0, r0, #%a0" : : "i" ((TInt)((BTrace::ETimestampPresent | BTrace::ETimestamp2Present)<<BTrace::EFlagsIndex*8))); |
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23 #else |
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24 asm("add r0, r0, #4 "); |
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25 asm("orr r0, r0, #%a0" : : "i" ((TInt)(BTrace::ETimestampPresent<<BTrace::EFlagsIndex*8))); |
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26 #endif |
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27 #endif |
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28 #ifdef __SMP__ |
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29 // add in CPU ID field to Header2 |
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30 asm("tst r0, #%a0" : : "i" ((TInt)(BTrace::EHeader2Present<<BTrace::EFlagsIndex*8))); |
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31 asm("movne r12, r1, lsl #12 "); // if Header2 already present, r12=Header2<<12 |
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32 asm("mrc p15, 0, r1, c0, c0, 5 "); // r1 = CPU ID |
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33 asm("orr r0, r0, #%a0" : : "i" ((TInt)(BTrace::EHeader2Present<<BTrace::EFlagsIndex*8))); // Header2 is there |
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34 asm("addeq r0, r0, #%a0" : : "i" ((TInt)(4<<BTrace::ESizeIndex*8))); // if Header2 was not there, add 4 to size |
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35 asm("mov r1, r1, lsl #20 "); // CPU ID into top 12 bits of Header2 |
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36 asm("orrne r1, r1, r12, lsr #12 "); // if Header2 was already there, keep bottom 20 bits of it |
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37 asm("stmdb sp!,{r0-r12,lr} "); // save first 4 args, callee-save registers, CPSR and return address (14 words) |
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38 #else |
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39 asm("mrs r12, cpsr "); // r12 = save interrupt status |
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40 asm("stmdb sp!,{r0-r12,lr} "); // save first 4 args, callee-save registers, CPSR and return address (14 words) |
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41 INTS_OFF(r14, r12, INTS_ALL_OFF); // disable interrupts |
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42 #endif |
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43 asm("ldr r10, __Buffer "); // r10 = our buffer structure |
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44 asm("add r4, r0, #3 "); |
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45 asm("and r4, r4, #0xfc "); // r4 = size of trace record rounded up to whole word size |
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46 asm("ldmia r10, {r5-r7} "); // r5 = Buffer.iAddress |
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47 // r6 = Buffer.iStart |
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48 // r7 = Buffer.iEnd |
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49 asm("ldr r14, [r5, #%a0]" : : "i" _FOFF(TBTraceBuffer,iGeneration)); |
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50 asm("ldr r9, [r10, #%a0]" : : "i" _FOFF(TBTraceBufferK,iRequestDataSize)); |
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51 asm("ldr r12, [r10, #%a0]" : : "i" _FOFF(TBTraceBufferK,iRecordOffsets)); |
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52 asm("add r14, r14, #1 "); |
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53 asm("str r14, [r5, #%a0]" : : "i" _FOFF(TBTraceBuffer,iGeneration)); |
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54 #ifdef __SMP__ |
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55 __DATA_MEMORY_BARRIER_Z__(r8); |
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56 #endif |
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57 asm("ldr r2, [r5, #%a0]" : : "i" _FOFF(TBTraceBuffer,iTail)); |
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58 // r2 = original iTail (might have bit 0 set) |
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59 asm("ldr r14, [r5, #%a0]" : : "i" _FOFF(TBTraceBuffer,iMode)); |
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60 // r14 = iMode |
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61 |
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62 asm("8: "); |
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63 asm("ldr r8, [r10, #%a0]" : : "i" _FOFF(TBTraceBufferK,iHead)); |
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64 asm("bic r1, r2, #1 "); // r1 = tail (bit 0 cleared) |
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65 asm("add r3, r8, r4 "); // r3 = head+size = newHead (always multiple of 4) |
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66 |
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67 /* Registers: R0=spare, R1=tail, R2=orig_tail, R3=newHead, R4=size, R5=&user_buffer, R6=iStart, R7=iEnd |
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68 R8=head, R9=requestDataSize, R10=&Buffer, R11=unused, R12=iRecordOffsets, R14=iMode |
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69 */ |
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70 |
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71 asm("tst r14, #%a0" : : "i" ((TInt)RBTrace::EEnable)); |
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72 asm("beq trace_off "); // end now if tracing is disabled |
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73 |
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74 asm("cmp r3, r7 "); // cmp newHead,end |
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75 asm("bls 1f "); // 1f==no_wrap |
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76 asm("mov r9, #0 "); // iRequestDataSize=0 |
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77 asm("add r3, r6, r4 "); // newHead = start+size |
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78 asm("add r0, r3, #1 "); // r0 = newHead+1 |
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79 asm("cmp r8, r1 "); // cmp head,tail |
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80 asm("cmphs r1, r0 "); // cmp tail,newHead+1 |
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81 asm("strhs r8, [r5, #%a0]" : : "i" _FOFF(TBTraceBuffer,iWrap)); |
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82 asm("movhs r8, r6 "); // head = start |
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83 asm("bhs 3f "); // ... done (3f==update_offsets) |
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84 // new trace would be overwriting tail pointer... |
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85 asm("tst r14, #%a0" : : "i" ((TInt)RBTrace::EFreeRunning)); |
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86 asm("beq trace_dropped "); // if we aren't in freerunning mode, drop the trace |
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87 asm("ldrb r1, [r12, r3, lsr #2] ");// r1 = word offset to next record after newHead |
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88 asm("str r8, [r5, #%a0]" : : "i" _FOFF(TBTraceBuffer,iWrap)); |
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89 asm("mov r8, r6 "); // head = start |
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90 asm("add r1, r3, r1, lsl #2 "); // tail = newHead + offset to next record |
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91 asm("b 2f "); // 2f==overwrite |
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92 |
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93 asm("1: "); // no_wrap |
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94 asm("cmp r8, r1 "); // cmp head,tail |
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95 asm("bhs 3f "); // if >= then done (3f==update_offsets) |
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96 asm("cmp r1, r3 "); // cmp tail,newHead |
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97 asm("bhi 3f "); // if > the done (3f==update_offsets) |
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98 asm("ldr r0, [r5, #%a0]" : : "i" _FOFF(TBTraceBuffer,iWrap)); // r0 = wrap |
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99 asm("tst r14, #%a0" : : "i" ((TInt)RBTrace::EFreeRunning)); |
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100 asm("beq trace_dropped "); // if we aren't in freerunning mode, drop the trace |
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101 asm("cmp r3, r7 "); // cmp newHead,end |
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102 asm("cmplo r3, r0 "); // cmp newHead,wrap |
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103 asm("ldrlob r1, [r12, r3, lsr #2] ");// r1 = word offset to next record after newHead |
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104 asm("mov r9, #0 "); // iRequestDataSize=0 |
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105 asm("addlo r1, r3, r1, lsl #2 "); // tail = newHead + offset to next record |
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106 asm("cmplo r1, r7 "); // cmp tail,end |
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107 asm("cmplo r1, r0 "); // cmp tail,wrap |
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108 asm("movhs r1, r6 "); // tail = start |
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109 |
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110 asm("2: "); // overwrite |
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111 asm("ldr r0, [r5, r1] "); // r1 = first word of record at new tail |
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112 #ifndef __SMP__ |
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113 // On single processor iTail can't have been updated since interrupts are off here |
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114 asm("orr r1, r1, #1 "); |
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115 asm("str r1, [r5, #%a0]" : : "i" _FOFF(TBTraceBuffer,iTail)); // update tail |
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116 asm("bic r1, r1, #1 "); |
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117 #endif |
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118 asm("orr r0, r0, #%a0" : : "i" ((TInt)(BTrace::EMissingRecord<<(BTrace::EFlagsIndex*8)))); |
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119 asm("str r0, [r5, r1] "); // set 'missing record' flag in next record to be read |
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120 #ifdef __SMP__ |
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121 // attempt to atomically update iTail |
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122 asm("9: "); |
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123 asm("add r5, r5, #%a0" : : "i" _FOFF(TBTraceBuffer,iTail)); // r5=&user_buffer.iTail |
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124 asm("orr r1, r1, #1 "); |
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125 LDREX(0,5); |
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126 asm("cmp r0, r2 "); // iTail = orig_tail ? |
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127 asm("movne r2, r0 "); // if not, orig_tail = iTail |
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128 asm("bne 8b "); // and go round again |
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129 STREX(0,1,5); // else try to update iTail with tail|1 |
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130 asm("cmp r0, #0 "); |
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131 asm("bne 9b "); |
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132 __DATA_MEMORY_BARRIER__(r0); // ensure update to iTail observed before overwrites |
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133 asm("sub r5, r5, #%a0" : : "i" _FOFF(TBTraceBuffer,iTail)); // r5=&user_buffer.iTail |
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134 #endif |
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135 |
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136 asm("3: "); // update_offsets |
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137 asm("sub r9, r9, r4 "); // iRequestDataSize -= size |
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138 asm("str r3, [r10, #%a0]" : : "i" _FOFF(TBTraceBufferK,iHead)); // OK to do this here since only used kernel side |
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139 asm("str r9, [r10, #%a0]" : : "i" _FOFF(TBTraceBufferK,iRequestDataSize)); |
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140 |
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141 asm("add r5, r5, r8 "); // r5 = address+head = destination to store trace |
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142 asm("mov r4, r4, asr #2 "); // r4 = size/4 = number of words in trace record |
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143 asm("add r11, r12, r8, asr #2 "); // r11 = address to store record sizes |
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144 // unused regs are now r0 r1 r2 r3 r6 r7 r8 r9 r12 r14 |
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145 |
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146 asm("ldr r14, [r10,#%a0]" : : "i" _FOFF(TBTraceBufferK,iDropped)); |
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147 asm("ldmia sp, {r6-r9} "); // r6 = aHeader, r7 = aHeader2, r8 = aContext, r9 = a1 |
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148 asm("cmp r14, #0 "); |
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149 asm("movne r14, #0 "); |
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150 asm("strne r14, [r10,#%a0]" : : "i" _FOFF(TBTraceBufferK,iDropped)); |
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151 asm("orrne r6, r6, #%a0" : : "i" ((TInt)(BTrace::EMissingRecord<<BTrace::EFlagsIndex*8))); |
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152 |
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153 asm("str r6, [r5], #4 "); // store aHeader |
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154 asm("strb r4, [r11], #1 "); |
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155 asm("sub r4, r4, #1 "); |
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156 |
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157 asm("tst r6, #%a0" : : "i" ((TInt)(BTrace::EHeader2Present<<BTrace::EFlagsIndex*8))); |
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158 asm("strne r7, [r5], #4 "); // store aHeader2 ? |
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159 asm("strneb r4, [r11], #1 "); |
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160 asm("subne r4, r4, #1 "); |
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161 |
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162 #ifdef BTRACE_INCLUDE_TIMESTAMPS |
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163 #ifdef __SMP__ |
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164 asm("bl Timestamp__5NKern "); |
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165 asm("str r0, [r5], #4 "); // store timestamp low word |
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166 #ifdef USE_TIMESTAMP2 |
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167 asm("str r1, [r5], #4 "); // store timestamp high word |
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168 #endif |
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169 #else // __SMP__ |
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170 #ifdef HAS_HIGH_RES_TIMER |
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171 GET_HIGH_RES_TICK_COUNT(r0); // r0 = timestamp |
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172 #else |
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173 asm("bl " CSM_ZN5NKern11FastCounterEv); |
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174 #endif |
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175 asm("str r0, [r5], #4 "); // store timestamp |
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176 asm("strb r4, [r11], #1 "); |
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177 asm("subs r4, r4, #1 "); |
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178 #ifdef USE_TIMESTAMP2 |
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179 asm("bl " CSM_ZN5NKern9TickCountEv ); |
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180 asm("str r0, [r5], #4 "); // store timestamp2 |
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181 asm("strb r4, [r11], #1 "); |
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182 asm("subs r4, r4, #1 "); |
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183 #endif |
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184 #endif // __SMP__ |
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185 #endif // BTRACE_INCLUDE_TIMESTAMPS |
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186 |
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187 asm("add r0, sp, #14*4 "); |
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188 asm("ldmia r0, {r0-r3} "); // r0 = a2, r1 = a3, r2 = aExtra, r3 = aPc |
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189 |
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190 asm("tst r6, #%a0" : : "i" ((TInt)(BTrace::EContextIdPresent<<BTrace::EFlagsIndex*8))); |
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191 asm("strne r8, [r5], #4 "); // store aContext ? |
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192 asm("strneb r4, [r11], #1 "); |
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193 asm("subne r4, r4, #1 "); |
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194 |
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195 asm("tst r6, #%a0" : : "i" ((TInt)(BTrace::EPcPresent<<BTrace::EFlagsIndex*8))); |
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196 asm("strne r3, [r5], #4 "); // store aPc ? |
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197 asm("strneb r4, [r11], #1 "); |
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198 asm("subne r4, r4, #1 "); |
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199 |
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200 asm("tst r6, #%a0" : : "i" ((TInt)(BTrace::EExtraPresent<<BTrace::EFlagsIndex*8))); |
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201 asm("strne r2, [r5], #4 "); // store aExtra ? |
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202 asm("strneb r4, [r11], #1 "); |
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203 asm("subne r4, r4, #1 "); |
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204 |
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205 asm("cmp r4, #0 "); // done? |
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206 asm("ble 6f "); // 6f==trace_stored |
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207 |
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208 asm("str r9, [r5], #4 "); // store a1 |
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209 asm("strb r4, [r11], #1 "); |
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210 asm("subs r4, r4, #1 "); |
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211 asm("ble 6f "); // 6f==trace_stored |
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212 |
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213 asm("str r0, [r5], #4 "); // store a2 |
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214 asm("strb r4, [r11], #1 "); |
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215 asm("subs r4, r4, #1 "); |
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216 asm("ble 6f "); // 6f==trace_stored |
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217 |
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218 asm("cmp r4, #1 "); |
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219 asm("streq r1, [r5], #4 "); // store a3 ? |
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220 asm("streqb r4, [r11], #1 "); |
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221 asm("beq 6f "); // 6f==trace_stored |
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222 |
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223 // r9 = pointer to rest of data to store... |
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224 asm("mov r9, r1 "); |
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225 |
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226 asm("cmp r4, #7 "); |
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227 asm("blo 5f "); // store_loop_last |
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228 |
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229 asm("ldr r14, __03020100 "); |
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230 asm("add r4, r4, r4, asl #8 "); |
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231 asm("add r4, r4, r4, asl #16 "); |
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232 asm("sub r4, r4, r14 "); |
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233 asm("ldr r8, __04040404 "); |
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234 |
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235 // align destination to 4 words... |
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236 asm("movs r14, r5, asl #28 "); |
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237 asm("beq 4f "); // 4f==block_copy_loop |
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238 asm("rsb r14, r14, #0 "); |
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239 asm("msr cpsr_f, r14 "); |
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240 |
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241 asm("ldmeqia r9!, {r0} "); |
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242 asm("streqb r4, [r11], #1 "); |
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243 asm("subeq r4, r4, r8, lsr #2 "); |
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244 asm("stmeqia r5!, {r0} "); |
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245 |
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246 asm("ldmmiia r9!, {r2,r3} "); |
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247 asm("strmih r4, [r11], #2 "); |
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248 asm("submi r4, r4, r8, lsr #1 "); |
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249 asm("stmmiia r5!, {r2,r3} "); |
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250 |
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251 asm("4: "); // block_copy_loop |
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252 asm("ldmia r9!, {r0-r3} "); |
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253 asm("stmia r5!, {r0-r3} "); |
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254 asm("str r4, [r11], #4 "); |
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255 asm("subs r4, r4, r8 "); |
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256 asm("cmphs r4, #0x01000000 "); |
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257 asm("bhs 4b "); // 4b==block_copy_loop |
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258 |
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259 asm("ands r4, r4, #3 "); |
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260 asm("beq 6f "); // 6f==trace_stored |
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261 |
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262 asm("5: "); // store_loop_last |
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263 asm("ldr r0, [r9], #4 "); // get next word for record |
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264 asm("strb r4, [r11], #1 "); // store size offset |
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265 asm("subs r4, r4, #1 "); |
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266 asm("str r0, [r5], #4 "); // store word of trace record |
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267 asm("bhi 5b "); // 5b==store_loop_last |
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268 |
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269 asm("6: "); // trace_stored |
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270 asm("ldr r5, [r10, #%a0]" : : "i" _FOFF(TBTraceBufferK,iAddress)); |
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271 asm("ldr r6, [r10, #%a0]" : : "i" _FOFF(TBTraceBufferK,iHead)); |
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272 #ifdef __SMP__ |
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273 __DATA_MEMORY_BARRIER_Z__(r8); // make sure all buffer writes observed before head pointer update |
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274 #endif |
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275 asm("ldr r4, [r10, #%a0]" : : "i" _FOFF(TBTraceBufferK,iWaitingDfc)); |
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276 asm("ldr r7, [r5, #%a0]" : : "i" _FOFF(TBTraceBuffer,iGeneration)); |
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277 asm("ldr r0, [r10, #%a0]" : : "i" _FOFF(TBTraceBufferK,iRequestDataSize)); |
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278 asm("str r6, [r5, #%a0]" : : "i" _FOFF(TBTraceBuffer,iHead)); // update user-visible head pointer |
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279 asm("add r7, r7, #1 "); |
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280 #ifdef __SMP__ |
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281 __DATA_MEMORY_BARRIER__(r8); // make sure head pointer update seen before generation update |
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282 #endif |
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283 asm("str r7, [r5, #%a0]" : : "i" _FOFF(TBTraceBuffer,iGeneration)); |
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284 asm("cmp r4, #0 "); |
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285 asm("beq done "); |
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286 asm("cmp r0, #0 "); |
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287 asm("bgt done "); |
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288 |
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289 // iWaitingDfc exists and iRequestDataSize<=0 so we need to trigger the DFC... |
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290 asm("mov r0, #0 "); |
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291 asm("str r0, [r10, #%a0]" : : "i" _FOFF(TBTraceBufferK,iWaitingDfc)); // iWaitingDfc=0 |
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292 |
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293 asm("mov r0, r4 "); |
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294 asm("bl " CSM_ZN4TDfc6RawAddEv); |
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295 asm("b done "); |
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296 |