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1 // Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // e32\include\memmodel\epoc\mmubase\mmubase.h |
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15 // |
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16 // WARNING: This file contains some APIs which are internal and are subject |
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17 // to change without notice. Such APIs should therefore not be used |
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18 // outside the Kernel and Hardware Services package. |
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19 // |
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20 |
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21 #ifndef __MMUBASE_H__ |
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22 #define __MMUBASE_H__ |
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23 #include <plat_priv.h> |
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24 #include <memmodel/epoc/mmubase/kblockmap.h> |
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25 |
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26 |
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27 /****************************************************************************** |
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28 * Definitions common to all MMU memory models |
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29 ******************************************************************************/ |
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30 |
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31 /** |
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32 @internalComponent |
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33 */ |
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34 struct SPageInfo |
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35 { |
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36 enum TType |
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37 { |
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38 EInvalid=0, // No physical RAM exists for this page |
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39 EFixed=1, // RAM fixed at boot time, |
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40 EUnused=2, // Page is unused |
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41 EChunk=3, // iOwner=DChunk* iOffset=index into chunk |
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42 ECodeSegMemory=4, // iOwner=DCodeSegMemory* iOffset=index into CodeSeg memory (Multiple Memory Model only) |
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43 // EHwChunk=5, // Not used |
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44 EPageTable=6, // iOwner=0 iOffset=index into KPageTableBase |
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45 EPageDir=7, // iOwner=ASID iOffset=index into Page Directory |
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46 EPtInfo=8, // iOwner=0 iOffset=index into KPageTableInfoBase |
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47 EShadow=9, // iOwner=phys ROM page iOffset=index into ROM |
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48 EPagedROM=10, // iOwner=0, iOffset=index into ROM |
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49 EPagedCode=11, // iOwner=DCodeSegMemory* iOffset=index into code chunk (not offset into CodeSeg!) |
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50 EPagedData=12, // NOT YET SUPPORTED |
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51 EPagedCache=13, // iOwner=DChunk* iOffset=index into chunk |
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52 EPagedFree=14, // In demand paging 'live list' but not used for any purpose |
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53 }; |
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54 |
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55 enum TState |
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56 { |
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57 EStateNormal = 0, // no special state |
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58 EStatePagedYoung = 1, // demand paged and is on the young list |
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59 EStatePagedOld = 2, // demand paged and is on the old list |
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60 EStatePagedDead = 3, // demand paged and is currently being modified |
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61 EStatePagedLocked = 4 // demand paged but is temporarily not being demand paged |
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62 }; |
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63 |
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64 inline TType Type() |
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65 { |
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66 return (TType)iType; |
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67 } |
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68 inline TState State() |
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69 { |
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70 return (TState)iState; |
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71 } |
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72 inline TAny* Owner() |
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73 { |
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74 return iOwner; |
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75 } |
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76 inline TUint32 Offset() |
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77 { |
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78 return iOffset; |
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79 } |
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80 inline TInt LockCount() |
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81 { |
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82 return iLockCount; |
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83 } |
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84 |
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85 /** Return the index of the zone the page is in |
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86 */ |
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87 inline TUint8 Zone() |
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88 { |
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89 return iZone; |
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90 } |
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91 |
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92 #ifdef _DEBUG |
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93 void Set(TType aType, TAny* aOwner, TUint32 aOffset); |
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94 void Change(TType aType,TState aState); |
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95 void SetState(TState aState); |
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96 void SetModifier(TAny* aModifier); |
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97 TInt CheckModified(TAny* aModifier); |
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98 void SetZone(TUint8 aZoneIndex); |
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99 #else |
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100 inline void Set(TType aType, TAny* aOwner, TUint32 aOffset) |
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101 { |
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102 (TUint16&)iType = aType; // also sets iState to EStateNormal |
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103 iOwner = aOwner; |
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104 iOffset = aOffset; |
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105 iModifier = 0; |
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106 } |
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107 inline void Change(TType aType,TState aState) |
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108 { |
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109 iType = aType; |
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110 iState = aState; |
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111 iModifier = 0; |
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112 } |
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113 inline void SetState(TState aState) |
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114 { |
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115 iState = aState; |
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116 iModifier = 0; |
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117 } |
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118 inline void SetModifier(TAny* aModifier) |
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119 { |
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120 iModifier = aModifier; |
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121 } |
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122 inline TInt CheckModified(TAny* aModifier) |
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123 { |
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124 return iModifier!=aModifier; |
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125 } |
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126 |
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127 inline void SetZone(TUint8 aZoneIndex) |
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128 { |
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129 iZone = aZoneIndex; |
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130 } |
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131 #endif // !_DEBUG |
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132 void Lock(); |
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133 TInt Unlock(); |
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134 |
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135 inline void SetFixed() |
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136 { |
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137 Set(EFixed,0,0); |
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138 iLockCount = 1; |
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139 } |
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140 inline void SetUnused() |
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141 { |
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142 __NK_ASSERT_DEBUG(0 == LockCount()); |
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143 (TUint16&)iType = EUnused; // also sets iState to zero |
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144 iModifier = 0; |
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145 // do not modify iOffset in this function because cache cleaning operations |
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146 // rely on using this value |
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147 } |
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148 inline void SetChunk(TAny* aChunk, TUint32 aOffset) |
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149 { |
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150 Set(EChunk,aChunk,aOffset); |
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151 } |
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152 inline void SetCodeSegMemory(TAny* aCodeSegMemory,TUint32 aOffset) |
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153 { |
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154 Set(ECodeSegMemory,aCodeSegMemory,aOffset); |
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155 } |
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156 // inline void SetHwChunk(TAny* aChunk, TUint32 aOffset) |
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157 // { |
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158 // Set(EHwChunk,aChunk,aOffset); |
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159 // } |
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160 inline void SetPageTable(TUint32 aId) |
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161 { |
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162 Set(EPageTable,0,aId); |
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163 } |
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164 inline void SetPageDir(TUint32 aOsAsid, TInt aOffset) |
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165 { |
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166 Set(EPageDir,(TAny*)aOsAsid,aOffset); |
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167 } |
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168 inline void SetPtInfo(TUint32 aOffset) |
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169 { |
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170 Set(EPtInfo,0,aOffset); |
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171 } |
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172 inline void SetShadow(TPhysAddr aOrigPhys, TUint32 aOffset) |
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173 { |
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174 Set(EShadow,(TAny*)aOrigPhys,aOffset); |
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175 } |
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176 inline void SetPagedROM(TUint32 aOffset) |
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177 { |
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178 Set(EPagedROM,0,aOffset); |
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179 } |
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180 inline void SetPagedCode(TAny* aCodeSegMemory, TUint32 aOffset) |
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181 { |
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182 Set(EPagedCode,aCodeSegMemory,aOffset); |
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183 } |
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184 |
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185 inline static SPageInfo* FromLink(SDblQueLink* aLink) |
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186 { return (SPageInfo*)((TInt)aLink-_FOFF(SPageInfo,iLink)); } |
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187 |
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188 inline TUint& PagedLock() |
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189 { return (TUint&)iLink.iPrev; } |
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190 |
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191 /** |
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192 Return the SPageInfo for a given page of physical RAM. |
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193 */ |
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194 inline static SPageInfo* FromPhysAddr(TPhysAddr aAddress); |
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195 |
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196 /** |
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197 Return physical address of the RAM page which this SPageInfo object is associated. |
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198 If the address has no SPageInfo, then a null pointer is returned. |
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199 */ |
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200 static SPageInfo* SafeFromPhysAddr(TPhysAddr aAddress); |
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201 |
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202 /** |
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203 Return physical address of the RAM page which this SPageInfo object is associated. |
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204 */ |
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205 inline TPhysAddr PhysAddr(); |
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206 |
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207 private: |
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208 TUint8 iType; // enum TType |
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209 TUint8 iState; // enum TState |
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210 TUint8 iZone; // The index of the zone the page is in, for use by DRamAllocator |
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211 TUint8 iSpare1; |
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212 TAny* iOwner; // owning object |
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213 TUint32 iOffset; // page offset withing owning object |
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214 TAny* iModifier; // pointer to object currently manipulating page |
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215 TUint32 iLockCount; // non-zero if page acquired by code outside of the kernel |
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216 TUint32 iSpare2; |
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217 public: |
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218 SDblQueLink iLink; // used for placing page into linked lists |
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219 }; |
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220 |
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221 /****************************************************************************** |
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222 Per-page table info |
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223 |
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224 Page count 0-256 |
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225 Usage unused |
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226 chunk ptr (26 bits) offset (12 bits) |
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227 HW chunk ptr (26 bits) offset (12 bits) |
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228 global offset (12 bits) |
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229 shadow page offset (12 bits) |
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230 |
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231 |
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232 *******************************************************************************/ |
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233 /** |
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234 @internalComponent |
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235 */ |
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236 struct SPageTableInfo |
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237 { |
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238 enum TAttribs |
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239 { |
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240 EUnused=0, |
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241 EChunk=1, |
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242 // EHwChunk=2, |
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243 EGlobal=3, |
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244 EShadow=4, |
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245 }; |
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246 |
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247 enum {EAttShift=6, EAttMask=0x3f}; |
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248 |
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249 inline TInt Attribs() |
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250 {return iAttPtr&EAttMask;} |
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251 inline TInt Count() |
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252 {return iCount;} |
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253 inline TUint32 Offset() |
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254 {return iOffset;} |
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255 inline TUint32 Ptr() |
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256 {return iAttPtr>>EAttShift;} |
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257 |
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258 inline void SetUnused() |
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259 {iCount=0; iOffset=0; iAttPtr=0;} |
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260 inline void SetChunk(TUint32 aChunk, TUint32 aOffset) |
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261 {iOffset=aOffset; iAttPtr=(aChunk<<EAttShift)|EChunk;} |
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262 // inline void SetHwChunk(TUint32 aChunk, TUint32 aOffset) |
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263 // {iOffset=aOffset; iAttPtr=(aChunk<<EAttShift)|EHwChunk;} |
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264 inline void SetGlobal(TUint32 aOffset) |
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265 {iOffset=aOffset; iAttPtr=EGlobal;} |
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266 inline void SetShadow(TUint32 aOffset) |
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267 {iCount=0; iOffset=aOffset; iAttPtr=EShadow;} |
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268 |
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269 TUint16 iCount; |
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270 TUint16 iOffset; |
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271 TUint32 iAttPtr; |
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272 }; |
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273 |
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274 /****************************************************************************** |
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275 Bitmap Allocators |
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276 |
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277 PageTableAllocator free page tables within allocated pages |
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278 PageTableLinearAllocator free linear addresses for page tables |
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279 ASIDAllocator free process slots |
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280 |
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281 Page directory linear address = PageDirBase + (ASID<<PageDirSizeShift) |
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282 Page table linear address = PageTableBase + (PTID<<PageTableSizeShift) |
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283 |
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284 Terminology |
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285 |
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286 Page table cluster = no. of page tables in one page |
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287 Page table block = no. of SPageTableInfo structures in one page |
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288 Page table group = no. of page tables mapped with a single page table |
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289 |
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290 Local = specific to process |
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291 Shared = subset of processes but not necessarily all |
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292 Global = all processes |
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293 *******************************************************************************/ |
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294 |
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295 /******************************************** |
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296 * Address range allocator |
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297 ********************************************/ |
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298 /** |
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299 @internalComponent |
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300 */ |
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301 class TLinearSection |
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302 { |
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303 public: |
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304 static TLinearSection* New(TLinAddr aBase, TLinAddr aEnd); |
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305 public: |
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306 TLinAddr iBase; |
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307 TLinAddr iEnd; |
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308 TBitMapAllocator iAllocator; // bitmap of used PDE positions |
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309 }; |
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310 |
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311 /****************************************************************************** |
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312 * Base class for MMU stuff |
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313 ******************************************************************************/ |
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314 |
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315 /** |
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316 @internalComponent |
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317 */ |
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318 const TPhysAddr KRomPhysAddrInvalid=0xFFFFFFFFu; |
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319 |
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320 /** |
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321 @internalComponent |
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322 */ |
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323 const TUint16 KPageTableNotPresentId=0xFFFF; |
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324 |
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325 /** |
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326 @internalComponent |
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327 */ |
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328 const TInt KUnmapPagesTLBFlushDeferred=0x80000000; |
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329 |
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330 /** |
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331 @internalComponent |
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332 */ |
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333 const TInt KUnmapPagesCountMask=0xffff; |
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334 |
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335 /** |
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336 @internalComponent |
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337 */ |
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338 const TInt KMaxPages = 32; |
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339 |
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340 /** |
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341 @internalComponent |
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342 */ |
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343 typedef TUint32 TPde; |
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344 |
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345 /** |
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346 @internalComponent |
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347 */ |
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348 typedef TUint32 TPte; |
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349 |
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350 class THwChunkAddressAllocator; |
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351 class RamCacheBase; |
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352 class Defrag; |
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353 class DRamAllocator; |
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354 class DMemModelCodeSegMemory; |
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355 class DMemModelChunk; |
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356 |
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357 /** |
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358 @internalComponent |
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359 */ |
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360 class MmuBase |
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361 { |
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362 public: |
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363 enum TPanic |
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364 { |
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365 EAsyncFreePageStillInUse=0, |
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366 EPtLinAllocCreateFailed=1, |
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367 EPtAllocCreateFailed=2, |
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368 EPageInfoCreateFailed=3, |
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369 EAsyncFreeListCreateFailed=4, |
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370 EPtBlockCountCreateFailed=5, |
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371 EPtGroupCountCreateFailed=6, |
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372 EInvalidPageTableAtBoot=7, |
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373 ERamAllocMutexCreateFailed=8, |
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374 EHwChunkMutexCreateFailed=9, |
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375 ECreateKernelSectionFailed=10, |
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376 ECreateHwChunkAllocFailed=11, |
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377 EFreeHwChunkAddrInvalid=12, |
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378 EFreeHwChunkIndexInvalid=13, |
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379 EBadMappedPageAfterBoot=14, |
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380 ERecoverRamDriveAllocPTIDFailed=15, |
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381 EMapPageTableBadExpand=16, |
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382 ERecoverRamDriveBadPageTable=17, |
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383 ERecoverRamDriveBadPage=18, |
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384 EBadFreePhysicalRam=19, |
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385 EPageLockedTooManyTimes=20, |
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386 EPageUnlockedTooManyTimes=21, |
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387 EPageInfoSetWhenNotUnused=22, |
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388 ERamCacheAllocFailed=23, |
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389 EDefragAllocFailed=24, |
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390 EDefragUnknownPageType=25, |
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391 EDefragUnknownPageTableType=27, |
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392 EDefragUnknownChunkType=28, |
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393 EDefragStackAllocFailed=29, |
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394 EDefragKernelChunkNoPageTable=30, |
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395 EDefragProcessWrongPageDir=31, |
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396 }; |
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397 public: |
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398 MmuBase(); |
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399 |
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400 // non virtual |
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401 TInt AllocPageTable(); |
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402 TInt DoAllocPageTable(TPhysAddr& aPhysAddr); |
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403 TInt InitPageTableInfo(TInt aId); |
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404 TInt MapPageTable(TInt aId, TPhysAddr aPhysAddr, TBool aAllowExpand=ETrue); |
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405 void FreePageTable(TInt aId); |
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406 TBool DoFreePageTable(TInt aId); |
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407 TInt AllocPhysicalRam(TInt aSize, TPhysAddr& aPhysAddr, TInt aAlign=0); |
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408 TInt ZoneAllocPhysicalRam(TUint* aZoneIdList, TUint aZoneIdCount, TInt aSize, TPhysAddr& aPhysAddr, TInt aAlign=0); |
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409 TInt AllocPhysicalRam(TInt aNumPages, TPhysAddr* aPageList); |
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410 TInt ZoneAllocPhysicalRam(TUint* aZoneIdList, TUint aZoneIdCount, TInt aNumPages, TPhysAddr* aPageList); |
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411 TInt FreePhysicalRam(TPhysAddr aPhysAddr, TInt aSize); |
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412 TInt FreePhysicalRam(TInt aNumPages, TPhysAddr* aPageList); |
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413 TInt ClaimPhysicalRam(TPhysAddr aPhysAddr, TInt aSize); |
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414 TInt GetPageTableId(TPhysAddr aPtPhys); |
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415 void MapRamPage(TLinAddr aAddr, TPhysAddr aPage, TPte aPtePerm); |
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416 void UnmapAndFree(TLinAddr aAddr, TInt aNumPages); |
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417 void FreePages(TPhysAddr* aPageList, TInt aCount, TZonePageType aPageType); |
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418 void CreateKernelSection(TLinAddr aEnd, TInt aHwChunkAlign); |
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419 TInt AllocateAllPageTables(TLinAddr aLinAddr, TInt aSize, TPde aPdePerm, TInt aMapShift, SPageTableInfo::TAttribs aAttrib); |
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420 TInt AllocShadowPage(TLinAddr aRomAddr); |
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421 TInt FreeShadowPage(TLinAddr aRomAddr); |
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422 TInt FreezeShadowPage(TLinAddr aRomAddr); |
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423 TInt FreeRamInBytes(); |
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424 TInt GetRamZonePageCount(TUint aId, SRamZonePageCount& aPageData); |
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425 TInt ModifyRamZoneFlags(TUint aId, TUint aClearMask, TUint aSetMask); |
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426 |
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427 // RAM allocator and defrag interfaces. |
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428 void RamAllocLock(); |
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429 void RamAllocUnlock(); |
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430 TUint NumberOfFreeDpPages(); |
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431 TInt MovePage(TPhysAddr aOld, TPhysAddr& aNew, TUint aBlockZoneId, TBool aBlockRest); |
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432 TInt DiscardPage(TPhysAddr aAddr, TUint aBlockZoneId, TBool aBlockRest); |
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433 |
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434 // virtual |
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435 virtual void Init1(); |
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436 virtual void Init2(); |
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437 virtual void Init3(); |
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438 virtual THwChunkAddressAllocator* MappingRegion(TUint aMapAttr); |
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439 virtual TInt RecoverRamDrive(); |
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440 virtual TInt CopyToShadowMemory(TLinAddr aDest, TLinAddr aSrc, TUint32 aLength); |
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441 |
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442 // cpu dependent page moving method - cutils.cia |
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443 TInt MoveKernelStackPage(DChunk* aChunk, TUint32 aOffset, TPhysAddr aOld, TPhysAddr& aNew, TUint aBlockZoneId, TBool aBlockRest); |
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444 |
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445 // pure virtual |
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446 virtual void DoInit2()=0; |
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447 virtual TBool PteIsPresent(TPte aPte)=0; |
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448 virtual TPhysAddr PtePhysAddr(TPte aPte, TInt aPteIndex)=0; |
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449 virtual TPhysAddr PdePhysAddr(TLinAddr aAddr)=0; |
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450 virtual void SetupInitialPageInfo(SPageInfo* aPageInfo, TLinAddr aChunkAddr, TInt aPdeIndex)=0; |
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451 virtual void SetupInitialPageTableInfo(TInt aId, TLinAddr aChunkAddr, TInt aNumPtes)=0; |
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452 virtual void AssignPageTable(TInt aId, TInt aUsage, TAny* aObject, TLinAddr aAddr, TPde aPdePerm)=0; |
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453 virtual TInt UnassignPageTable(TLinAddr aAddr)=0; |
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454 virtual void BootstrapPageTable(TInt aXptId, TPhysAddr aXptPhys, TInt aId, TPhysAddr aPhysAddr)=0; |
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455 virtual void FixupXPageTable(TInt aId, TLinAddr aTempMap, TPhysAddr aOld, TPhysAddr aNew)=0; |
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456 virtual TInt PageTableId(TLinAddr aAddr)=0; |
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457 virtual TInt BootPageTableId(TLinAddr aAddr, TPhysAddr& aPtPhys)=0; |
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458 virtual void ClearPageTable(TInt aId, TInt aFirstIndex=0)=0; |
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459 virtual TPhysAddr LinearToPhysical(TLinAddr aAddr)=0; |
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460 virtual TInt LinearToPhysical(TLinAddr aAddr, TInt aSize, TPhysAddr& aPhysicalAddress, TPhysAddr* aPhysicalPageList=NULL)=0; |
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461 virtual void MapRamPages(TInt aId, SPageInfo::TType aType, TAny* aPtr, TUint32 aOffset, const TPhysAddr* aPageList, TInt aNumPages, TPte aPtePerm)=0; |
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462 virtual void MapPhysicalPages(TInt aId, SPageInfo::TType aType, TAny* aPtr, TUint32 aOffset, TPhysAddr aPhysAddr, TInt aNumPages, TPte aPtePerm)=0; |
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463 virtual void RemapPage(TInt aId, TUint32 aAddr, TPhysAddr aOldAddr, TPhysAddr aNewAddr, TPte aPtePerm, DProcess* aProcess)=0; |
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464 virtual TInt UnmapPages(TInt aId, TUint32 aAddr, TInt aNumPages, TPhysAddr* aPageList, TBool aSetPagesFree, TInt& aNumPtes, TInt& aNumFree, DProcess* aProcess)=0; |
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465 virtual void ClearRamDrive(TLinAddr aStart)=0; |
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466 virtual TInt PdePtePermissions(TUint& aMapAttr, TPde& aPde, TPte& aPte)=0; |
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467 virtual void Map(TLinAddr aLinAddr, TPhysAddr aPhysAddr, TInt aSize, TPde aPdePerm, TPte aPtePerm, TInt aMapShift)=0; |
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468 virtual void Unmap(TLinAddr aLinAddr, TInt aSize)=0; |
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469 virtual void InitShadowPageTable(TInt aId, TLinAddr aRomAddr, TPhysAddr aOrigPhys)=0; |
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470 virtual void InitShadowPage(TPhysAddr aShadowPhys, TLinAddr aRomAddr)=0; |
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471 virtual void DoUnmapShadowPage(TInt aId, TLinAddr aRomAddr, TPhysAddr aOrigPhys)=0; |
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472 virtual TInt UnassignShadowPageTable(TLinAddr aRomAddr, TPhysAddr aOrigPhys)=0; |
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473 virtual void DoFreezeShadowPage(TInt aId, TLinAddr aRomAddr)=0; |
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474 virtual void FlushShadow(TLinAddr aRomAddr)=0; |
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475 virtual void AssignShadowPageTable(TInt aId, TLinAddr aRomAddr)=0; |
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476 virtual void ClearPages(TInt aNumPages, TPhysAddr* aPageList, TUint8 aClearByte = KChunkClearByteDefault)=0; |
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477 virtual void Pagify(TInt aId, TLinAddr aLinAddr)=0; |
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478 virtual void CacheMaintenanceOnDecommit(const TPhysAddr* aPhysAdr, TInt aPageCount)=0; |
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479 virtual void CacheMaintenanceOnDecommit(const TPhysAddr aPhysAdr)=0; |
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480 virtual void CacheMaintenanceOnPreserve(const TPhysAddr* aPhysAdr, TInt aPageCount, TUint aMapAttr)=0; |
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481 virtual void CacheMaintenanceOnPreserve(const TPhysAddr aPhysAdr, TUint aMapAttr)=0; |
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482 virtual void CacheMaintenanceOnPreserve(TPhysAddr aPhysAddr, TInt aSize, TLinAddr aLinAddr, TUint iMapAttr)=0; |
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483 |
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484 // memory model dependent page moving methods - mdefrag.cpp |
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485 virtual TInt MoveCodeSegMemoryPage(DMemModelCodeSegMemory* aCodeSegMemory, TUint32 aOffset, TPhysAddr aOld, TPhysAddr& aNew, TUint aBlockZoneId, TBool aBlockRest)=0; |
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486 virtual TInt MoveCodeChunkPage(DChunk* aChunk, TUint32 aOffset, TPhysAddr aOld, TPhysAddr& aNew, TUint aBlockZoneId, TBool aBlockRest)=0; |
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487 virtual TInt MoveDataChunkPage(DChunk* aChunk, TUint32 aOffset, TPhysAddr aOld, TPhysAddr& aNew, TUint aBlockZoneId, TBool aBlockRest)=0; |
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488 |
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489 // cpu and memory model dependent page moving methods - xmmu.cpp |
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490 virtual TInt RamDefragFault(TAny* aExceptionInfo)=0; |
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491 virtual void DisablePageModification(DMemModelChunk* aChunk, TInt aOffset)=0; |
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492 virtual TPte PtePermissions(TChunkType aChunkType)=0; |
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493 |
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494 public: |
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495 static TUint32 RoundToPageSize(TUint32 aSize); |
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496 static TUint32 RoundToChunkSize(TUint32 aSize); |
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497 static TInt RoundUpRangeToPageSize(TUint32& aBase, TUint32& aSize); |
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498 static void Wait(); |
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499 static void Signal(); |
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500 static void WaitHwChunk(); |
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501 static void SignalHwChunk(); |
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502 static void Panic(TPanic aPanic); |
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503 public: |
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504 inline TLinAddr PageTableLinAddr(TInt aId) |
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505 {return iPageTableLinBase+(aId<<iPageTableShift);} |
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506 inline SPageTableInfo& PtInfo(TInt aId) |
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507 {return iPtInfo[aId];} |
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508 |
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509 inline TLinAddr PtInfoBlockLinAddr(TInt aBlock) |
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510 {return (TLinAddr)iPtInfo+(aBlock<<iPageShift);} |
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511 |
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512 /** Get the page table info block number from a page table ID |
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513 @param aId The ID of the page table. |
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514 @return The page table info block |
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515 */ |
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516 inline TInt PtInfoBlock(TInt aId) |
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517 {return aId >> iPtBlockShift;} |
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518 |
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519 /** |
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520 @return The page table entry for the page table info pages. |
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521 */ |
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522 inline TPte PtInfoPtePerm() |
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523 {return iPtInfoPtePerm;} |
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524 |
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525 public: |
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526 TInt AllocRamPages(TPhysAddr* aPageList, TInt aNumPages, TZonePageType aPageType, TUint aBlockedZoneId=KRamZoneInvalidId, TBool aBlockRest=EFalse); |
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527 TInt ZoneAllocRamPages(TUint* aZoneIdList, TUint aZoneIdCount, TPhysAddr* aPageList, TInt aNumPages, TZonePageType aPageType); |
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528 TInt AllocContiguousRam(TInt aSize, TPhysAddr& aPhysAddr, TZonePageType aPageType, TInt aAlign, TUint aBlockedZoneId=KRamZoneInvalidId, TBool aBlockRest=EFalse); |
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529 TInt ZoneAllocContiguousRam(TUint* aZoneIdList, TUint aZoneIdCount, TInt aSize, TPhysAddr& aPhysAddr, TZonePageType aPageType, TInt aAlign); |
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530 |
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531 public: |
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532 TInt iPageSize; // page size in bytes |
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533 TInt iPageMask; // page size - 1 |
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534 TInt iPageShift; // log2(page size) |
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535 TInt iChunkSize; // PDE size in bytes |
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536 TInt iChunkMask; // PDE size - 1 |
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537 TInt iChunkShift; // log2(PDE size) |
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538 TInt iPageTableSize; // 2nd level page table size in bytes |
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539 TInt iPageTableMask; // 2nd level page table size - 1 |
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540 TInt iPageTableShift; // log2(2nd level page table size) |
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541 TInt iPtClusterSize; // number of page tables per page |
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542 TInt iPtClusterMask; // number of page tables per page - 1 |
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543 TInt iPtClusterShift; // log2(number of page tables per page) |
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544 TInt iPtBlockSize; // number of SPageTableInfo per page |
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545 TInt iPtBlockMask; // number of SPageTableInfo per page - 1 |
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546 TInt iPtBlockShift; // log2(number of SPageTableInfo per page) |
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547 TInt iPtGroupSize; // number of page tables mapped by a page table |
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548 TInt iPtGroupMask; // number of page tables mapped by a page table - 1 |
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549 TInt iPtGroupShift; // log2(number of page tables mapped by a page table) |
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550 TInt iMaxPageTables; // maximum number of page tables (<65536) |
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551 TInt* iPtBlockCount; // number of page table pages in each block |
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552 TInt* iPtGroupCount; // number of page table pages in each group |
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553 TInt iNumPages; // Number of pages being managed |
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554 SPageTableInfo* iPtInfo; // per-page table information array |
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555 TLinAddr iPageTableLinBase; // base address of page tables |
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556 DRamAllocator* iRamPageAllocator; |
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557 TBitMapAllocator* iPageTableAllocator; // NULL if page table size = page size |
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558 TBitMapAllocator* iPageTableLinearAllocator; |
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559 TInt iInitialFreeMemory; |
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560 TBool iAllocFailed; |
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561 TPte iPtInfoPtePerm; |
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562 TPte iPtPtePerm; |
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563 TPde iPtPdePerm; |
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564 TPte* iTempPte; // PTE used for temporary mappings |
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565 TLinAddr iTempAddr; // address corresponding to iTempPte |
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566 TLinearSection* iKernelSection; // bitmap used to allocate kernel section addresses |
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567 THwChunkAddressAllocator* iHwChunkAllocator; // address allocator for HW chunks in kernel section |
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568 TUint32 iMapSizes; // bit mask of supported mapping sizes |
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569 TUint iDecommitThreshold; // threshold for selective/global cache flush on decommit for VIPT caches |
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570 TLinAddr iRomLinearBase; |
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571 TLinAddr iRomLinearEnd; |
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572 TPte iShadowPtePerm; |
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573 TPde iShadowPdePerm; |
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574 |
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575 // Page moving and defrag fault handling members. |
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576 TLinAddr iAltStackBase; |
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577 TLinAddr iDisabledAddr; |
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578 TInt iDisabledAddrAsid; |
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579 TPte* iDisabledPte; |
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580 TPte iDisabledOldVal; |
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581 |
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582 RamCacheBase* iRamCache; |
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583 Defrag* iDefrag; |
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584 |
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585 static DMutex* HwChunkMutex; // mutex protecting HW chunk address allocators |
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586 static DMutex* RamAllocatorMutex; // the main mutex protecting alloc/dealloc and most map/unmap |
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587 static MmuBase* TheMmu; // pointer to the single instance of this class |
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588 static const SRamZone* RamZoneConfig; /**<Pointer to variant specified array containing details on RAM banks and their allocation preferences*/ |
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589 static TRamZoneCallback RamZoneCallback; /**<Pointer to callback function to be invoked when RAM power state changes*/ |
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590 |
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591 public: |
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592 friend class Monitor; |
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593 }; |
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594 |
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595 |
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596 /****************************************************************************** |
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597 * Address allocator for HW chunks |
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598 ******************************************************************************/ |
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599 |
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600 /** |
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601 @internalComponent |
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602 */ |
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603 class THwChunkRegion |
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604 { |
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605 public: |
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606 inline THwChunkRegion(TInt aIndex, TInt aSize, TPde aPdePerm) |
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607 : iIndex((TUint16)aIndex), iRegionSize((TUint16)aSize), iPdePerm(aPdePerm) |
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608 {} |
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609 public: |
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610 TUint16 iIndex; // index of base of this region in linear section |
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611 TUint16 iRegionSize; // number of PDEs covered; 0 means page table |
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612 union |
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613 { |
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614 TPde iPdePerm; // PDE permissions for this region |
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615 THwChunkRegion* iNext; // used during deallocation |
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616 }; |
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617 }; |
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618 |
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619 /** |
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620 @internalComponent |
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621 */ |
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622 class THwChunkPageTable : public THwChunkRegion |
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623 { |
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624 public: |
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625 THwChunkPageTable(TInt aIndex, TInt aSize, TPde aPdePerm); |
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626 static THwChunkPageTable* New(TInt aIndex, TPde aPdePerm); |
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627 public: |
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628 TBitMapAllocator iAllocator; // bitmap of used page positions |
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629 }; |
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630 |
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631 /** |
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632 @internalComponent |
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633 */ |
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634 class THwChunkAddressAllocator : public RPointerArray<THwChunkRegion> |
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635 { |
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636 public: |
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637 static THwChunkAddressAllocator* New(TInt aAlign, TLinearSection* aSection); |
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638 TLinAddr Alloc(TInt aSize, TInt aAlign, TInt aOffset, TPde aPdePerm); |
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639 THwChunkRegion* Free(TLinAddr aAddr, TInt aSize); |
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640 public: |
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641 THwChunkAddressAllocator(); |
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642 TLinAddr SearchExisting(TInt aNumPages, TInt aPageAlign, TInt aPageOffset, TPde aPdePerm); |
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643 void Discard(THwChunkRegion* aRegion); |
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644 static TInt Order(const THwChunkRegion& a1, const THwChunkRegion& a2); |
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645 THwChunkRegion* NewRegion(TInt aIndex, TInt aSize, TPde aPdePerm); |
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646 THwChunkPageTable* NewPageTable(TInt aIndex, TPde aPdePerm, TInt aInitB, TInt aInitC); |
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647 public: |
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648 TInt iAlign; // alignment required for allocated addresses |
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649 TLinearSection* iSection; // linear section in which allocation occurs |
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650 }; |
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651 |
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652 |
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653 /** Hardware chunk |
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654 |
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655 @internalComponent |
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656 */ |
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657 class DMemModelChunkHw : public DPlatChunkHw |
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658 { |
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659 public: |
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660 virtual TInt Close(TAny* aPtr); |
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661 public: |
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662 TInt AllocateLinearAddress(TPde aPdePerm); |
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663 void DeallocateLinearAddress(); |
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664 public: |
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665 THwChunkAddressAllocator* iAllocator; |
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666 }; |
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667 |
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668 |
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669 /****************************************************************************** |
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670 * MMU-specifc code segment data |
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671 ******************************************************************************/ |
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672 |
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673 /** |
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674 @internalComponent |
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675 */ |
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676 class DMmuCodeSegMemory : public DEpocCodeSegMemory |
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677 { |
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678 public: |
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679 DMmuCodeSegMemory(DEpocCodeSeg* aCodeSeg); |
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680 ~DMmuCodeSegMemory(); |
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681 virtual TInt Create(TCodeSegCreateInfo& aInfo); |
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682 virtual TInt Loaded(TCodeSegCreateInfo& aInfo); |
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683 |
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684 /** |
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685 Apply code relocations and import fixups to one page of code. |
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686 @param aBuffer The buffer containg the code |
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687 @param aCodeAddress The address the page will be mapped at |
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688 */ |
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689 void ApplyCodeFixups(TUint32* aBuffer, TLinAddr aCodeAddress); |
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690 |
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691 /** |
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692 Apply code relocations and import fixups to one page of code. |
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693 Called by DMemModelCodeSegMemory::Loaded to fixup pages which are already paged-in. |
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694 |
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695 @param aBuffer The buffer containg the code |
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696 @param aCodeAddress The address the page will be mapped at |
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697 */ |
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698 TInt ApplyCodeFixupsOnLoad(TUint32* aBuffer, TLinAddr aCodeAddress); |
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699 private: |
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700 TInt ReadBlockMap(const TCodeSegCreateInfo& aInfo); |
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701 TInt ReadFixupTables(const TCodeSegCreateInfo& aInfo); |
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702 public: |
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703 TBool iIsDemandPaged; |
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704 |
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705 TInt iPageCount; // Number of pages used for code |
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706 TInt iDataPageCount; // Number of extra pages used to store data section |
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707 TUint8* iCodeRelocTable; // Code relocation information |
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708 TInt iCodeRelocTableSize; // Size of code relocation table in bytes |
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709 TUint8* iImportFixupTable; // Import fixup information |
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710 TInt iImportFixupTableSize; // Size of import fixup table in bytes |
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711 TUint32 iCodeDelta; // Code relocation delta |
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712 TUint32 iDataDelta; // Data relocation delta |
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713 |
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714 TInt iCompressionType; // Compression scheme in use |
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715 TInt32* iCodePageOffsets; // Array of compressed page offsets within the file |
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716 TInt iCodeLocalDrive; // Local drive number |
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717 TBlockMap iBlockMap; // Kernel-side representation of block map |
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718 TInt iCodeStartInFile; // Offset of (possibly compressed) code from start of file |
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719 |
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720 TAny* iDataSectionMemory; // pointer to saved copy of data section (when demand paging) |
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721 |
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722 TInt iCodeAllocBase; |
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723 }; |
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724 |
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725 #endif |