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1 // Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // e32\include\memmodel\epoc\platform.h |
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15 // Public header file for device drivers |
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16 // |
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17 // WARNING: This file contains some APIs which are internal and are subject |
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18 // to change without notice. Such APIs should therefore not be used |
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19 // outside the Kernel and Hardware Services package. |
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20 // |
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21 |
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22 #ifndef __M32STD_H__ |
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23 #define __M32STD_H__ |
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24 #include <kernel/kernel.h> |
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25 #include <kernel/kernboot.h> |
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26 #ifdef __EPOC32__ |
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27 #include <e32rom.h> |
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28 #else |
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29 class TRomHeader; |
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30 class TRomImageHeader; |
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31 class TRomEntry; |
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32 #endif |
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33 // |
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34 |
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35 /******************************************** |
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36 * Hardware chunk abstraction |
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37 ********************************************/ |
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38 |
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39 /** |
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40 The list of memory types (aka cache attributes) in Kernel on ARMv6K, ARMv7 and later platforms. |
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41 Types 0-3 can be used on all platforms. Types 4-7 can be used only on the platforms with memory type remapping. |
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42 @see TMappingAttributes2 |
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43 @publishedPartner |
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44 @released |
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45 */ |
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46 enum TMemoryType |
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47 { |
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48 EMemAttStronglyOrdered = 0, /**< Strongly Ordered memory.*/ |
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49 EMemAttDevice = 1, /**< Device memory.*/ |
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50 EMemAttNormalUncached = 2, /**< Uncached Normal memory. Writes may combine.*/ |
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51 EMemAttNormalCached = 3, /**< Fully cached (Write-Back, Read/Write Allocate, Normal memory).*/ |
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52 EMemAttKernelInternal4 = 4, /**< @internalComponent. Not to be used by device drivers.*/ |
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53 EMemAttPlatformSpecific5= 5, /**< Defined by Baseport - H/W independent.*/ |
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54 EMemAttPlatformSpecific6= 6, /**< Defined by Baseport - H/W specific - see ARM core's document for the details.*/ |
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55 EMemAttPlatformSpecific7= 7 /**< Defined by Baseport - H/W independent.*/ |
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56 }; |
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57 |
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58 const TUint KMemoryTypeShift = 3; /**< @internalComponent. The number of bits in a TMemoryType value.*/ |
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59 const TUint KMemoryTypeMask = (1<<KMemoryTypeShift)-1; /**< @internalComponent. Mask value for extracting a TMemoryType value from a bitfield.*/ |
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60 |
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61 /** |
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62 Memory mapping permissions and attributes. |
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63 |
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64 @see TChunkCreateInfo |
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65 @see Kern::ChunkCreate |
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66 @see DSharedIoBuffer::New |
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67 @see DPlatChunkHw::New |
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68 @see Kern::ChunkPhysicalAddress |
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69 @see Cache::SyncMemoryBeforeDmaWrite |
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70 @see Cache::SyncMemoryBeforeDmaRead |
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71 @see Cache::SyncMemoryBeforeDmaWrite |
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72 |
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73 @publishedPartner |
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74 @released |
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75 */ |
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76 enum TMappingAttributes |
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77 { |
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78 // access permissions for read |
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79 EMapAttrReadNoone=0x0, /**< Sets the memory as not readable in any mode */ |
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80 EMapAttrReadSup=0x1, /**< Sets the memory as readable only from Kernel (Supervisor) mode */ |
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81 EMapAttrReadUser=0x4, /**< Sets the memory as readable for user, hence it can be read in both user and supervisor mode*/ |
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82 EMapAttrReadMask=0xF, /**< Used for masking read attributes*/ |
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83 |
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84 // access permissions for write |
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85 EMapAttrWriteNoone=0x00, /**< Sets the memory as not writable in any mode */ |
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86 EMapAttrWriteSup=0x10, /**< Sets the memory as writable only from Kernel (Supervisor) mode */ |
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87 EMapAttrWriteUser=0x40, /**< Sets the memory as writable for user, hence it can be written in both user and supervisor mode*/ |
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88 EMapAttrWriteMask=0xF0, /**< Used for masking write attributes*/ |
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89 |
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90 // access permissions for execute |
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91 EMapAttrExecNoone=0x000, /**< Sets the memory as not executable in any mode */ |
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92 EMapAttrExecSup=0x100, /**< Sets the memory as executable only from Kernel (Supervisor) mode */ |
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93 EMapAttrExecUser=0x400, /**< Sets the memory as executable for user, hence it can be executed in both user and supervisor mode*/ |
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94 EMapAttrExecMask=0xF00, /**< Used for masking execute attributes*/ |
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95 |
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96 // access permissions - popular combinations |
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97 EMapAttrSupRo=0x01, /**< Supervisor has read only and user has no access permissions*/ |
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98 EMapAttrSupRw=0x11, /**< Supervisor has read/write and user has no access permissions*/ |
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99 EMapAttrSupRwx=0x111, /**< Supervisor has read/write/execute and user has no access permissions*/ |
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100 EMapAttrUserRo=0x14, /**< Supervisor has read/write and user has read only permissions*/ |
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101 EMapAttrUserRw=0x44, /**< Supervisor and user both have read/write permissions*/ |
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102 EMapAttrUserRwx=0x444, /**< Supervisor and user both have read/write/execute permissions*/ |
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103 EMapAttrAccessMask=0xFFF, /**< Used for masking access permissions attribute for popular combination */ |
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104 |
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105 // Level 1 cache/buffer attributes |
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106 EMapAttrFullyBlocking=0x0000, /**< Level 1 cache/buffer attributes sets the memory as uncached, unbuffered (may not be L2 cached)*/ |
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107 EMapAttrBufferedNC=0x1000, /**< Level 1 cache/buffer attributes sets the memory as uncached, buffered, writes do not coalesce (may not be L2 cached)*/ |
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108 EMapAttrBufferedC=0x2000, /**< Level 1 cache/buffer attributes sets the memory as uncached, buffered, writes may coalesce (may not be L2 cached)*/ |
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109 EMapAttrL1Uncached=0x3000, /**< Level 1 cache/buffer attributes sets the memory as uncached, buffered, writes may coalesce (may be L2 cached)*/ |
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110 EMapAttrCachedWTRA=0x4000, /**< Level 1 cache/buffer attributes sets the memory as write-through cached, read allocate*/ |
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111 EMapAttrCachedWTWA=0x5000, /**< Level 1 cache/buffer attributes sets the memory as write-through cached, read/write allocate*/ |
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112 EMapAttrCachedWBRA=0x6000, /**< Level 1 cache/buffer attributes sets the memory as write-back cached, read allocate*/ |
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113 EMapAttrCachedWBWA=0x7000, /**< Level 1 cache/buffer attributes sets memory as write-back cached, read/write allocate*/ |
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114 EMapAttrAltCacheWTRA=0x8000, /**< Level 1 cache/buffer attributes sets memory as write-through cached, read allocate, use alternate cache*/ |
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115 EMapAttrAltCacheWTWA=0x9000, /**< Level 1 cache/buffer attributes sets memory as write-through cached, read/write allocate, use alternate cache*/ |
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116 EMapAttrAltCacheWBRA=0xA000, /**< Level 1 cache/buffer attributes sets memory as write-back cached, read allocate, use alternate cache*/ |
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117 EMapAttrAltCacheWBWA=0xB000, /**< Level 1 cache/buffer attributes write-back cached, read/write allocate, use alternate cache*/ |
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118 EMapAttrL1CachedMax=0xF000, /**< Used to make memory maximally cached in L1 cache*/ |
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119 EMapAttrL1CacheMask=0xF000, /**< Used for masking L1 cache attributes*/ |
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120 |
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121 // Level 2 cache attributes |
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122 EMapAttrL2Uncached=0x00000, /**< Level 2 cache attributes used to set memory as uncached at level 2 */ |
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123 EMapAttrL2CachedWTRA=0x40000, /**< Level 2 cache attributes sets memory as write-through cached, read allocate*/ |
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124 EMapAttrL2CachedWTWA=0x50000, /**< Level 2 cache attributes sets memory as write-through cached, read/write allocate*/ |
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125 EMapAttrL2CachedWBRA=0x60000, /**< Level 2 cache attributes sets memory as write-back cached, read allocate*/ |
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126 EMapAttrL2CachedWBWA=0x70000, /**< Level 2 cache attributes sets memory as write-back cached, read/write allocate*/ |
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127 EMapAttrL2CachedMax=0xF0000, /**< Used to make memory maximally cached in L2 cache*/ |
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128 EMapAttrL2CacheMask=0xF0000, /**< Used for masking L2 cache attributes*/ |
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129 |
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130 // Others |
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131 EMapAttrCachedMax=0xFF000, /**< Used to set memory as maximally cached for system (fully cached in L1&L2 cache)*/ |
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132 EMapAttrShared=0x100000, /**< Used to set the memory as shared with other processors*/ |
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133 EMapAttrUseECC=0x200000, /**< Used for error correcting code*/ |
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134 }; |
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135 |
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136 /** |
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137 Container class for memory region's attributes. |
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138 It is intended for ARM platforms with memory type and access permission remapping |
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139 (arm11mpcore, arm1176, cortex_a8 and later), but could be used on any previous platform as well. |
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140 |
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141 The object of this type can replace TMappingAttributes bit mask whereever it is in use. For example: |
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142 @code |
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143 TChunkCreateInfo chunkInfo; |
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144 ... |
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145 new (&chunkInfo.iMapAttr) TMappingAttributes2(EMemAttStronglyOrdered,EFalse,ETrue); |
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146 r = Kern::ChunkCreate(chunkInfo, ...); |
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147 @endcode |
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148 |
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149 @see TMemoryType |
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150 @see TMappingAttributes |
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151 @see TChunkCreateInfo |
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152 @see Kern::ChunkCreate |
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153 @see DSharedIoBuffer::New |
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154 @see DPlatChunkHw::New |
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155 @see Kern::ChunkPhysicalAddress |
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156 @see Cache::SyncMemoryBeforeDmaWrite |
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157 @see Cache::SyncMemoryBeforeDmaRead |
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158 @see Cache::SyncMemoryBeforeDmaWrite |
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159 |
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160 @publishedPartner |
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161 @released |
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162 */ |
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163 class TMappingAttributes2 |
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164 { |
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165 public: |
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166 /** |
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167 Constructor. |
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168 Memory is always readable by Kernel. Other attributes are defined by input parameters, as follows: |
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169 @param aType Type (aka cache attributes) of the memory. |
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170 @param aUserAccess True if memory is also accessed from user code, false if it is only accessible from kernel. |
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171 @param aWritable True if memory is writable, false if this is read only memory. |
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172 @param aExecutable True if memory contains code or data, false if it only contains data. |
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173 Default argument value is false. |
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174 @param aShared Shared attribute of the mapping: |
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175 <0 Default value for the platform, e.g. Shareable for SMP, Unshareable for uni-processor. |
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176 ==0 Unshareable memory |
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177 >0 Shareable memory |
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178 To ensure future compatibility, use the value <0 except when absolutely neccessary. |
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179 Default argument value is -1. |
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180 @param aParity Parity error attribute of the mapping: |
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181 <0 Default value for the platform (which is off on all platforms so far). |
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182 ==0 Parity error doesn't generate external abort. |
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183 >0 Parity error generates external abort. |
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184 To ensure future compatibility, use the value <0 except when absolutely neccessary. |
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185 Default argument value is -1. |
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186 |
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187 @see TMemoryType |
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188 */ |
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189 IMPORT_C TMappingAttributes2(TMemoryType aType , |
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190 TBool aUserAccess , |
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191 TBool aWritable , |
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192 TBool aExecutable = EFalse, |
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193 TInt aShared = -1, |
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194 TInt aParity = -1); |
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195 |
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196 TMappingAttributes2(TUint aMapAttr);/**< @internalComponent*/ |
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197 TMemoryType Type(); /**< @internalComponent @return Type of the memory (aka cache attributes).*/ |
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198 TBool UserAccess(); /**< @internalComponent @return True if memory can be accessed from user code.*/ |
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199 TBool Writable(); /**< @internalComponent @return True if memory can be written into, false if this is reaad only memory.*/ |
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200 TBool Executable(); /**< @internalComponent @return True if memory can contain code and data, false if it can only contain data.*/ |
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201 TBool Shared(); /**< @internalComponent @return True if memory is shared, false if not.*/ |
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202 TBool Parity(); /**< @internalComponent @return True if parity error generates external abort, false if not.*/ |
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203 TBool ObjectType2();/**< @internalComponent @return True if the object is TMappingAttributes2, false if it is TMappingAttributes bitmask.*/ |
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204 private: |
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205 static void Panic(TInt aPanic); /**< @internalComponent*/ |
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206 private: |
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207 TUint32 iAttributes; /**< @internalComponent*/ |
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208 }; |
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209 |
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210 /** |
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211 @internalComponent |
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212 */ |
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213 inline TBool ComparePermissions(TInt aActual, TInt aRequired) |
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214 { |
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215 return ((aActual&EMapAttrReadMask)>=(aRequired&EMapAttrReadMask)) && |
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216 ((aActual&EMapAttrWriteMask)>=(aRequired&EMapAttrWriteMask)) && |
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217 ((aActual&EMapAttrExecMask)>=(aRequired&EMapAttrExecMask)); |
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218 } |
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219 |
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220 |
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221 /** Hardware Chunk class |
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222 Class representing a global mapping of I/O or global memory buffers |
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223 |
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224 @publishedPartner |
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225 @released |
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226 */ |
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227 class DPlatChunkHw : public DObject |
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228 { |
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229 public: |
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230 IMPORT_C static TInt New(DPlatChunkHw*& aChunk, TPhysAddr anAddr, TInt aSize, TUint aAttribs); |
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231 inline TLinAddr LinearAddress() {return iLinAddr;} |
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232 inline TPhysAddr PhysicalAddress() {return iPhysAddr;} |
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233 public: |
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234 /** @internalComponent */ |
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235 static TInt DoNew(DPlatChunkHw*& aChunk, TPhysAddr anAddr, TInt aSize, TUint aAttribs); |
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236 public: |
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237 TPhysAddr iPhysAddr; /**< @internalComponent */ |
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238 TLinAddr iLinAddr; /**< @internalComponent */ |
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239 TInt iSize; /**< @internalComponent */ |
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240 TUint iAttribs; /**< @internalComponent */ // mapping attributes |
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241 }; |
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242 |
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243 /******************************************** |
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244 * Exports from layer 2 or below of the kernel |
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245 * which are not available to layer 1 |
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246 ********************************************/ |
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247 |
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248 /** |
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249 Specifies the operation performed by the TRamZoneCallback function. |
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250 @see TRamZoneCallback |
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251 @publishedPartner |
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252 @released |
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253 */ |
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254 enum TRamZoneOp |
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255 { |
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256 /** Informs the variant that a specified RAM zone is not currently |
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257 being used and therefore it may be possible to save power by not refreshing |
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258 this zone or, if the rest of the its RAM IC's zones are also empty, powering |
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259 down the RAM IC. |
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260 |
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261 The TRamZoneCallback parameter aParam1 is the ID of the zone. |
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262 The TRamZoneCallback parameter aParam2 is a pointer to const array of TUints |
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263 that are the bit masks of the zones' power status. |
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264 */ |
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265 ERamZoneOp_PowerDown=0, |
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266 |
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267 /** Informs the variant that a specified RAM zone is now required for use |
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268 and therefore it must be ready. |
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269 The variant should ensure the zone is refreshed, if required, and that the |
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270 RAM IC is powered and fully initialised. |
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271 |
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272 The TRamZoneCallback parameter aParam1 is the ID of the zone. |
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273 The TRamZoneCallback parameter aParam2 is a pointer to const array of TUints |
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274 that are the bit masks of the zones' power status. |
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275 */ |
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276 ERamZoneOp_PowerUp=1, |
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277 |
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278 /** Operation that informs the variant of the RAM zones that have been used |
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279 during the initial stages of the boot process. Any RAM zones that are not |
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280 in use may be powered down or not refreshed to save power. |
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281 This will be the first operation requested of the variant and it is only |
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282 issued once. |
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283 |
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284 The TRamZoneCallback parameter aParam1 is unused by this operation. |
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285 The TRamZoneCallback parameter aParam2 is a pointer to const array of TUints |
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286 that are the bit masks of the zones' power status. |
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287 */ |
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288 ERamZoneOp_Init=2, |
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289 }; |
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290 |
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291 |
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292 /** |
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293 Call back function that is invoked by the kernel when its RAM allocator determines |
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294 that an operation can be performed on a particular RAM zone. |
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295 |
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296 @publishedPartner |
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297 @released |
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298 |
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299 @param aOp Type of operation to perform; a value of TRamZoneOp |
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300 @param aParam1 A value whose use is defined by the TRamZoneOp to be performed |
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301 @param aParam2 A value whose use is defined by the TRamZoneOp to be performed |
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302 The data pointed to by aParam2 is const and therefore should not be modified |
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303 |
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304 @return KErrNone if successful, otherwise one of the system wide error codes |
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305 |
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306 @see TRamZoneOp |
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307 */ |
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308 typedef TInt (*TRamZoneCallback) (TRamZoneOp aOp, TAny* aParam1, const TAny* aParam2); |
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309 |
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310 /** |
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311 Holds the number of each page type within a RAM zone. |
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312 |
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313 @see Epoc::GetRamZonePageCount() |
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314 |
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315 @publishedPartner |
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316 @released |
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317 */ |
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318 struct SRamZonePageCount |
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319 { |
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320 TUint iFreePages; /**< The number of free pages in the RAM zone*/ |
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321 TUint iUnknownPages; /**< The number of unknown pages in the RAM zone*/ |
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322 TUint iFixedPages; /**< The number of fixed pages in the RAM zone*/ |
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323 TUint iMovablePages; /**< The number of movable pages in the RAM zone*/ |
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324 TUint iDiscardablePages;/**< The number of discardable pages in the RAM zone*/ |
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325 TUint iReserved[4]; /**<@internalComponent reserved for internal use only*/ |
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326 }; |
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327 |
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328 /** |
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329 @publishedPartner |
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330 @released |
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331 */ |
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332 class Epoc |
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333 { |
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334 public: |
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335 /** |
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336 The types of RAM defragmentation operations. |
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337 @internalComponent |
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338 */ |
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339 enum TRamDefragOp |
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340 { |
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341 ERamDefrag_DefragRam, |
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342 ERamDefrag_EmptyRamZone, |
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343 ERamDefrag_ClaimRamZone, |
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344 }; |
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345 |
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346 /** |
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347 The type of page to move with Epoc::MovePhysicalPage(). |
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348 @internalComponent |
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349 */ |
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350 enum TRamDefragPageToMove |
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351 { |
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352 /** |
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353 Move the physical page aOld. |
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354 */ |
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355 ERamDefragPage_Physical, |
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356 /** |
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357 Move the page table page that maps the linear address in the |
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358 current thread at aOld. |
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359 */ |
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360 ERamDefragPage_PageTable, |
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361 /** |
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362 Move the page table info page of the page table that maps the linear |
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363 address in the current thread at aOld. |
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364 */ |
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365 ERamDefragPage_PageTableInfo, |
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366 }; |
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367 |
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368 |
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369 IMPORT_C static void SetMonitorEntryPoint(TDfcFn aFunction); /**< @internalComponent */ |
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370 IMPORT_C static void SetMonitorExceptionHandler(TLinAddr aHandler); /**< @internalComponent */ |
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371 IMPORT_C static TAny* ExceptionInfo(); /**< @internalComponent */ |
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372 IMPORT_C static const TRomHeader& RomHeader(); |
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373 IMPORT_C static TInt AllocShadowPage(TLinAddr aRomAddr); |
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374 IMPORT_C static TInt CopyToShadowMemory(TLinAddr aDest, TLinAddr aSrc, TUint32 aLength); |
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375 IMPORT_C static TInt FreeShadowPage(TLinAddr aRomAddr); |
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376 IMPORT_C static TInt FreezeShadowPage(TLinAddr aRomAddr); |
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377 IMPORT_C static TInt AllocPhysicalRam(TInt aSize, TPhysAddr& aPhysAddr, TInt aAlign=0); |
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378 IMPORT_C static TInt ZoneAllocPhysicalRam(TUint aZoneId, TInt aSize, TPhysAddr& aPhysAddr, TInt aAlign=0); |
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379 IMPORT_C static TInt ZoneAllocPhysicalRam(TUint* aZoneIdList, TUint aZoneIdCount, TInt aSize, TPhysAddr& aPhysAddr, TInt aAlign=0); |
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380 IMPORT_C static TInt AllocPhysicalRam(TInt aNumPages, TPhysAddr* aPageList); |
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381 IMPORT_C static TInt ZoneAllocPhysicalRam(TUint aZoneId, TInt aNumPages, TPhysAddr* aPageList); |
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382 IMPORT_C static TInt ZoneAllocPhysicalRam(TUint* aZoneIdList, TUint aZoneIdCount, TInt aNumPages, TPhysAddr* aPageList); |
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383 IMPORT_C static TInt FreePhysicalRam(TPhysAddr aPhysAddr, TInt aSize); |
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384 IMPORT_C static TInt FreePhysicalRam(TInt aNumPages, TPhysAddr* aPageList); |
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385 IMPORT_C static TInt ClaimPhysicalRam(TPhysAddr aPhysAddr, TInt aSize); |
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386 IMPORT_C static TPhysAddr LinearToPhysical(TLinAddr aLinAddr); |
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387 IMPORT_C static void RomProcessInfo(TProcessCreateInfo& aInfo, const TRomImageHeader& aRomImageHeader); /**< @internalComponent */ |
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388 #ifdef BTRACE_KERNEL_MEMORY |
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389 static TInt DriverAllocdPhysRam; // the number of bytes allocated by Epoc::AllocPhysicalRam and Epoc::FreePhysicalRam |
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390 static TInt KernelMiscPages; // the number of bytes of 'miscelaneous' kernel memory allocated |
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391 #endif |
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392 IMPORT_C static TInt MovePhysicalPage(TPhysAddr aOld, TPhysAddr& aNew, TRamDefragPageToMove aPageToMove=ERamDefragPage_Physical); /**< @internalComponent */ |
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393 IMPORT_C static TInt SetRamZoneConfig(const SRamZone* aZones, TRamZoneCallback aCallback); |
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394 IMPORT_C static TInt GetRamZonePageCount(TUint aId, SRamZonePageCount& aPageData); |
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395 IMPORT_C static TInt ModifyRamZoneFlags(TUint aId, TUint aClearMask, TUint aSetMask); |
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396 }; |
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397 |
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398 /** |
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399 @publishedPartner |
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400 @released |
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401 */ |
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402 class DebugSupport |
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403 { |
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404 public: |
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405 |
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406 /** Bitmask values representing different breakpoint types. */ |
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407 enum TType |
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408 { |
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409 EBreakpointGlobal = 1<<0, /**< Breakpoint appears in all processes */ |
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410 EBreakpointLocal = 1<<1, /**< Breakpoint appears in the specified process only. */ |
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411 }; |
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412 |
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413 IMPORT_C static TInt InitialiseCodeModifier(TUint& aCapabilities, TInt aMinBreakpoints); |
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414 IMPORT_C static void CloseCodeModifier(); |
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415 IMPORT_C static TInt ModifyCode(DThread* aThread, TLinAddr aAddress, TInt aSize, TUint aValue, TUint aType); |
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416 IMPORT_C static TInt RestoreCode(DThread* aThread, TLinAddr aAddress); |
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417 |
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418 /** |
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419 @internalTechnology |
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420 @prototype |
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421 */ |
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422 IMPORT_C static void TerminateProcess(DProcess* aProcess, const TInt aReason); |
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423 |
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424 }; |
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425 |
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426 #ifdef __DEBUGGER_SUPPORT__ |
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427 /** |
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428 @internalComponent |
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429 */ |
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430 class CodeModifier : public DBase |
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431 { |
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432 public: |
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433 |
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434 /** Values for panic values in category 'CodeModifier'. */ |
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435 enum TPanic |
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436 { |
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437 EPanicNotInitialised = 0, |
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438 EPanicInvalidSizeOrAlignment = 1, |
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439 }; |
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440 |
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441 /** Defines the type/size of the breakpoint - see TBreakpoint::iSize*/ |
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442 enum TBrkType |
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443 { |
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444 EEmpty =0, //The slot is unused |
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445 EByte =1, //Jazelle breakpoint |
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446 EHalfword =2, //Thumb breakpoint |
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447 EWord =4 //ARM breakpoint |
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448 }; |
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449 |
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450 TInt static CreateAndInitialise(TInt aMinBreakpoints); |
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451 ~CodeModifier(); |
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452 void Close(); |
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453 TInt Modify(DThread* aThread, TLinAddr aAddress, TInt aSize, TUint aValue); |
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454 TInt Restore(DThread* aThread, TLinAddr aAddress); |
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455 static void CodeSegRemoved(DCodeSeg* aCodeSeg, DProcess* aProcess); |
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456 static DMutex& Mutex() {return *Kern::CodeSegLock();} |
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457 static void Fault(TPanic aPanic); |
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458 |
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459 private: |
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460 |
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461 /**Desribes a breakpoint slot in the pool*/ |
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462 struct TBreakpoint |
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463 { |
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464 TUint iProcessId; //Id of the process associated to this breakpoint. |
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465 TUint iAddress; //The virtual address of the breakpoint |
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466 TUint32 iOldValue; //Will hold the original content of iAddress |
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467 TInt16 iSize; //Could be one of TBrkType. 0 means empty/unused, otherwise it indicates the size of the breakpoint in bytes. |
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468 TInt16 iPageIndex; //If iSize!=0 identifies corresponding shadowed page, or -1 if it is non-XIP page. |
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469 }; |
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470 |
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471 /** Desribes a page slot in the pool. Used for pages that are shadowed or need to be locked (for demand paging). */ |
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472 struct TPageInfo |
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473 { |
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474 TLinAddr iAddress; //Base address of the page. |
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475 TInt32 iCounter; //The number of breakpoints associated with this page. 0 indicates empty slot. |
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476 TBool iWasShadowed; //True if the page had been already shadowed before the first breakpoint was applied, |
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477 //false otherwise. If true, it won't be un-shadowed after all breakpoints are removed. |
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478 #ifdef __DEMAND_PAGING__ |
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479 /// If set, points to the deamnd paging lock object used to lock this page. Only applies to |
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480 /// RAM-loaded code. |
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481 DDemandPagingLock* iPagingLock; |
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482 #endif |
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483 }; |
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484 private: |
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485 TBreakpoint* FindBreakpoint(DThread* aThread, TLinAddr aAddress, TInt aSize, TBool& aOverlap); |
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486 TBreakpoint* FindEmptyBrk(); |
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487 TInt FindEmptyPageInfo(); |
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488 TInt FindPageInfo(TLinAddr aAddress); |
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489 TInt IsRom(TLinAddr aAddress); |
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490 TInt WriteCode(TLinAddr aAddress, TInt aSize, TUint aValue, void* aOldValue); |
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491 DProcess* Process(TUint aProcessId); |
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492 TInt SafeWriteCode(DProcess* aProcess, TLinAddr aAddress, TInt aSize, TUint aValue, void* aOldValue); |
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493 void RestorePage(TInt aPageIndex); |
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494 void DoCodeSegRemoved(DCodeSeg* aCodeSeg, DProcess* aProcess); |
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495 |
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496 private: |
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497 TInt iPoolSize; |
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498 TBreakpoint* iBreakpoints; //Breakpoint pool with iPoolSize slots |
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499 TPageInfo* iPages; //The pool of the shadowed/locked pages with iPoolSize slots |
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500 TUint iPageSize; |
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501 TUint iPageMask; |
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502 }; |
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503 |
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504 GLREF_D CodeModifier* TheCodeModifier; |
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505 #endif //__DEBUGGER_SUPPORT__ |
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506 |
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507 |
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508 /** |
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509 @internalComponent |
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510 */ |
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511 inline const TRomEntry &RomEntry(TLinAddr anAddr) |
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512 {return(*((const TRomEntry *)anAddr));} |
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513 |
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514 /** |
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515 @internalComponent |
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516 */ |
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517 inline const TRomImageHeader& RomImageHeader(TLinAddr anAddr) |
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518 {return(*((const TRomImageHeader*)anAddr));} |
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519 |
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520 /** |
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521 TRamDefragRequest is intended to be used by device drivers to request that RAM defragmentation |
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522 operations are performed. |
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523 |
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524 All RAM defragmentation operations can be invoked synchronously or asynchronously. |
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525 The asynchronous RAM defragmentation operations can use either a TDfc or a NFastSemaphore |
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526 to signal to the caller that the operation has completed. |
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527 |
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528 @see TDfc |
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529 @see NFastSemaphore |
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530 @publishedPartner |
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531 @released |
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532 */ |
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533 class TRamDefragRequest : protected TAsyncRequest |
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534 { |
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535 public: |
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536 IMPORT_C TRamDefragRequest(); |
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537 IMPORT_C TInt DefragRam(TInt aPriority, TInt aMaxPages=0); |
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538 IMPORT_C TInt DefragRam(NFastSemaphore* aSem, TInt aPriority, TInt aMaxPages=0); |
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539 IMPORT_C TInt DefragRam(TDfc* aDfc, TInt aPriority, TInt aMaxPages=0); |
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540 IMPORT_C TInt EmptyRamZone(TUint aId, TInt aPriority); |
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541 IMPORT_C TInt EmptyRamZone(TUint aId, NFastSemaphore* aSem, TInt aPriority); |
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542 IMPORT_C TInt EmptyRamZone(TUint aId, TDfc* aDfc, TInt aPriority); |
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543 IMPORT_C TInt ClaimRamZone(TUint aId, TPhysAddr& aPhysAddr, TInt aPriority); |
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544 IMPORT_C TInt ClaimRamZone(TUint aId, TPhysAddr& aPhysAddr, NFastSemaphore* aSem, TInt aPriority); |
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545 IMPORT_C TInt ClaimRamZone(TUint aId, TPhysAddr& aPhysAddr, TDfc* aDfc, TInt aPriority); |
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546 IMPORT_C TInt Result(); |
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547 IMPORT_C void Cancel(); |
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548 |
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549 /** |
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550 Values that can be specified to control which thread priority |
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551 the RAM defragmentation operations are run with. |
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552 */ |
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553 enum TPrioritySpecial |
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554 { |
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555 /** |
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556 The RAM defragmentation operation will use the same thread priority as |
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557 that of the caller. |
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558 */ |
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559 KInheritPriority = -1, |
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560 }; |
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561 |
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562 private: |
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563 void SetupPriority(TInt aPriority); |
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564 |
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565 private: |
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566 Epoc::TRamDefragOp iOp; |
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567 TUint iId; |
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568 TUint iMaxPages; |
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569 TInt iThreadPriority; |
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570 TPhysAddr* iPhysAddr; |
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571 TInt iSpare[6]; |
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572 |
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573 public: |
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574 friend class Defrag; |
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575 }; |
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576 |
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577 |
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578 #endif |
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579 |