|
1 // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
|
2 // All rights reserved. |
|
3 // This component and the accompanying materials are made available |
|
4 // under the terms of the License "Eclipse Public License v1.0" |
|
5 // which accompanies this distribution, and is available |
|
6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
|
7 // |
|
8 // Initial Contributors: |
|
9 // Nokia Corporation - initial contribution. |
|
10 // |
|
11 // Contributors: |
|
12 // |
|
13 // Description: |
|
14 // e32/include/nkern/arm/entry.h |
|
15 // |
|
16 // |
|
17 |
|
18 extern "C" { |
|
19 |
|
20 extern void __ArmVectorReset(); |
|
21 extern void __ArmVectorUndef(); |
|
22 extern void __ArmVectorSwi(); |
|
23 extern void __ArmVectorAbortPrefetch(); |
|
24 extern void __ArmVectorAbortData(); |
|
25 extern void __ArmVectorReserved(); |
|
26 extern void __ArmVectorIrq(); |
|
27 extern void __ArmVectorFiq(); |
|
28 |
|
29 #define __DECLARE_UNDEFINED_INSTRUCTION_HANDLER asm(".word __ArmVectorUndef ") |
|
30 #define __DECLARE_PREFETCH_ABORT_HANDLER asm(".word __ArmVectorAbortPrefetch ") |
|
31 #define __DECLARE_DATA_ABORT_HANDLER asm(".word __ArmVectorAbortData ") |
|
32 |
|
33 /* NOTE: We must ensure that this code goes at the beginning of the kernel image. |
|
34 */ |
|
35 __NAKED__ void __this_must_go_at_the_beginning_of_the_kernel_image() |
|
36 { |
|
37 asm("ldr pc, __reset_vector "); // 00 = Reset vector |
|
38 asm("ldr pc, __undef_vector "); // 04 = Undefined instruction vector |
|
39 asm("ldr pc, __swi_vector "); // 08 = SWI vector |
|
40 asm("ldr pc, __pabt_vector "); // 0C = Prefetch abort vector |
|
41 asm("ldr pc, __dabt_vector "); // 10 = Data abort vector |
|
42 asm("ldr pc, __unused_vector "); // 14 = unused |
|
43 asm("b HandleIrq "); // 18 = IRQ vector |
|
44 // 1C = FIQ vector, code in situ |
|
45 asm("ldr r12, __ArmInterrupt "); // THIS MUST BE AN IDEMPOTENT INSTRUCTION TO AVOID A PROBLEM WITH XSCALE PXA255 |
|
46 asm("sub lr, lr, #4 "); |
|
47 asm("str lr, [sp, #-4]! "); |
|
48 // we assume FIQ handler preserves r0-r7 but not r8-r12 |
|
49 // hence must be assembler, so stack misalignment OK |
|
50 #if defined(__CPU_ARM_HAS_WORKING_CLREX) |
|
51 CLREX |
|
52 #elif defined(__CPU_ARM_HAS_LDREX_STREX) |
|
53 STREX(8,14, 13); // dummy STREX to reset exclusivity monitor |
|
54 #endif |
|
55 #ifdef __USER_MEMORY_GUARDS_ENABLED__ |
|
56 USER_MEMORY_GUARD_ON(,lr,r8); |
|
57 asm("str lr, [sp, #-4]! "); |
|
58 #endif |
|
59 #ifdef BTRACE_CPU_USAGE |
|
60 asm("ldrb r8, [r12,#%a0]" : : "i" _FOFF(SArmInterruptInfo,iCpuUsageFilter)); |
|
61 asm("ldr lr, _ArmVectorFiq "); |
|
62 asm("mov r10, #%a0" : : "i" ((TInt)(BTrace::ECpuUsage<<BTrace::ECategoryIndex*8)+(BTrace::EFiqStart<<BTrace::ESubCategoryIndex*8)) ); |
|
63 asm("cmp r8,#0"); |
|
64 asm("bne btrace_fiq"); |
|
65 asm("ldr pc, [r12,#%a0]" : : "i" _FOFF(SArmInterruptInfo,iFiqHandler)); // call FIQ handler, return to ArmVectorFiq |
|
66 |
|
67 asm("btrace_fiq:"); // call trace handler before fiq handler... |
|
68 asm("stmdb sp!, {r0-r3} "); |
|
69 asm("add r0, r10, #%a0" : : "i" ((TInt)4) ); // add size of trace into header |
|
70 asm("mov lr, pc"); |
|
71 asm("ldr pc, [r12,#%a0]" : : "i" _FOFF(SArmInterruptInfo,iBTraceHandler)); |
|
72 asm("ldr r12, __ArmInterrupt "); |
|
73 asm("ldmia sp!, {r0-r3} "); |
|
74 #endif |
|
75 asm("ldr lr, _ArmVectorFiq "); |
|
76 asm("ldr pc, [r12,#%a0]" : : "i" _FOFF(SArmInterruptInfo,iFiqHandler)); // call FIQ handler, return to ArmVectorFiq |
|
77 |
|
78 asm("HandleIrq: "); |
|
79 asm("sub lr, lr, #4 "); |
|
80 asm("stmfd sp!, {r0-r3,r12,lr} "); |
|
81 #if defined(__CPU_ARM_HAS_WORKING_CLREX) |
|
82 CLREX |
|
83 #elif defined(__CPU_ARM_HAS_LDREX_STREX) |
|
84 STREX(12, 0, 13); // dummy STREX to reset exclusivity monitor |
|
85 #endif |
|
86 #ifdef __USER_MEMORY_GUARDS_ENABLED__ |
|
87 USER_MEMORY_GUARD_ON(,lr,r12); |
|
88 asm("str lr, [sp, #-8]! "); |
|
89 #endif |
|
90 asm("ldr r12, __ArmInterrupt "); |
|
91 #ifdef BTRACE_CPU_USAGE |
|
92 asm("mov r0, #%a0" : : "i" ((TInt)(BTrace::ECpuUsage<<BTrace::ECategoryIndex*8)+(BTrace::EIrqStart<<BTrace::ESubCategoryIndex*8)) ); |
|
93 asm("add r0, r0, #%a0" : : "i" ((TInt)4) ); // add size of trace into header |
|
94 asm("ldrb r1, [r12,#%a0]" : : "i" _FOFF(SArmInterruptInfo,iCpuUsageFilter)); |
|
95 asm("ldr lr, _ArmVectorIrq "); |
|
96 asm("cmp r1,#0"); |
|
97 asm("bne btrace_irq"); |
|
98 asm("ldr pc, [r12,#%a0]" : : "i" _FOFF(SArmInterruptInfo,iIrqHandler)); // call IRQ handler, return to ArmVectorIrq |
|
99 |
|
100 asm("btrace_irq:"); // call trace handler before irq handler... |
|
101 asm("mov lr, pc"); |
|
102 asm("ldr pc, [r12,#%a0]" : : "i" _FOFF(SArmInterruptInfo,iBTraceHandler)); |
|
103 asm("ldr r12, __ArmInterrupt "); |
|
104 #endif |
|
105 asm("ldr lr, _ArmVectorIrq "); |
|
106 asm("ldr pc, [r12,#%a0]" : : "i" _FOFF(SArmInterruptInfo,iIrqHandler)); // call IRQ handler, return to ArmVectorIrq |
|
107 |
|
108 asm("__reset_vector:"); |
|
109 asm(".word __ArmVectorReset "); |
|
110 asm("__undef_vector:"); |
|
111 __DECLARE_UNDEFINED_INSTRUCTION_HANDLER; |
|
112 asm("__swi_vector:"); |
|
113 asm(".word __ArmVectorSwi "); |
|
114 asm("__pabt_vector:"); |
|
115 __DECLARE_PREFETCH_ABORT_HANDLER; |
|
116 asm("__dabt_vector:"); |
|
117 __DECLARE_DATA_ABORT_HANDLER; |
|
118 asm("__unused_vector:"); |
|
119 asm(".word __ArmVectorReserved "); |
|
120 |
|
121 asm("__ArmInterrupt: "); |
|
122 asm(".word ArmInterruptInfo "); |
|
123 asm("_ArmVectorIrq:"); |
|
124 asm(".word __ArmVectorIrq"); |
|
125 asm("_ArmVectorFiq:"); |
|
126 asm(".word __ArmVectorFiq "); |
|
127 } |
|
128 } |
|
129 |