1 // Copyright (c) 1998-2009 Nokia Corporation and/or its subsidiary(-ies).

     2 // All rights reserved.

     3 // This component and the accompanying materials are made available

     4 // under the terms of the License "Eclipse Public License v1.0"

     5 // which accompanies this distribution, and is available

     6 // at the URL "http://www.eclipse.org/legal/epl-v10.html".

     7 //

     8 // Initial Contributors:

     9 // Nokia Corporation - initial contribution.

    10 //

    11 // Contributors:

    12 //

    13 // Description:

    14 // e32\include\nkern\x86\nk_plat.h

    15 // 

    16 // WARNING: This file contains some APIs which are internal and are subject

    17 //          to change without notice. Such APIs should therefore not be used

    18 //          outside the Kernel and Hardware Services package.

    19 //

    20 

    21 /**

    22  @file

    23  @internalComponent

    24 */

    25 

    26 #ifndef __NK_X86_H__

    27 #define __NK_X86_H__

    28 #include <nk_cpu.h>

    29 

    30 #define IRQ_STACK_SIZE	1024

    31 

    32 //#define __SCHEDULER_MACHINE_CODED__

    33 //#define __DFC_MACHINE_CODED__

    34 //#define __MSTIM_MACHINE_CODED__

    35 //#define __PRI_LIST_MACHINE_CODED__

    36 //#define __FAST_SEM_MACHINE_CODED__

    37 //#define __FAST_MUTEX_MACHINE_CODED__

    38 

    39 // TScheduler member data

    40 #define	i_ExcInfo			iExtras[15]		// pointer to exception info for crash debugger

    41 

    42 class TX86RegSet;

    43 class NThread : public NThreadBase

    44 	{

    45 public:

    46 	TInt Create(SNThreadCreateInfo& anInfo, TBool aInitial);

    47 	inline void Stillborn()

    48 		{}

    49 	void GetUserContext(TX86RegSet& aContext);

    50 	void ModifyUsp(TLinAddr aUsp);

    51 public:

    52 	TUint32	i_NThread_Pad1;

    53 	TUint64	iCoprocessorState[64];	// state of FPU, SSE, SSE2

    54 	};

    55 

    56 __ASSERT_COMPILE(!(_FOFF(NThread,iCoprocessorState)&7));

    57 

    58 // Positions of registers on stack, relative to saved SP

    59 struct SThreadStack

    60 	{

    61 	TUint32 iCR0;

    62 	TUint32 iEbx;

    63 	TUint32 iEsi;

    64 	TUint32 iEdi;

    65 	TUint32 iEbp;

    66 	TUint32 iGs;

    67 	TUint32 iFs;

    68 	TUint32 iReschedFlag;

    69 	TUint32 iEip;

    70 	};

    71 

    72 extern "C" {

    73 GLREF_D TUint32 X86_IrqStack[IRQ_STACK_SIZE/4];

    74 GLREF_D TLinAddr X86_IrqHandler;

    75 GLREF_D TInt X86_IrqNestCount;

    76 GLREF_D SCpuIdleHandler CpuIdleHandler;

    77 GLREF_D TBool X86_UseGlobalPTEs;

    78 GLREF_D TUint64 DefaultCoprocessorState[64];

    79 }

    80 

    81 

    82 /** Ensure the ordering of explicit memory writes

    83 

    84 	On x86 this is a no-op

    85 */

    86 #define	wmb()

    87 #define smp_wmb()

    88 

    89 /** Ensure the ordering of explicit memory accesses

    90 

    91 	On x86 any instruction with the LOCK prefix does this

    92 */

    93 #ifdef __GCC32__

    94 #define	mb()	__asm__ __volatile__("lock add dword ptr [esp], 0" : : : "memory")

    95 #else

    96 #define	mb()	do { _asm lock add dword ptr [esp], 0 } while (0)

    97 #endif

    98 #define smp_mb()

    99 

   100 // End of file

   101 #endif