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1 // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // e32\include\nkernsmp\arm\arm_gic.h |
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15 // Register definitions for ARM Generic Interrupt Controller |
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16 // |
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17 // WARNING: This file contains some APIs which are internal and are subject |
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18 // to change without notice. Such APIs should therefore not be used |
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19 // outside the Kernel and Hardware Services package. |
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20 // |
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21 |
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22 #ifndef __ARM_GIC_H__ |
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23 #define __ARM_GIC_H__ |
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24 #include <e32def.h> |
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25 |
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26 #ifdef __STANDALONE_NANOKERNEL__ |
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27 #undef __IN_KERNEL__ |
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28 #define __IN_KERNEL__ |
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29 #endif |
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30 |
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31 enum TGicIntId |
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32 { |
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33 E_GicIntId_Soft0 =0, // IDs 0-15 are for software triggered IPIs |
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34 E_GicIntId_Soft1 =1, |
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35 E_GicIntId_Soft2 =2, |
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36 E_GicIntId_Soft3 =3, |
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37 E_GicIntId_Soft4 =4, |
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38 E_GicIntId_Soft5 =5, |
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39 E_GicIntId_Soft6 =6, |
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40 E_GicIntId_Soft7 =7, |
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41 E_GicIntId_Soft8 =8, |
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42 E_GicIntId_Soft9 =9, |
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43 E_GicIntId_Soft10 =10, |
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44 E_GicIntId_Soft11 =11, |
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45 E_GicIntId_Soft12 =12, |
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46 E_GicIntId_Soft13 =13, |
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47 E_GicIntId_Soft14 =14, |
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48 E_GicIntId_Soft15 =15, |
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49 |
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50 E_GicIntId_Private0 =16, // IDs 16-31 are for private peripherals |
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51 E_GicIntId_Private1 =17, |
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52 E_GicIntId_Private2 =18, |
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53 E_GicIntId_Private3 =19, |
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54 E_GicIntId_Private4 =20, |
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55 E_GicIntId_Private5 =21, |
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56 E_GicIntId_Private6 =22, |
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57 E_GicIntId_Private7 =23, |
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58 E_GicIntId_Private8 =24, |
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59 E_GicIntId_Private9 =25, |
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60 E_GicIntId_Private10 =26, |
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61 E_GicIntId_Private11 =27, |
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62 E_GicIntId_Private12 =28, |
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63 E_GicIntId_Private13 =29, |
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64 E_GicIntId_Private14 =30, |
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65 E_GicIntId_Private15 =31, |
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66 |
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67 E_GicIntId_Normal0 =32, // first normal interrupt ID |
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68 |
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69 E_GicIntId_NormalLast =1019, // last possible normal interrupt ID |
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70 E_GicIntId_Reserved0 =1020, // reserved interrupt ID |
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71 E_GicIntId_Reserved1 =1021, // reserved interrupt ID |
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72 E_GicIntId_NS =1022, // only nonsecure interrupts are serviceable |
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73 E_GicIntId_Spurious =1023 // no interrupts are serviceable |
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74 }; |
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75 |
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76 struct GicDistributor |
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77 { |
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78 volatile TUint32 iCtrl; // 000 Control register |
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79 volatile TUint32 iType; // 004 Type register |
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80 volatile TUint32 iImpId; // 008 Implementor Identification register (not on MPCore) |
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81 volatile TUint32 i_Skip_1[29]; // 00C unused |
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82 volatile TUint32 iIntSec[32]; // 080 Interrupt Security register (not on MPCore) (1 bit per interrupt) |
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83 volatile TUint32 iEnableSet[32]; // 100 Enable set register (1 bit per interrupt) |
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84 volatile TUint32 iEnableClear[32]; // 180 Enable clear register (1 bit per interrupt) |
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85 volatile TUint32 iPendingSet[32]; // 200 Pending set register (1 bit per interrupt) |
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86 volatile TUint32 iPendingClear[32]; // 280 Pending clear register (1 bit per interrupt) |
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87 volatile TUint32 iActive[32]; // 300 Active status register (1 bit per interrupt) |
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88 volatile TUint32 i_Skip_2[32]; // 380 unused |
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89 volatile TUint32 iPriority[256]; // 400 Interrupt priority register (8 bits per interrupt) |
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90 volatile TUint32 iTarget[256]; // 800 Interrupt target CPUs register (8 bits per interrupt) |
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91 volatile TUint32 iConfig[64]; // C00 Interrupt configuration register (2 bits per interrupt) |
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92 volatile TUint32 iImpDef[64]; // D00 Implementation defined registers |
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93 // = Interrupt line level on MPCore |
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94 volatile TUint32 i_Skip_3[64]; // E00 unused |
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95 volatile TUint32 iSoftIrq; // F00 Software triggered interrupt register |
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96 volatile TUint32 i_Skip_4[51]; // F04 unused |
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97 volatile TUint32 iIdent[12]; // FD0 Identification registers |
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98 }; |
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99 |
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100 __ASSERT_COMPILE(sizeof(GicDistributor)==0x1000); |
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101 |
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102 struct GicCpuIfc |
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103 { |
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104 volatile TUint32 iCtrl; // 00 Control register |
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105 volatile TUint32 iPriMask; // 04 Priority mask register |
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106 volatile TUint32 iBinaryPoint; // 08 Binary point register |
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107 volatile TUint32 iAck; // 0C Interrupt acknowledge register |
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108 volatile TUint32 iEoi; // 10 End of interrupt register |
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109 volatile TUint32 iRunningPri; // 14 Running priority register |
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110 volatile TUint32 iHighestPending; // 18 Highest pending interrupt register |
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111 volatile TUint32 iNSBinaryPoint; // 1C Aliased nonsecure binary point register (not on MPCore) |
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112 volatile TUint32 i_Skip_1[8]; // 20 unused |
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113 volatile TUint32 iImpDef[36]; // 40 Implementation defined (not present on MPCore) |
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114 volatile TUint32 i_Skip_2[11]; // D0 unused |
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115 volatile TUint32 iImpId; // FC Implementor Identification register (not on MPCore) |
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116 }; |
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117 |
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118 __ASSERT_COMPILE(sizeof(GicCpuIfc)==0x100); |
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119 |
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120 enum TGicDistCtrl |
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121 { |
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122 E_GicDistCtrl_Enable =1, // Enable interrupt distributor |
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123 }; |
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124 |
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125 enum TGicDistType |
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126 { |
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127 E_GicDistType_ITShift =0u, // bits 0-4 = number of sets of 32 interrupts supported |
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128 E_GicDistType_ITMask =0x1fu, |
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129 E_GicDistType_CPUNShift =5u, // bits 5-7 = number of CPUs supported - 1 |
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130 E_GicDistType_CPUNMask =0xe0u, |
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131 E_GicDistType_Domains =0x400u, // set if two security domains supported |
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132 E_GicDistType_LSPIShift =11u, // bits 11-15 = number of lockable shared peripheral interrupts |
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133 E_GicDistType_LSPIMask =0xf800u, |
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134 }; |
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135 |
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136 enum TGicDistIntConfig |
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137 { |
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138 E_GicDistICfg1N =1u, // if set use 1-N model else use N-N model |
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139 // peripheral interrupts support only 1-N model, s/w interrupts N-N |
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140 // 1-N means the interrupt is cleared by the first CPU to accept it |
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141 E_GicDistICfgEdge =2u, // if set, rising edge triggered, else active high level triggered |
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142 }; |
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143 |
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144 enum TGicDistSoftIrqDestType |
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145 { |
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146 E_GicDestTypeList =0u, // send to all CPUs in list (bit mask) |
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147 E_GicDestTypeOthers =1u, // send to all CPUs other than self |
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148 E_GicDestTypeSelf =2u, // send to self only |
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149 E_GicDestTypeRsvd =3u |
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150 }; |
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151 |
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152 // Compile word to generate IPI |
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153 // dt = destination type, dl = bit mask of destination CPUs, id = interrupt ID (0-15) |
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154 #define GIC_SOFT_IRQ_WORD(dt,dl,id) ((TUint32(dt)<<24)|(TUint32(dl)<<16)|(TUint32(id))) |
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155 |
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156 #define GIC_IPI_SELF(id) GIC_SOFT_IRQ_WORD(E_GicDestTypeSelf, 0, id) |
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157 #define GIC_IPI_OTHERS(id) GIC_SOFT_IRQ_WORD(E_GicDestTypeOthers, 0, id) |
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158 #define GIC_IPI(dl,id) GIC_SOFT_IRQ_WORD(E_GicDestTypeList, dl, id) |
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159 |
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160 |
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161 #endif // __ARM_GIC_H__ |