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1 // Copyright (c) 2007-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // e32\include\nkernsmp\arm\nk_plat.h |
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15 // |
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16 // WARNING: This file contains some APIs which are internal and are subject |
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17 // to change without notice. Such APIs should therefore not be used |
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18 // outside the Kernel and Hardware Services package. |
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19 // |
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20 |
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21 /** |
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22 @file |
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23 @internalComponent |
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24 */ |
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25 |
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26 #ifndef __NK_ARM_H__ |
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27 #define __NK_ARM_H__ |
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28 #include <nk_cpu.h> |
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29 |
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30 // These macros are intended for Symbian use only. |
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31 // It may not be possible to build the kernel if any of these macros are undefined |
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32 //#define __SCHEDULER_MACHINE_CODED__ |
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33 //#define __DFC_MACHINE_CODED__ |
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34 //#define __MSTIM_MACHINE_CODED__ |
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35 #define __PRI_LIST_MACHINE_CODED__ |
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36 #define __FAST_SEM_MACHINE_CODED__ |
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37 #define __FAST_MUTEX_MACHINE_CODED__ |
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38 #define __NTHREAD_WAITSTATE_MACHINE_CODED__ |
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39 |
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40 // TSubScheduler member data |
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41 #define i_ScuAddr iExtras[4] // Address of SCU (also in TScheduler) |
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42 #define i_GicDistAddr iExtras[5] // Address of GIC Distributor (also in TScheduler) |
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43 #define i_GicCpuIfcAddr iExtras[6] // Address of GIC CPU Interface (also in TScheduler) |
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44 #define i_LocalTimerAddr iExtras[7] // Address of local timer registers (also in TScheduler) |
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45 #define i_IrqCount iExtras[8] // count of interrupts handled |
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46 #define i_IrqNestCount iExtras[9] // IRQ nest count for this CPU (starts at -1) |
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47 #define i_ExcInfo iExtras[10] // pointer to exception info for crash debugger |
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48 #define i_CrashState iExtras[11] // 0=normal, 1=this CPU faulted, 2=this CPU has received an NMI and halted |
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49 #define i_AbtStackTop iExtras[12] // Top of ABT stack for this CPU, also used to point to SFullArmRegSet |
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50 #define i_UndStackTop iExtras[13] // Top of UND stack for this CPU |
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51 #define i_FiqStackTop iExtras[14] // Top of FIQ stack for this CPU |
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52 #define i_IrqStackTop iExtras[15] // Top of IRQ stack for this CPU |
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53 #define i_TimerMultF iExtras[16] // Timer frequency / Max Timer frequency * 2^32 |
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54 #define i_TimerMultI iExtras[17] // Max Timer frequency / Timer frequency * 2^24 |
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55 #define i_CpuMult iExtras[18] // CPU frequency / Max CPU frequency * 2^32 |
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56 #define i_LastTimerSet iExtras[20] // Value last written to local timer counter |
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57 #define i_TimestampError iExtras[21] // Current error in the timestamp |
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58 #define i_MaxCorrection iExtras[22] // Maximum correction to timestamp in one go |
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59 #define i_TimerGap iExtras[23] // Timestamp ticks taken to read and write local timer counter |
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60 |
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61 #define i_Regs iExtras[12] // Alias for i_AbtStackTop |
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62 |
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63 // TScheduler member data |
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64 #define i_TimerMax iExtras[16] // Maximum per-CPU timer frequency (after prescaling) |
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65 |
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66 |
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67 #define RESCHED_IPI_VECTOR 0x00 |
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68 #define GENERIC_IPI_VECTOR 0x01 |
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69 #define TRANSFERRED_IRQ_VECTOR 0x02 |
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70 #define CRASH_IPI_VECTOR 0x03 // would really like this to be a FIQ |
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71 #define BOOT_IPI_VECTOR 0x04 // used during boot to handshake with APs |
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72 #define RESERVED_IPI_VECTOR_1 0x05 // reserved for future kernel functionality |
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73 #define RESERVED_IPI_VECTOR_2 0x06 // reserved for future kernel functionality |
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74 #define RESERVED_IPI_VECTOR_3 0x07 // reserved for future kernel functionality |
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75 |
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76 #if defined(__CPU_ARM11MP__) |
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77 #define TIMESLICE_VECTOR 0x1D // vector 29 is per-CPU timer interrupt |
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78 // vector 30 is per-CPU Watchdog timer when not in watchdog mode |
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79 // vector 31 is external nIRQ local interrupt pin |
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80 #elif defined(__CPU_CORTEX_A9__) |
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81 #define TIMESLICE_VECTOR 0x1D // vector 29 is per-CPU timer interrupt |
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82 // vector 30 is per-CPU Watchdog timer when not in watchdog mode |
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83 #else |
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84 #error TIMESLICE_VECTOR not defined |
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85 #endif |
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86 |
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87 |
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88 //extern "C" TSubScheduler* SubSchedulerLookupTable[256]; // look up subscheduler from APIC ID |
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89 |
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90 const TUint32 KNThreadContextFlagThumbBit0=1; |
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91 |
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92 /** Registers saved by the scheduler |
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93 |
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94 Let's just have the same stack layout for all CPUs shall we? |
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95 TEEHBR, FpExc may not be used but leave space on the stack for them. |
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96 |
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97 @internalComponent |
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98 */ |
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99 struct SThreadReschedStack |
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100 { |
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101 TUint32 iFpExc; // VFP enable |
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102 TUint32 iCar; // coprocessor access register |
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103 TUint32 iTEEHBR; // Thumb2-EE Handler Base |
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104 TUint32 iRWROTID; // User RO Thread ID |
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105 TUint32 iRWRWTID; // User RW Thread ID |
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106 TUint32 iDacr; // domain access control |
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107 TUint32 iSpare; |
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108 TUint32 iSpsrSvc; |
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109 TUint32 iSPRschdFlg; // Stack pointer plus flag indicating reschedule occurred |
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110 TUint32 iR15; // return address from Reschedule() |
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111 }; |
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112 |
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113 /** Registers saved on any exception, interrupt or system call |
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114 |
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115 @internalComponent |
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116 */ |
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117 struct SThreadExcStack |
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118 { |
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119 enum TType |
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120 { |
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121 EPrefetch =0, // prefetch abort |
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122 EData =1, // data abort |
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123 EUndef =2, // undefined instruction |
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124 EIrq =3, // IRQ interrupt |
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125 EFiq =4, // FIQ interrupt |
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126 ESvc =5, // SWI |
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127 EInit =6, // Thread has never run |
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128 EStub =7, // Stub indicating parameter block still on stack |
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129 }; |
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130 |
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131 TUint32 iR0; |
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132 TUint32 iR1; |
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133 TUint32 iR2; |
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134 TUint32 iR3; |
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135 TUint32 iR4; |
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136 TUint32 iR5; |
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137 TUint32 iR6; |
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138 TUint32 iR7; |
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139 TUint32 iR8; |
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140 TUint32 iR9; |
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141 TUint32 iR10; |
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142 TUint32 iR11; |
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143 TUint32 iR12; |
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144 TUint32 iR13usr; // always user mode R13 |
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145 TUint32 iR14usr; // always user mode R14 |
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146 TUint32 iExcCode; |
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147 TUint32 iR15; // return address |
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148 TUint32 iCPSR; // return CPSR |
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149 }; |
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150 |
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151 /** |
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152 @internalComponent |
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153 */ |
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154 struct SThreadStackStub |
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155 { |
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156 TLinAddr iPBlock; // pointer to parameter block |
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157 TUint32 iExcCode; // always EStub |
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158 TUint32 iR15; // unused |
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159 TUint32 iCPSR; // unused |
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160 }; |
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161 |
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162 /** |
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163 @internalComponent |
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164 */ |
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165 struct SThreadInitStack |
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166 { |
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167 SThreadReschedStack iR; |
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168 SThreadExcStack iX; |
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169 }; |
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170 |
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171 |
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172 /** |
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173 @internalComponent |
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174 */ |
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175 struct SThreadIrqStack |
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176 { |
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177 SThreadReschedStack iR; |
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178 TUint32 iUMGSave; // User memory guard state (if active) |
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179 TUint32 iR14svc; |
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180 SThreadExcStack iX; |
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181 }; |
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182 |
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183 |
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184 class TArmContextElement; |
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185 class TArmRegSet; |
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186 |
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187 /** ARM-specific part of the nano-thread abstraction. |
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188 @internalComponent |
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189 */ |
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190 class NThread : public NThreadBase |
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191 { |
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192 public: |
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193 TInt Create(SNThreadCreateInfo& aInfo, TBool aInitial); |
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194 inline void Stillborn() |
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195 {} |
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196 |
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197 /** Value indicating what event caused thread to enter privileged mode. |
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198 @publishedPartner |
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199 @released |
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200 */ |
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201 enum TUserContextType |
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202 { |
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203 EContextNone=0, /**< Thread has no user context */ |
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204 EContextException=1, /**< Hardware exception while in user mode */ |
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205 EContextUndefined, |
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206 EContextUserInterrupt, /**< Preempted by interrupt taken in user mode */ |
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207 EContextUserInterruptDied, /**< Killed while preempted by interrupt taken in user mode */ // NOT USED |
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208 EContextSvsrInterrupt1, /**< Preempted by interrupt taken in executive call handler */ |
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209 EContextSvsrInterrupt1Died, /**< Killed while preempted by interrupt taken in executive call handler */ // NOT USED |
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210 EContextSvsrInterrupt2, /**< Preempted by interrupt taken in executive call handler */ // NOT USED |
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211 EContextSvsrInterrupt2Died, /**< Killed while preempted by interrupt taken in executive call handler */ // NOT USED |
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212 EContextWFAR, /**< Blocked on User::WaitForAnyRequest() */ |
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213 EContextWFARDied, /**< Killed while blocked on User::WaitForAnyRequest() */ // NOT USED |
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214 EContextExec, /**< Slow executive call */ |
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215 EContextKernel, /**< Kernel side context (for kernel threads) */ |
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216 EContextKernel1, /**< Kernel side context (for kernel threads) (NKern::Unlock, NKern::PreemptionPoint) */ |
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217 EContextKernel2, /**< Kernel side context (for kernel threads) (NKern::FSWait, NKern::WaitForAnyRequest) */ |
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218 EContextKernel3, /**< Kernel side context (for kernel threads) (Interrupt) */ |
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219 EContextKernel4, /**< Kernel side context (for kernel threads) (Exec::WaitForAnyRequest) */ |
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220 }; |
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221 |
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222 IMPORT_C static const TArmContextElement* const* UserContextTables(); |
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223 IMPORT_C TUserContextType UserContextType(); |
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224 void GetUserContext(TArmRegSet& aContext, TUint32& aAvailRegistersMask); |
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225 void SetUserContext(const TArmRegSet& aContext, TUint32& aRegMask); |
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226 void GetSystemContext(TArmRegSet& aContext, TUint32& aAvailRegistersMask); |
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227 |
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228 TUint32 Dacr(); |
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229 void SetDacr(TUint32 aDacr); |
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230 TUint32 ModifyDacr(TUint32 aClearMask, TUint32 aSetMask); |
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231 |
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232 void SetCar(TUint32 aDacr); |
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233 IMPORT_C TUint32 Car(); |
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234 IMPORT_C TUint32 ModifyCar(TUint32 aClearMask, TUint32 aSetMask); |
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235 |
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236 #ifdef __CPU_HAS_VFP |
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237 void SetFpExc(TUint32 aDacr); |
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238 #endif |
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239 IMPORT_C TUint32 FpExc(); |
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240 IMPORT_C TUint32 ModifyFpExc(TUint32 aClearMask, TUint32 aSetMask); |
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241 |
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242 void CompleteContextSave(); |
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243 }; |
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244 |
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245 |
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246 struct SArmInterruptInfo |
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247 { |
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248 TLinAddr iIrqHandler; |
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249 TLinAddr iFiqHandler; |
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250 SCpuIdleHandler iCpuIdleHandler; |
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251 }; |
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252 |
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253 extern "C" SArmInterruptInfo ArmInterruptInfo; |
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254 |
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255 #if defined(__ARMCC__) |
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256 #ifndef __CIA__ |
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257 inline void mb() |
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258 { |
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259 TUint32 reg = 0; |
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260 asm("mcr p15, 0, reg, c7, c10, 5 "); |
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261 } |
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262 |
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263 inline void arm_dsb() |
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264 { |
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265 TUint32 reg = 0; |
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266 asm("mcr p15, 0, reg, c7, c10, 4 "); |
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267 } |
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268 |
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269 inline void arm_isb() |
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270 { |
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271 TUint32 reg = 0; |
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272 asm("mcr p15, 0, reg, c7, c5, 4 "); |
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273 } |
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274 #endif |
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275 #elif defined(__GNUC__) || defined(__GCC32__) |
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276 #define mb() \ |
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277 do { \ |
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278 TUint32 reg = 0; \ |
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279 __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 5" : : "r"(reg) : "memory"); \ |
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280 } while(0) |
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281 |
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282 #define arm_dsb() \ |
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283 do { \ |
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284 TUint32 reg = 0; \ |
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285 __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" : : "r"(reg) : "memory"); \ |
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286 } while(0) |
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287 |
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288 #define arm_isb() \ |
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289 do { \ |
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290 TUint32 reg = 0; \ |
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291 __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 4" : : "r"(reg) : "memory"); \ |
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292 } while(0) |
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293 #else |
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294 #error Unknown ARM compiler |
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295 #endif |
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296 |
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297 #define smp_mb() mb() |
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298 #define wmb() mb() |
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299 #define smp_wmb() mb() |
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300 |
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301 #ifdef __IN_KERNEL__ |
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302 struct ArmScu; |
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303 struct GicDistributor; |
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304 struct GicCpuIfc; |
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305 struct ArmLocalTimer; |
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306 #define SCU (*(ArmScu*)TheScheduler.i_ScuAddr) |
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307 #define GIC_DIST (*(GicDistributor*)TheScheduler.i_GicDistAddr) |
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308 #define GIC_CPU_IFC (*(GicCpuIfc*)TheScheduler.i_GicCpuIfcAddr) |
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309 #define LOCAL_TIMER (*(ArmLocalTimer*)TheScheduler.i_LocalTimerAddr) |
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310 #endif |
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311 |
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312 |
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313 // End of file |
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314 #endif |