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1 // Copyright (c) 1997-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // e32\memmodel\epoc\moving\arm\xmmu.cia |
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15 // |
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16 // |
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17 |
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18 #include <e32cia.h> |
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19 #include <arm_mem.h> |
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20 #include "execs.h" |
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21 #include "cache_maintenance.h" |
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22 |
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23 __NAKED__ void InvalidateTLBForPage(TLinAddr /*aLinAddr*/) |
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24 // |
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25 // Flush a specified virtual address from the DTLB. |
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26 // Flush from the ITLB as well, provided that doesn't require flushing the whole ITLB |
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27 // ArmMmu::SyncCodeMappings() should follow this if flushing from the ITLB is essential. |
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28 // |
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29 { |
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30 #ifdef __CPU_SPLIT_TLB |
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31 #if defined(__CPU_HAS_SINGLE_ENTRY_IDTLB_FLUSH) |
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32 FLUSH_IDTLB_ENTRY(,r0); |
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33 #elif defined(__CPU_HAS_SINGLE_ENTRY_ITLB_FLUSH) |
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34 FLUSH_DTLB_ENTRY(,r0); |
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35 FLUSH_ITLB_ENTRY(,r0); |
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36 #else |
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37 FLUSH_DTLB_ENTRY(,r0); |
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38 #endif |
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39 #else |
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40 FLUSH_IDTLB_ENTRY(,r0); |
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41 #endif |
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42 // don't need CPWAIT since it always happens in the function which calls this one |
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43 __JUMP(,lr); |
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44 } |
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45 |
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46 __NAKED__ void ArmMmu::SyncCodeMappings() |
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47 // |
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48 // Flush the ITLB if it is not flushed page-by-page during unmapping of pages |
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49 // |
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50 { |
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51 #if defined(__CPU_SPLIT_TLB) && !defined(__CPU_HAS_SINGLE_ENTRY_ITLB_FLUSH) && !defined(__CPU_HAS_SINGLE_ENTRY_IDTLB_FLUSH) |
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52 asm("mov r2, #0 "); |
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53 FLUSH_ITLB(,r2); |
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54 CPWAIT(,r0); |
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55 #endif |
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56 __JUMP(,lr); |
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57 } |
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58 |
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59 __NAKED__ void FlushTLBs() |
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60 { |
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61 asm("mov r0, #0 "); |
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62 FLUSH_IDTLB(,r0); |
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63 CPWAIT(,r0); |
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64 __JUMP(,lr); |
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65 } |
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66 |
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67 __NAKED__ void FlushUnmapShadow(TLinAddr /*aRomAddr*/) |
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68 // |
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69 // Flush both I and D TLBs and flush page at aRomAddr from both caches |
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70 // |
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71 { |
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72 asm("mov r0, #0 "); |
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73 FLUSH_IDTLB(,r0); // flush both TLBs |
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74 CPWAIT(,r0); |
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75 __JUMP(,lr); |
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76 } |
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77 |
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78 // Generic cache/TLB flush function. |
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79 // Which things are flushed is determined by aMask. |
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80 // Call this with the system locked. Preemption can occur during this function. |
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81 __NAKED__ void ArmMmu::GenericFlush(TUint32 /*aMask*/) |
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82 { |
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83 asm("tst r1, #%a0" : : "i" (EFlushDMove|EFlushDDecommit)); |
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84 asm("orrne r1, r1, #%a0" : : "i" (EFlushDCache)); |
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85 asm("tst r1, #%a0" : : "i" (EFlushDMove|EFlushDDecommit|EFlushDPermChg)); |
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86 asm("orrne r1, r1, #%a0" : : "i" (EFlushDTLB)); |
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87 asm("tst r1, #%a0" : : "i" (EFlushIMove)); |
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88 asm("orrne r1, r1, #%a0" : : "i" (EFlushICache)); |
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89 asm("tst r1, #%a0" : : "i" (EFlushIMove|EFlushIPermChg)); |
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90 asm("orrne r1, r1, #%a0" : : "i" (EFlushITLB)); |
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91 asm("mov r2, #0 "); |
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92 #ifdef __CPU_SPLIT_CACHE |
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93 asm("tst r1, #%a0" : : "i" (EFlushDCache) ); |
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94 #else |
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95 asm("tst r1, #%a0" : : "i" (EFlushDCache|EFlushICache) ); |
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96 #endif |
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97 asm("beq 1f "); |
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98 asm("stmfd sp!, {r1,lr} "); |
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99 asm("bl " CSM_ZN16CacheMaintenance15OnProcessSwitchEv); // flush data or unified cache |
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100 asm("ldmfd sp!, {r1,lr} "); |
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101 asm("mov r2, #0 "); |
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102 asm("1: "); |
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103 |
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104 #ifdef __CPU_SPLIT_CACHE |
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105 asm("tst r1, #%a0" : : "i" (EFlushICache) ); |
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106 FLUSH_ICACHE(ne,r2); |
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107 #endif |
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108 |
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109 #ifdef __CPU_SPLIT_TLB |
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110 asm("tst r1, #%a0" : : "i" (EFlushDTLB) ); |
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111 FLUSH_DTLB(ne,r2); |
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112 asm("tst r1, #%a0" : : "i" (EFlushITLB) ); |
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113 FLUSH_ITLB(ne,r2); |
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114 #else |
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115 asm("tst r1, #%a0" : : "i" (EFlushDTLB|EFlushITLB) ); |
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116 FLUSH_IDTLB(ne,r2); |
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117 #endif |
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118 CPWAIT(,r0); |
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119 __JUMP(,lr); |
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120 } |
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121 |
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122 #if defined(__CPU_XSCALE__) |
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123 // Special routine to process minicache attributes |
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124 __NAKED__ TUint MiniCacheConfig() |
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125 { |
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126 asm("mrc p15, 0, r0, c1, c0, 1 "); |
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127 #if defined (__CPU_XSCALE_MANZANO__) |
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128 asm("and r0, r0, #0x30 "); // 00=WBRA 01=WBRA 10=WTRA 11=WBRA |
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129 asm("cmp r0, #0x20"); //is it WTRA? |
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130 asm("moveq r0, #8"); // yes |
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131 asm("movne r0, #10"); // no |
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132 #else |
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133 asm("mov r0, r0, lsr #4 "); |
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134 asm("and r0, r0, #3 "); // 00=WBRA 01=WBWA 10=WTRA 11=UNP |
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135 asm("bic r0, r0, #2 "); // 10=WBRA 11=WBWA 00=WTRA 01=UNP |
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136 asm("add r0, r0, #8 "); // WBRA->AWBR, WBWA->AWBW, WTRA->AWTR, UNP->AWTW (can't occur) |
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137 #endif |
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138 __JUMP(,lr); |
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139 } |
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140 #endif |
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141 |
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142 __NAKED__ void ExecHandler::UnlockRamDrive() |
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143 { |
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144 asm("ldr r0, [r1, #%a0]" : : "i" (_FOFF(DThread,iOwningProcess)-_FOFF(DThread,iNThread))); |
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145 asm("ldr r0, [r0, #%a0]" : : "i" _FOFF(DProcess,iS.iCaps)); |
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146 // __KERNEL_CAPABILITY_CHECK |
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147 asm("tst r0, #%a0 " : : "i" ((TInt)(1<<ECapabilityTCB))); |
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148 __JUMP(eq,lr); // don't unlock the RAM drive if don't have MediaDD capability |
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149 |
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150 // fall through to unlock |
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151 } |
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152 |
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153 EXPORT_C __NAKED__ void TInternalRamDrive::Unlock() |
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154 { |
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155 asm("mrc p15, 0, r0, c3, c0, 0 "); |
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156 asm("orr r0, r0, #0xc0 "); |
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157 asm("mcr p15, 0, r0, c3, c0, 0 "); |
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158 CPWAIT(,r0); |
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159 __JUMP(,lr); |
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160 } |
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161 |
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162 EXPORT_C __NAKED__ void TInternalRamDrive::Lock() |
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163 { |
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164 asm("mrc p15, 0, r0, c3, c0, 0 "); |
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165 asm("bic r0, r0, #0xc0 "); |
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166 asm("mcr p15, 0, r0, c3, c0, 0 "); |
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167 CPWAIT(,r0); |
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168 __JUMP(,lr); |
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169 } |
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170 |
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171 #if defined(__CPU_WRITE_BACK_CACHE) |
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172 #if defined(__CPU_HAS_SINGLE_ENTRY_DCACHE_FLUSH) |
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173 __NAKED__ void CopyPageForRemap32(TLinAddr /*aDest*/, TLinAddr /*aSrc*/) |
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174 { |
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175 // Source and destination 4k page aligned (and thus cache aligned) |
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176 // Fixed copy size of 4k |
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177 // But.. after each cache line we need to purge the line from the cache |
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178 // and when we're done we need to drain the write buffer |
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179 // We are assuming 32-byte cache lines here but this function is only used |
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180 // when this is the case, so it's ok. |
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181 |
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182 asm("stmfd sp!, {r4-r9} "); |
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183 asm("1: "); |
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184 PLD_ioff(1, 32); |
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185 asm("mov ip, r1 "); |
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186 asm("ldmia r1!, {r2-r9} "); |
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187 asm("tst r1, #0xff0 "); |
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188 asm("stmia r0!, {r2-r9} "); |
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189 PURGE_DCACHE_LINE(,ip); |
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190 asm("bne 1b "); |
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191 asm("ldmfd sp!, {r4-r9} "); |
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192 DRAIN_WRITE_BUFFER(,r0,r1); |
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193 CPWAIT(,r0); |
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194 __JUMP(,lr); |
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195 } |
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196 |
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197 __NAKED__ void CopyPageForRemap16(TLinAddr /*aDest*/, TLinAddr /*aSrc*/) |
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198 { |
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199 // Source and destination 4k page aligned (and thus cache aligned) |
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200 // Fixed copy size of 4k |
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201 // But.. after each cache line we need to purge the line from the cache |
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202 // and when we're done we need to drain the write buffer |
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203 // We are assuming 16-byte cache lines here but this function is only used |
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204 // when this is the case, so it's ok. |
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205 |
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206 asm("stmfd sp!, {r4-r5} "); |
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207 asm("1: "); |
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208 PLD_ioff(1, 16); |
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209 asm("mov ip, r1 "); |
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210 asm("ldmia r1!, {r2-r5} "); |
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211 asm("tst r1, #0xff0 "); |
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212 asm("stmia r0!, {r2-r5} "); |
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213 PURGE_DCACHE_LINE(,ip); |
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214 asm("bne 1b "); |
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215 asm("ldmfd sp!, {r4-r5} "); |
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216 DRAIN_WRITE_BUFFER(,r0,r1); |
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217 CPWAIT(,r0); |
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218 __JUMP(,lr); |
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219 } |
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220 #endif |
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221 #else //!__CPU_HAS_WRITE_BACK_CACHE |
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222 __NAKED__ void CopyPageForRemapWT(TLinAddr /*aDest*/, TLinAddr /*aSrc*/) |
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223 { |
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224 // Source and destination 4k page aligned (and thus cache aligned) |
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225 // Fixed copy size of 4k |
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226 // Writethrough cache means no purging is required, but |
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227 // when we're done we still need to drain the write buffer |
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228 |
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229 asm("stmfd sp!, {r4-r8} "); |
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230 asm("1: "); |
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231 PLD_ioff(1, 16); |
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232 asm("ldmia r1!, {r2-r8,ip} "); |
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233 asm("tst r1, #0xff0 "); |
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234 asm("stmia r0!, {r2-r8,ip} "); |
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235 asm("bne 1b "); |
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236 asm("ldmfd sp!, {r4-r8,ip} "); |
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237 DRAIN_WRITE_BUFFER(,r0,r1); |
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238 CPWAIT(,r0); |
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239 __JUMP(,lr); |
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240 } |
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241 #endif |
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242 |
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243 #ifdef __MMU_MACHINE_CODED__ |
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244 __NAKED__ void ImpMmu::MapRamPages(TInt /*anId*/, TLinAddr /*anAddr*/, TPhysAddr* /*aPageList*/, TInt /*aNumPages*/, TPte /*aPtePerm*/) |
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245 // |
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246 // Map a list of physical RAM pages to a specified linear address using a specified page table and |
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247 // specified PTE permissions. Call this with the kernel locked. |
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248 // |
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249 { |
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250 // enter with r0=&MM::TheMmu, r1=anId, r2=anAddr, r3=aPageList, [sp]=aNumPages, [sp+4]=aPtePerm |
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251 asm("stmfd sp!, {r4-r6,lr} "); |
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252 asm("mov r4, r1 "); // r4=anId |
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253 asm("mov r5, r2 "); // r5=anAddr |
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254 asm("mov r6, r3 "); // r6=aPageList |
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255 asm("bl " CSM_ZN6ImpMmu16UnlockPageTablesEv); // unlock page tables |
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256 asm("mov r0, r5, lsr #20 "); // r0=pdeIndex |
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257 asm("bic r1, r5, r0, lsl #20 "); // r1=anAddr & 0xfffff |
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258 asm("and r1, r1, #0xff000 "); // r1=ptOffset<<12 |
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259 asm("mov r4, r4, lsl #10 "); |
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260 asm("add r4, r4, #%a0" : : "i" ((TInt)KPageTableLinearBase)); // r4=linear address of page table anId |
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261 asm("add r1, r4, r1, lsr #10 "); // r1 points to first PTE to add |
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262 asm("ldr r2, [sp, #16] "); // r2=number of pages to map |
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263 asm("mov r0, r0, lsl #2 "); |
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264 asm("add r0, r0, #%a0" : : "i" ((TInt)KPageDirectoryLinearAddress)); |
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265 asm("add r0, r0, #%a0" : : "i" ((TInt)KPageTableInfoOffset)); // r0->page table info entry for anAddr |
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266 asm("ldr r3, [r0] "); |
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267 asm("add r3, r3, r2 "); // add number of pages to pages present count |
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268 asm("str r3, [r0] "); |
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269 asm("ldr r3, [sp, #20] "); // r3=PTE permissions |
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270 asm("b map_ram_pages2 "); |
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271 |
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272 asm("map_ram_pages1: "); |
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273 asm("ldr lr, [r6], #4 "); // get physical address of page and step to next in list |
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274 asm("orr lr, lr, r3 "); // OR in permissions to give PTE |
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275 asm("str lr, [r1], #4 "); // store PTE and step to next |
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276 |
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277 asm("map_ram_pages2: "); |
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278 asm("subs r2, r2, #1 "); |
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279 asm("bge map_ram_pages1 "); // loop for all pages |
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280 asm("ldmfd sp!, {r4-r6,lr} "); |
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281 DRAIN_WRITE_BUFFER(,r0,r0); |
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282 CPWAIT(,r0); |
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283 asm("b " CSM_ZN6ImpMmu14LockPageTablesEv); // lock page tables and exit |
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284 } |
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285 |
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286 __NAKED__ void ImpMmu::MapPhysicalPages(TInt /*anId*/, TLinAddr /*anAddr*/, TPhysAddr /*aPhysAddr*/, TInt /*aNumPages*/, TPte /*aPtePerm*/) |
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287 // |
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288 // Map consecutive physical pages to a specified linear address using a specified page table and |
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289 // specified PTE permissions. Call this with the kernel locked. |
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290 // |
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291 { |
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292 // enter with r0=&MM::TheMmu, r1=anId, r2=anAddr, r3=aPhysAddr, [sp]=aNumPages, [sp+4]=aPtePerm |
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293 asm("stmfd sp!, {r4-r6,lr} "); |
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294 asm("mov r4, r1 "); // r4=anId |
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295 asm("mov r5, r2 "); // r5=anAddr |
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296 asm("mov r6, r3 "); // r6=aPhysAddr |
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297 asm("bl " CSM_ZN6ImpMmu16UnlockPageTablesEv); // unlock page tables |
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298 asm("mov r0, r5, lsr #20 "); // r0=pdeIndex |
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299 asm("bic r1, r5, r0, lsl #20 "); // r1=anAddr & 0xfffff |
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300 asm("and r1, r1, #0xff000 "); // r1=ptOffset<<12 |
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301 asm("mov r4, r4, lsl #10 "); |
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302 asm("add r4, r4, #%a0" : : "i" ((TInt)KPageTableLinearBase)); // r4=linear address of page table anId |
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303 asm("add r1, r4, r1, lsr #10 "); // r1 points to first PTE to add |
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304 asm("ldr r2, [sp, #16] "); // r2=number of pages to map |
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305 asm("mov r0, r0, lsl #2 "); |
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306 asm("add r0, r0, #%a0" : : "i" ((TInt)KPageDirectoryLinearAddress)); |
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307 asm("add r0, r0, #%a0" : : "i" ((TInt)KPageTableInfoOffset)); // r0->page table info entry for anAddr |
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308 asm("ldr r3, [r0] "); |
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309 asm("add r3, r3, r2 "); // add number of pages to pages present count |
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310 asm("str r3, [r0] "); |
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311 asm("ldr r3, [sp, #20] "); // r3=PTE permissions |
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312 asm("orr r3, r3, r6 "); // OR in physical address to give first PTE |
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313 asm("b map_phys_pages2 "); |
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314 |
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315 asm("map_phys_pages1: "); |
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316 asm("str r3, [r1], #4 "); // store PTE and step to next |
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317 asm("add r3, r3, #0x1000 "); // step physical address on by page size |
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318 |
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319 asm("map_phys_pages2: "); |
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320 asm("subs r2, r2, #1 "); |
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321 asm("bge map_phys_pages1 "); // loop for all pages |
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322 asm("ldmfd sp!, {r4-r6,lr} "); |
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323 DRAIN_WRITE_BUFFER(,r0,r0); |
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324 CPWAIT(,r0); |
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325 asm("b " CSM_ZN6ImpMmu14LockPageTablesEv); // lock page tables and exit |
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326 } |
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327 |
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328 __NAKED__ TInt ImpMmu::UnmapPages(TInt /*anId*/, TLinAddr /*anAddr*/, TInt /*aNumPages*/, TPhysAddr* /*aPageList*/, TInt& /*aNumPtes*/) |
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329 // |
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330 // Unmap a specified area at address anAddr mapped by page table anId. Place physical addresses of unmapped |
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331 // RAM pages into aPageList and count of unmapped pages into aNumPtes. Return number of pages still |
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332 // mapped using this page table. Call this with the kernel locked. |
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333 // Note that a write-back cache may also require flushing after this. |
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334 // |
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335 { |
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336 // Enter with r0=this, r1=anId, r2=anAddr, r3=aNumPages, [sp]=aPageList, [sp+4]=&aNumPtes |
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337 asm("stmfd sp!, {r4-r9,lr} "); |
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338 asm("mov r4, r0 "); |
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339 asm("mov r5, r1 "); |
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340 asm("mov r6, r2 "); |
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341 asm("mov r7, r3 "); |
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342 asm("bl " CSM_ZN6ImpMmu16UnlockPageTablesEv); // unlock the page tables |
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343 asm("mov r8, r6, lsr #20 "); // r8=pdeIndex |
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344 asm("bic r0, r6, r8, lsl #20 "); // r0=anAddr&0xfffff |
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345 asm("and r0, r0, #0xff000 "); // r0=ptOffset<<12 |
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346 asm("mov r5, r5, lsl #10 "); // convert page table id to linear address |
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347 asm("add r5, r5, r0, lsr #10 "); // add offset within page table |
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348 asm("add r5, r5, #%a0" : : "i" ((TInt)KPageTableLinearBase)); // r5=pte address |
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349 asm("mov ip, #0 "); // ip=0 throughout loop |
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350 asm("mov r3, #0 "); // r3 counts present pages |
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351 asm("ldr r9, [sp, #28] "); // r9=aPageList |
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352 asm("mov r2, #0xff "); |
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353 asm("orr r2, r2, #0xf00 "); // r2=BIC mask for PTE->page physical address |
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354 asm("b unmap_pages_2 "); |
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355 |
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356 asm("unmap_pages_1: "); |
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357 asm("ldr r0, [r5] "); // fetch PTE |
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358 asm("str ip, [r5], #4 "); // clear PTE |
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359 asm("tst r0, #3 "); // test if page present |
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360 #ifdef __CPU_SPLIT_TLB |
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361 #if defined(__CPU_HAS_SINGLE_ENTRY_IDTLB_FLUSH) |
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362 FLUSH_IDTLB_ENTRY(ne,r6); // flush page from both TLBs if possible |
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363 #elif defined(__CPU_HAS_SINGLE_ENTRY_ITLB_FLUSH) |
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364 FLUSH_DTLB_ENTRY(ne,r6); |
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365 FLUSH_ITLB_ENTRY(ne,r6); |
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366 #else |
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367 FLUSH_DTLB_ENTRY(ne,r6); // no single-entry ITLB flush, complete ITLB flush will be done later |
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368 #endif |
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369 #else |
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370 FLUSH_IDTLB_ENTRY(ne,r6); |
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371 #endif |
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372 asm("bicne r0, r0, r2 "); // ... r0=page physical address ... |
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373 asm("strne r0, [r9], #4 "); // ... *aPageList++=r0 ... |
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374 asm("addne r3, r3, #1 "); // ... increment present pages count |
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375 asm("add r6, r6, #0x1000 "); // increment address by page size |
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376 |
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377 asm("unmap_pages_2: "); |
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378 asm("subs r7, r7, #1 "); // decrement page count |
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379 asm("bge unmap_pages_1 "); |
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380 |
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381 asm("ldr r0, [sp, #32] "); // r0=&aNumPtes |
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382 asm("str r3, [r0] "); // aNumPtes=r3 |
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383 asm("mov r0, #%a0" : : "i" ((TInt)KPageDirectoryLinearAddress)); |
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384 asm("add r0, r0, #%a0" : : "i" ((TInt)KPageTableInfoOffset)); // r0->base of page table info array |
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385 asm("add r0, r0, r8, lsl #2 "); // r0 points to PTINFO entry for this pde |
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386 asm("ldr r1, [r0] "); // r1[31:16]=page table id, r1[15:0]=present pages |
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387 asm("sub r1, r1, r3 "); // subtract number of pages unmapped |
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388 asm("str r1, [r0] "); // store new pages present count |
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389 asm("mov r4, r1, lsl #16 "); // shift out top 16 bits and store in r4 |
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390 asm("bl " CSM_ZN6ImpMmu14LockPageTablesEv); // lock the page tables |
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391 asm("mov r0, r4, lsr #16 "); // r0=number of pages remaining |
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392 DRAIN_WRITE_BUFFER(,r0,r1); |
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393 CPWAIT(,r1); |
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394 asm("ldmfd sp!, {r4-r9,pc} "); // restore registers and return |
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395 } |
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396 |
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397 __NAKED__ TInt Mmu::PageTableId(TLinAddr /*anAddr*/) |
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398 { |
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399 asm("mov r1, r1, lsr #20 "); // r1=anAddr>>20 |
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400 asm("mov r0, #%a0" : : "i" ((TInt)KPageDirectoryLinearAddress)); |
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401 asm("add r0, r0, #%a0" : : "i" ((TInt)KPageTableInfoOffset)); // r0->base of page table info array |
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402 asm("mrc p15, 0, r2, c3, c0, 0 "); // r2=current DACR |
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403 asm("orr r3, r2, #0x30 "); |
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404 asm("mcr p15, 0, r3, c3, c0, 0 "); // unlock page tables |
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405 CPWAIT(,r3); |
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406 asm("ldr r0, [r0, r1, lsl #2] "); // fetch page table info entry for anAddr |
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407 asm("mcr p15, 0, r2, c3, c0, 0 "); // lock page tables |
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408 asm("cmn r0, #0x10000 "); // test if page table id=0xffff |
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409 asm("movcc r0, r0, lsr #16 "); // if not, return page table id |
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410 asm("mvncs r0, #0 "); // else return -1 |
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411 __JUMP(,lr); |
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412 } |
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413 |
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414 __NAKED__ void ImpMmu::AssignPageTable(TInt /*anId*/, TLinAddr /*anAddr*/, TPde /*aPdePerm*/) |
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415 // |
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416 // Assign an allocated page table to map a given linear address with specified permissions. |
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417 // This function assumes the page table initially contains no physical RAM page mappings. |
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418 // This should be called with the kernel locked. |
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419 // |
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420 { |
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421 // on entry r0=&MM::TheMmu, r1=anId, r2=anAddr, r3=aPdePerm |
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422 asm("stmfd sp!, {r4,lr} "); |
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423 asm("and r4, r1, #3 "); // r4=bottom 2 bits of anId (offset of page table within page) |
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424 asm("orr r3, r3, r4, lsl #10 "); // combine these bits with PDE permissions |
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425 asm("bic r0, r1, #3 "); // r0=anId with bottom 2 bits cleared |
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426 asm("add r0, r0, #%a0" : : "i" ((TInt)KPageTableLinearBase)); // r0=address of PTE mapping page table anId |
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427 asm("mov r1, r1, lsl #16 "); // put ptid into top 16 bits of r1, zero bottom 16 bits |
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428 asm("mov r2, r2, lsr #20 "); // r2=anAddr>>20 |
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429 asm("mov r2, r2, lsl #2 "); // r2=pdeIndex*4 |
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430 asm("add r2, r2, #%a0" : : "i" ((TInt)KPageDirectoryLinearAddress)); // r2 points to PDE for anAddr |
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431 asm("mrc p15, 0, lr, c3, c0, 0 "); // lr=current DACR |
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432 asm("orr r4, lr, #0x30 "); |
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433 asm("mcr p15, 0, r4, c3, c0, 0 "); // unlock page tables |
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434 CPWAIT(,r4); |
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435 asm("ldr r0, [r0] "); // fetch page table PTE |
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436 asm("mov r0, r0, lsr #12 "); // shift out permission bits, leave phys addr>>12 |
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437 asm("orr r3, r3, r0, lsl #12 "); // r3=PDE word (add PDE permissions and offset within page) |
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438 asm("str r3, [r2] "); // store PDE |
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439 asm("add r2, r2, #%a0" : : "i" ((TInt)KPageTableInfoOffset)); // r2 points to PT info entry |
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440 asm("str r1, [r2] "); // PTinfo top 16=page table ID, PT info bottom 16=pages present=0 (assumption) |
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441 asm("mcr p15, 0, lr, c3, c0, 0 "); // lock page tables |
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442 DRAIN_WRITE_BUFFER(,r0,r0); |
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443 CPWAIT(,r0); |
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444 asm("ldmfd sp!, {r4,pc} "); |
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445 } |
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446 |
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447 __NAKED__ void ImpMmu::UnassignPageTable(TLinAddr /*anAddr*/) |
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448 // |
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449 // Unassign a now-empty page table currently mapping the specified linear address. |
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450 // We assume that TLB and/or cache flushing has been done when any RAM pages were unmapped. |
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451 // Call this with the kernel locked. |
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452 // |
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453 { |
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454 asm("mov r1, r1, lsr #20 "); // r1=anAddr>>20 |
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455 asm("mov r0, #%a0" : : "i" ((TInt)KPageDirectoryLinearAddress)); |
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456 asm("add r0, r0, r1, lsl #2 "); // r0 points to page directory entry for anAddr |
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457 asm("ldr r1, __NotPresentPtInfo "); // r1=PTInfo entry for not present PDE |
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458 asm("mrc p15, 0, r2, c3, c0, 0 "); // r2=current DACR |
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459 asm("orr r3, r2, #0x30 "); |
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460 asm("mcr p15, 0, r3, c3, c0, 0 "); // unlock page tables |
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461 CPWAIT(,r3); |
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462 asm("mov r3, #0 "); |
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463 asm("str r3, [r0] "); // clear the PDE |
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464 asm("add r0, r0, #%a0" : : "i" ((TInt)KPageTableInfoOffset)); // step r0 on to PT info entry |
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465 asm("str r1, [r0] "); // clear the PT info entry |
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466 asm("mcr p15, 0, r2, c3, c0, 0 "); // lock page tables |
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467 DRAIN_WRITE_BUFFER(,r0,r0); |
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468 CPWAIT(,r0); |
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469 __JUMP(,lr); |
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470 |
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471 asm("__NotPresentPtInfo: "); |
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472 asm(".word 0xffff0000 "); |
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473 } |
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474 #endif |
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475 |
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476 |