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1 // Copyright (c) 1997-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // e32\memmodel\epoc\multiple\arm\xmmu.cia |
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15 // |
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16 // |
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17 |
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18 #include <arm_mem.h> |
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19 #include "execs.h" |
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20 #include <nk_cpu.h> |
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21 |
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22 #if defined(__CPU_ARM1136__) && !defined(__CPU_ARM1136_ERRATUM_353494_FIXED) |
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23 // This will also invalidate TLB entry if the third argument (asid) is specified (>=0). |
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24 // If asid is < 0, the caller is expected to deal with TLB invalidation. |
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25 __NAKED__ void remove_and_invalidate_page(TPte*, TLinAddr, TInt) |
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26 { |
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27 asm("stmfd sp!, {r4-r6,lr} "); |
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28 asm("mov r6, r2 "); //r6 = asid |
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29 asm("mov r4, r0 "); |
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30 asm("mov r5, #1 "); //by default, one cache line to clean |
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31 |
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32 asm("ldr r3, [r0] "); // r0 = original PTE |
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33 asm("cmp r2, #0 "); |
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34 asm("bicpl r1, r1, #0xff "); |
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35 asm("orrpl r1, r1, r2 "); // if ASID supplied, combine with VA |
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36 asm("mrs r12, cpsr "); |
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37 asm("mov r2, #0 "); |
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38 CPSIDAIF; // interrupts off |
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39 asm("str r2, [r0], #4 "); // clear PTE |
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40 asm("tst r3, #3 "); // PTE present? |
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41 asm("beq 0f "); // if not, done |
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42 asm("tst r3, #2 "); // small page? |
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43 asm("bne 1f "); // skip if small |
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44 |
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45 asm("mov r5, #2 "); // there will be 2 cache lines to clean |
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46 asm("mov r3, #0 "); |
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47 asm("str r2, [r0], #4 "); |
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48 asm("stmia r0!, {r2,r3} "); // clear 16 consecutive PTEs |
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49 asm("stmia r0!, {r2,r3} "); |
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50 asm("stmia r0!, {r2,r3} "); |
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51 asm("stmia r0!, {r2,r3} "); |
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52 asm("stmia r0!, {r2,r3} "); |
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53 asm("stmia r0!, {r2,r3} "); |
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54 asm("stmia r0!, {r2,r3} "); |
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55 |
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56 asm("1: "); |
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57 #if defined(__CPU_PAGE_TABLES_FULLY_CACHED) |
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58 // Clean the changed page table entries from the cache. |
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59 // On ARM1136, cache line is always 32 bytes. |
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60 // For small page, a single cache line has to be cached. |
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61 // For large page, 16 page table entries always fits into two cache lines |
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62 CLEAN_DCACHE_LINE(,r4); |
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63 asm("subs r5, r5, #1"); |
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64 asm("addhi r4, r4, #32");// Clean the next cache line as well. Executes ... |
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65 CLEAN_DCACHE_LINE(hi,r4);// ... only in case of large page table. |
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66 #endif |
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67 |
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68 asm("mcr p15, 0, r1, c7, c10, 4 "); // drain write buffer |
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69 asm("cmp r6, #0"); //is asid valid? |
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70 |
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71 FLUSH_DTLB_ENTRY(pl,r1); // remove stale TLB entry if asid >= 0 |
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72 FLUSH_ITLB_ENTRY(pl,r1); |
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73 |
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74 asm("0: "); |
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75 asm("msr cpsr, r12 "); |
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76 asm("ldmfd sp!, {r4-r6,pc} "); // if successful, exit |
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77 } |
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78 |
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79 // This will also invalidate TLB entry. (The third argument (asid) is assumed to be valid (>=0).) |
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80 __NAKED__ void remove_and_invalidate_section(TPde*, TLinAddr, TInt) |
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81 { |
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82 asm("ldr r3, [r0] "); // r0 = original PDE |
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83 asm("cmp r2, #0 "); |
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84 asm("bicpl r1, r1, #0xff "); |
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85 asm("orrpl r1, r1, r2 "); // if ASID supplied, combine with VA |
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86 asm("mrs r12, cpsr "); |
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87 asm("mov r2, #0 "); |
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88 CPSIDAIF; // interrupts off |
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89 asm("tst r3, #3 "); // PDE present? |
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90 asm("beq 0f "); // if not, done |
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91 asm("str r2, [r0] "); // clear PDE |
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92 #if defined(__CPU_PAGE_TABLES_FULLY_CACHED) |
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93 CLEAN_DCACHE_LINE(,r0); |
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94 #endif |
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95 asm("mcr p15, 0, r1, c7, c10, 4 "); // drain write buffer |
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96 FLUSH_DTLB_ENTRY(,r1); // remove stale TLB entry |
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97 FLUSH_ITLB_ENTRY(,r1); |
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98 asm("0: "); |
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99 asm("msr cpsr, r12 "); |
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100 __JUMP(,lr); |
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101 } |
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102 #endif |
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103 |
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104 |
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105 __NAKED__ void MakeGlobalPTEInaccessible(TPte* aPtePtr, TPte aNewPte, TLinAddr aLinAddr) |
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106 { |
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107 asm("mov r3,#0 "); |
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108 // fall through |
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109 } |
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110 |
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111 __NAKED__ void MakePTEInaccessible(TPte* aPtePtr, TPte aNewPte, TLinAddr aLinAddr, TInt aAsid) |
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112 { |
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113 asm("bic r2, r2, #0xff "); |
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114 asm("orr r2, r2, r3 "); |
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115 #if defined(__CPU_ARM1136__) && !defined(__CPU_ARM1136_ERRATUM_353494_FIXED) |
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116 CPSIDIF; // interrupts off |
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117 asm("str r1,[r0]"); |
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118 #if defined(__CPU_PAGE_TABLES_FULLY_CACHED) |
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119 CLEAN_DCACHE_LINE(,r0); |
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120 #endif |
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121 DRAIN_WRITE_BUFFER(,r1,r1); |
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122 FLUSH_DTLB_ENTRY(,r2); // remove stale TLB entries |
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123 FLUSH_ITLB_ENTRY(,r2); |
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124 asm("mov r1, #0"); |
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125 FLUSH_BTB(,r1); |
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126 CPSIEIF; // interrupts on |
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127 #else |
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128 asm("str r1,[r0]"); |
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129 #if defined(__CPU_PAGE_TABLES_FULLY_CACHED) |
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130 #ifdef __CPU_ARMV7 |
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131 DCCMVAU(r0); |
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132 ARM_DSBSH; |
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133 #else |
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134 CLEAN_DCACHE_LINE(,r0); |
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135 DRAIN_WRITE_BUFFER(,r1,r1); |
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136 #endif |
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137 #endif |
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138 #ifdef __CPU_ARMV7 |
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139 UTLBIMVA(r2); |
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140 ARM_DSBSH; |
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141 ARM_ISBSY; |
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142 #else |
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143 FLUSH_DTLB_ENTRY(,r2); // remove stale TLB entries |
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144 FLUSH_ITLB_ENTRY(,r2); |
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145 #endif |
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146 #endif |
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147 __JUMP(,lr); |
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148 } |
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149 |
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150 |
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151 __NAKED__ void InvalidateTLBForPage(TLinAddr /*aLinAddr*/, TInt /*aAsid*/) |
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152 // |
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153 // Flush a specified virtual address from the TLB. |
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154 // If aAsid>0, flush is restricted to ASID=aAsid for non-global entries. |
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155 // If aAsid=0, Kernel asid is specified - will flush global entry or the entry belonging to local Kernel space. |
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156 // If aAsid<0, no ASID is specified - will flush all TLB entries with matching VA regardles of ASID (or whether they are |
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157 // local or global). In the absence of such MMU command, flush-entire-TLB will apply here. |
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158 { |
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159 asm("cmp r1, #0 "); |
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160 asm("bmi 1f "); |
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161 asm("bic r0, r0, #0xff "); // if aAsid > 0, orr it with linear address in r0. |
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162 asm("orr r0, r0, r1 "); |
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163 #ifdef __CPU_ARMV7 |
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164 UTLBIMVA(r0); |
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165 ARM_DSBSH; |
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166 ARM_ISBSY; |
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167 #else |
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168 FLUSH_DTLB_ENTRY(,r0); |
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169 FLUSH_ITLB_ENTRY(,r0); |
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170 #endif |
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171 __JUMP(,lr); |
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172 |
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173 asm("1: "); |
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174 #ifdef __CPU_ARMV7 |
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175 UTLBIALL; |
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176 ARM_DSBSH; |
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177 ARM_ISBSY; |
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178 #else |
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179 asm("mov r0, #0 "); |
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180 FLUSH_IDTLB(,r0); // aAsid < 0. There is no coprocessor instruction that will flush all ... |
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181 // ... entries matching Linear address. Flush entire TLB instead and exit. |
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182 #endif |
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183 __JUMP(,lr); |
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184 } |
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185 |
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186 __NAKED__ void FlushTLBs() |
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187 { |
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188 #ifdef __CPU_ARMV7 |
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189 UTLBIALL; |
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190 ARM_DSBSH; |
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191 ARM_ISBSY; |
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192 #else |
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193 asm("mov r0, #0 "); |
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194 FLUSH_IDTLB(,r0); |
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195 #endif |
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196 __JUMP(,lr); |
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197 } |
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198 |
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199 __NAKED__ TUint32 TTCR() |
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200 { |
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201 asm("mrc p15, 0, r0, c2, c0, 2 "); |
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202 asm("and r0, r0, #7 "); // only bottom 3 bits are defined |
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203 __JUMP(,lr); |
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204 } |
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205 |
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206 GLDEF_C __NAKED__ void __FlushBtb() |
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207 { |
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208 #ifdef __CPU_ARMV7 |
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209 #ifdef __SMP__ |
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210 BPIALLIS; |
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211 #else //def __SMP__ |
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212 BPIALL; |
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213 #endif // else __SMP__ |
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214 ARM_DSBSH; |
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215 ARM_ISBSY; |
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216 #else //def __CPU_ARMV7 |
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217 asm("mov r1, #0"); |
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218 FLUSH_BTB(,r1); |
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219 #endif //else __CPU_ARMV7 |
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220 __JUMP(,lr); |
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221 } |
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222 |
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223 // Generic cache/TLB flush function. |
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224 // Which things are flushed is determined by aMask. |
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225 __NAKED__ void ArmMmu::GenericFlush(TUint32 /*aMask*/) |
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226 { |
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227 #ifdef __CPU_ARMV7 |
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228 asm("tst r1, #%a0" : : "i" (EFlushDTLB) ); |
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229 asm("tsteq r1, #%a0" : : "i" (EFlushDPermChg) ); |
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230 asm("tsteq r1, #%a0" : : "i" (EFlushITLB) ); |
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231 asm("tsteq r1, #%a0" : : "i" (EFlushIPermChg) ); |
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232 asm("beq 1f "); |
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233 UTLBIALL; |
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234 ARM_DSBSH; |
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235 ARM_ISBSY; |
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236 asm("1: "); |
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237 #else |
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238 asm("mov r2, #0 "); |
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239 asm("tst r1, #%a0" : : "i" (EFlushDTLB) ); |
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240 asm("tsteq r1, #%a0" : : "i" (EFlushDPermChg) ); |
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241 FLUSH_DTLB(ne,r2); |
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242 asm("tst r1, #%a0" : : "i" (EFlushITLB) ); |
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243 asm("tsteq r1, #%a0" : : "i" (EFlushIPermChg) ); |
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244 FLUSH_ITLB(ne,r2); |
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245 #endif |
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246 __JUMP(,lr); |
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247 } |
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248 |
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249 __NAKED__ void ExecHandler::UnlockRamDrive() |
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250 { |
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251 asm("ldr r0, [r1, #%a0]" : : "i" (_FOFF(DThread,iOwningProcess)-_FOFF(DThread,iNThread))); |
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252 asm("ldr r0, [r0, #%a0]" : : "i" _FOFF(DProcess,iS.iCaps)); |
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253 // __KERNEL_CAPABILITY_CHECK |
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254 asm("tst r0, #%a0 " : : "i" ((TInt)(1<<ECapabilityTCB))); |
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255 __JUMP(eq,lr); // don't unlock the RAM drive if don't have MediaDD capability |
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256 |
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257 // fall through to unlock |
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258 } |
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259 |
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260 EXPORT_C __NAKED__ void TInternalRamDrive::Unlock() |
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261 { |
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262 asm("mrc p15, 0, r0, c3, c0, 0 "); |
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263 asm("bic r0, r0, #0x0c "); |
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264 asm("orr r0, r0, #0x04 "); // RAM drive in domain 1 |
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265 asm("mcr p15, 0, r0, c3, c0, 0 "); |
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266 CPWAIT(,r0); |
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267 __JUMP(,lr); |
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268 } |
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269 |
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270 EXPORT_C __NAKED__ void TInternalRamDrive::Lock() |
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271 { |
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272 asm("mrc p15, 0, r0, c3, c0, 0 "); |
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273 asm("bic r0, r0, #0x0c "); // RAM drive in domain 1 |
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274 asm("mcr p15, 0, r0, c3, c0, 0 "); |
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275 CPWAIT(,r0); |
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276 __JUMP(,lr); |
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277 } |
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278 |
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279 __NAKED__ void ArmMmu::UnlockAlias() |
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280 { |
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281 asm("mrc p15, 0, r0, c3, c0, 0 "); |
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282 asm("orr r0, r0, #0x10 "); // Alias memory in domain 2 |
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283 asm("mcr p15, 0, r0, c3, c0, 0 "); |
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284 CPWAIT(,r0); |
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285 __JUMP(,lr); |
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286 } |
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287 |
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288 __NAKED__ void ArmMmu::LockAlias() |
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289 { |
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290 asm("mrc p15, 0, r0, c3, c0, 0 "); |
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291 asm("bic r0, r0, #0x30 "); // Alias memory in domain 2 |
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292 asm("mcr p15, 0, r0, c3, c0, 0 "); |
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293 CPWAIT(,r0); |
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294 __JUMP(,lr); |
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295 } |
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296 |
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297 |
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298 __NAKED__ void M::LockUserMemory() |
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299 { |
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300 USER_MEMORY_GUARD_ON(,r0,r0); |
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301 __JUMP(,lr); |
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302 } |
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303 |
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304 |
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305 __NAKED__ void M::UnlockUserMemory() |
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306 { |
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307 USER_MEMORY_GUARD_OFF(,r0,r0); |
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308 __JUMP(,lr); |
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309 } |
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310 |