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1 // Copyright (c) 1997-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // e32\memmodel\epoc\multiple\arm\xsched.cia |
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15 // |
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16 // |
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17 |
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18 #include <e32cia.h> |
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19 #include <arm_mem.h> |
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20 #include "nk_cpu.h" |
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21 |
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22 #define iMState iWaitLink.iSpare1 |
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23 |
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24 //#define __DEBUG_BAD_ADDR |
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25 |
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26 #ifdef __REQUEST_COMPLETE_MACHINE_CODED__ |
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27 #if defined(_DEBUG) |
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28 extern "C" void __DebugMsgRequestComplete(TInt a0, TInt a1, TInt a2); |
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29 extern "C" void __DebugMsgReqCompleteWrite(TInt a0, TInt a1, TInt a2); |
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30 #endif |
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31 |
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32 __NAKED__ void DThread::RequestComplete(TRequestStatus*& /*aStatus*/, TInt /*aReason*/) |
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33 // |
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34 // Signal this threads request semaphore. |
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35 // Enter with system locked, return with system unlocked. |
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36 // |
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37 { |
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38 ASM_DEBUG2(DThreadRequestComplete,r0,lr); |
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39 |
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40 asm("ldr r3, [r1] "); // r3 points to TRequestStatus |
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41 asm("mov r12, #0 "); |
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42 asm("str r12, [r1] "); // aStatus=NULL |
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43 |
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44 asm(".global _asm_RequestComplete "); |
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45 asm("_asm_RequestComplete: "); |
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46 |
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47 #ifdef BTRACE_REQUESTS |
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48 asm("stmdb sp!,{r0-r3,lr}"); |
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49 asm("mov r1,r3"); |
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50 asm("mov r3,r2"); // arg3 = aReason |
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51 asm("mov r2,r1"); // arg2 = aStatus |
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52 asm("add r1,r0,#%a0" : : "i" _FOFF(DThread,iNThread)); // arg1 = &this->iNThread |
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53 asm("ldr r0,_threadReqequestCompleteTraceHeader"); // arg0 = header |
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54 asm("bl " CSM_ZN6BTrace4OutXEmmmm); |
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55 asm("ldmia sp!,{r0-r3,lr}"); |
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56 #endif |
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57 |
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58 ASM_DEBUG3(RequestComplete,r0,r3,r2); |
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59 |
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60 // r0 -> DThread, r3 -> TRequestStatus in user space, r2 = aReason |
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61 asm("ldrb r12, [r0, #%a0]" : : "i" _FOFF(DThread,iMState)); |
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62 asm("ldr r1, __TheScheduler "); // r1->TheScheduler |
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63 asm("stmfd sp!, {r4-r9} "); |
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64 asm("add r6, r0, #%a0" : : "i" _FOFF(DThread,iNThread)); // r6->target NThread |
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65 asm("ldr r4, [r1, #%a0]" : : "i" _FOFF(TScheduler,iAddressSpace)); // r4->current process |
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66 asm("ldr r0, [r0, #%a0]" : : "i" _FOFF(DThread,iOwningProcess)); // r0->target process |
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67 asm("cmp r12, #%a0" : : "i" (DThread::EDead)); // test if iMState=EDead |
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68 asm("beq req_complete_dead_thread "); // if it is, finished |
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69 asm("ldr r5, [r1, #%a0]" : : "i" _FOFF(TScheduler,iCurrentThread)); // r5->current NThread |
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70 |
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71 asm("mrc p15, 0, r7, c2, c0, 0 "); // save TTBR0 |
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72 asm("ldr r9, [r0, #%a0]" : : "i" _FOFF(DMemModelProcess,iLocalPageDir)); // r9 -> target process page directory |
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73 asm("ldr r8, [r0, #%a0]" : : "i" _FOFF(DMemModelProcess,iOsAsid)); // r8 = target ASID |
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74 asm("and r12, r7, #%a0" : : "i" ((TInt)KTTBRExtraBitsMask)); // r12 = page table cache attributes |
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75 asm("orr r9, r9, r12 "); // r9 = target process TTBR0 value |
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76 asm("mrs r12, cpsr "); // save CPSR |
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77 CPSIDAIF; // disable all interrupts |
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78 asm("mcr p15, 0, r12, c7, c10, 4 "); // drain write buffer before changing MMU registers (see ARMv6 specs) |
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79 UPDATE_PW_CACHING_ATTRIBUTES(,r9); // ERRATUM 1136_317041 |
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80 asm("mcr p15, 0, r9, c2, c0, 0 "); // change TTBR0 |
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81 asm("mcr p15, 0, r8, c13, c0, 1 "); // change ASID |
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82 |
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83 #if defined(__CPU_ARM11MP__) |
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84 // On other platforms, tha ASID change above has already flushed the branch prediction buffers |
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85 asm("mcr p15, 0, r12, c7, c5, 6 "); // flush BTAC |
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86 #endif |
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87 |
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88 asm("str r0, [r1, #%a0]" : : "i" _FOFF(TScheduler,iAddressSpace)); |
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89 asm("str r0, [r5, #%a0]" : : "i" _FOFF(NThread,iAddressSpace)); |
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90 asm("msr cpsr, r12 "); // restore interrupts |
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91 |
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92 USER_MEMORY_GUARD_OFF(,r12,r12); |
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93 asm(".global __magic_address_reqc "); // NOTE: Z flag always clear here |
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94 asm("__magic_address_reqc: "); // this instruction is magically immune from exceptions |
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95 asm("strt r2, [r3] "); // store completion code with user permissions |
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96 // MAY MODIFY Z and R12 |
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97 USER_MEMORY_GUARD_ON(,r12,r12); |
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98 |
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99 asm("mrs r12, cpsr "); // save CPSR and Z flag which indicates whether write succeeded |
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100 asm("ldr r2, [r4, #%a0]" : : "i" _FOFF(DMemModelProcess,iOsAsid)); // r2 = current process ASID |
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101 CPSIDAIF; // disable all interrupts |
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102 asm("mcr p15, 0, r12, c7, c10, 4 "); // drain write buffer before changing MMU registers (see ARMv6 specs) |
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103 UPDATE_PW_CACHING_ATTRIBUTES(,r7); // ERRATUM 1136_317041 |
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104 asm("mcr p15, 0, r7, c2, c0, 0 "); // restore TTBR0 |
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105 asm("mcr p15, 0, r2, c13, c0, 1 "); // restore ASID |
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106 |
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107 #if defined(__CPU_ARM11MP__) |
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108 // On other platforms, tha ASID change above has already flushed the branch prediction buffers |
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109 asm("mcr p15, 0, r12, c7, c5, 6 "); // flush BTAC |
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110 #endif |
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111 |
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112 asm("str r4, [r1, #%a0]" : : "i" _FOFF(TScheduler,iAddressSpace)); |
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113 asm("str r4, [r5, #%a0]" : : "i" _FOFF(NThread,iAddressSpace)); |
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114 asm("msr cpsr, r12 "); // restore interrupts and Z flag |
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115 |
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116 #ifdef __DEBUG_BAD_ADDR |
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117 asm("moveq r12, #0xde000000 "); |
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118 asm("streq r12, [r12, #0xaf] "); //HACK-CRASH SYSTEM IF WRITE FAILED |
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119 #endif |
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120 |
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121 asm("movne r0, r6 "); // if write OK, r0->iNThread |
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122 asm("req_complete_dead_thread: "); // NOTE: Z flag set if thread dead |
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123 asm("ldmfd sp!, {r4-r9} "); // restore registers whether OK or not |
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124 asm("movne r1, #0 "); |
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125 asm("bne " CSM_ZN5NKern19ThreadRequestSignalEP7NThreadP10NFastMutex ); |
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126 asm("b " CSM_ZN5NKern12UnlockSystemEv); // if any error, unlock system and return |
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127 |
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128 #ifdef BTRACE_REQUESTS |
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129 asm("_threadReqequestCompleteTraceHeader:"); |
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130 asm(".word %a0" : : "i" (BTRACE_HEADER_C(16,BTrace::ERequests,BTrace::ERequestComplete))); |
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131 #endif |
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132 } |
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133 #endif |
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134 |
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135 GLDEF_C __NAKED__ void DoProcessSwitch() |
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136 { |
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137 // Enter and return with kernel locked |
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138 // r0->scheduler, r3->current thread |
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139 // r5->old process, r9->new process |
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140 // Return with r2 = (r2<<8) | ASID |
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141 // Must preserve r0,r3, can modify other registers |
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142 |
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143 // This code is optimized with the ARM1136 static branch prediction scheme in mind. |
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144 // Unusually, ARM1136 flushes the BTAC on every ContextID write whether it needs to |
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145 // or not! We only need to flush the prefetch if there's differing local code... -jls |
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146 |
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147 asm("cmp r5, r9 "); // check if current address space correct |
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148 asm("beq address_switch_done"); // skip if address space change not required |
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149 |
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150 asm("mrc p15, 0, r1, c2, c0, 0 "); // get TTBR0 |
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151 asm("ldr r4, [r9, #%a0]" : : "i" _FOFF(DMemModelProcess, iLocalPageDir)); |
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152 asm("and r1, r1, #%a0" : : "i" ((TInt)KTTBRExtraBitsMask)); // r1 = page table cache attributes |
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153 asm("str r9, [r0, #%a0]" : : "i" _FOFF(TScheduler, iAddressSpace)); |
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154 asm("orr r4, r4, r1 "); // r4 = new TTBR0 value |
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155 asm("ldr r1, [r9, #%a0]" : : "i" _FOFF(DMemModelProcess, iSelfModChunks)); |
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156 asm("mcr p15, 0, r4, c7, c10, 4 "); // drain write buffer before changing MMU registers (see ARMv6 specs) |
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157 UPDATE_PW_CACHING_ATTRIBUTES(,r4); // ERRATUM 1136_317041 |
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158 asm("mcr p15, 0, r4, c2, c0, 0 "); // set TTBR0 - no TLB flush required due to ASID |
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159 asm("cmp r1, #0"); // do we have selfmod chunks? (probably not) |
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160 asm("bgt gotchunks "); // yes, so we need to look closer (will predict not taken) |
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161 |
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162 asm("address_switch_done:"); |
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163 asm("ldr r4, [r9, #%a0]" : : "i" _FOFF(DMemModelProcess, iOsAsid)); |
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164 asm("ldr r6, [r3, #%a0]" : : "i" (_FOFF(DMemModelThread, iAliasLinAddr)-_FOFF(DThread, iNThread)) ); |
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165 asm("orr r2, r4, r2, lsl #8 "); // r2 = original r2 << 8 | ASID |
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166 asm("cmp r6, #0"); // check if thread has an alias in place |
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167 asm("bne got_alias"); |
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168 __JUMP(,lr); |
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169 |
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170 // restore alias... |
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171 asm("got_alias:"); |
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172 asm("ldr r7, [r3, #%a0]" : : "i" (_FOFF(DMemModelThread, iAliasPde)-_FOFF(DThread, iNThread)) ); |
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173 asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(TScheduler, iExtras[1])); // Alias remap old address |
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174 asm("ldr r8, [r3, #%a0]" : : "i" (_FOFF(DMemModelThread, iAliasPdePtr)-_FOFF(DThread, iNThread)) ); |
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175 asm("orr r6, r6, r4"); // put ASID into address for TLB flush later... |
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176 asm("eor r1, r1, r7 "); // compare old address with pde |
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177 asm("cmp r1, #0x1000 "); // if result only has perm bits, addresses were the same |
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178 asm("blo remap_alias "); |
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179 |
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180 asm("alias_remap_done: "); |
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181 asm("str r7, [r8]"); // restore PDE for alias |
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182 |
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183 CACHE_MAINTENANCE_PDE_PTE_UPDATED(r8); |
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184 |
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185 #ifdef __CPU_ARMV7 |
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186 UTLBIMVA(r6); |
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187 ARM_DSBSH; |
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188 ARM_ISBSY; |
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189 #else |
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190 FLUSH_DTLB_ENTRY(,r6); // flush TLB for aliased page |
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191 #endif |
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192 __JUMP(,lr); |
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193 |
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194 asm("remap_alias: "); |
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195 asm("ldr r7, [r0, #%a0]" : : "i" _FOFF(TScheduler, iExtras[2])); // Alias remap new address |
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196 asm("orr r7, r1, r7 "); // r1 has perm bits, left over from xor above |
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197 asm("b alias_remap_done "); |
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198 |
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199 asm("gotchunks: "); |
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200 asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(TScheduler, iExtras[0])); // address of last selfmod process |
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201 asm("cmp r1, r9"); // was it whoever's next up? (probably) |
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202 asm("beq address_switch_done"); |
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203 asm("mcr p15, 0, r4, c7, c5, 4 "); // prefetch flush before returning |
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204 #ifdef __CPU_HAS_UNFLUSHED_BTB |
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205 #ifdef __CPU_ARMV7 |
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206 BPIALL; |
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207 #else |
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208 FLUSH_BTB(,r1); // flush the dynamic branch predictor table |
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209 #endif |
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210 #endif |
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211 asm("str r9, [r0, #%a0]" : : "i" _FOFF(TScheduler, iExtras[0])); // update it |
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212 asm("b address_switch_done"); |
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213 |
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214 asm("__TheScheduler: "); |
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215 asm(".word TheScheduler "); |
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216 }; |
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217 |
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218 /** |
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219 Restore the address space of the current thread so it matches its owning process. |
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220 */ |
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221 __NAKED__ void DMemModelThread::RestoreAddressSpace() |
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222 { |
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223 asm("ldr r12, __TheScheduler "); // r12->TheScheduler |
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224 asm("ldr r3, [r12, #%a0]" : : "i" _FOFF(TScheduler,iCurrentThread)); // r3->current NThread |
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225 asm("ldr r0, [r3, #%a0]" : : "i" (-_FOFF(DThread,iNThread)+_FOFF(DThread,iOwningProcess))); // r0->process |
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226 |
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227 // switch address space to process r0... |
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228 asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(DMemModelProcess,iLocalPageDir));// r1->process page directory |
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229 asm("mrc p15, 0, r2, c2, c0, 0 "); // get TTBR0 |
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230 asm("and r2, r2, #%a0" : : "i" ((TInt)KTTBRExtraBitsMask)); // r2 = page table cache attributes |
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231 asm("orr r1, r1, r2 "); // r1 = new TTBR0 value |
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232 asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(DMemModelProcess,iOsAsid)); // r2 = ASID |
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233 CPSIDAIF; // disable all interrupts |
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234 asm("mcr p15, 0, r2, c7, c10, 4 "); // drain write buffer before changing MMU registers (see ARMv6 specs) |
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235 UPDATE_PW_CACHING_ATTRIBUTES(,r1); // ERRATUM 1136_317041 |
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236 asm("mcr p15, 0, r1, c2, c0, 0 "); // change TTBR0 |
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237 asm("mcr p15, 0, r2, c13, c0, 1 "); // change ASID |
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238 |
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239 #if defined(__CPU_ARM11MP__) |
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240 // On other platforms, tha ASID change above has already flushed the branch prediction buffers |
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241 asm("mcr p15, 0, r2, c7, c5, 6 "); // flush BTAC |
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242 #endif |
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243 |
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244 asm("str r0, [r12, #%a0]" : : "i" _FOFF(TScheduler,iAddressSpace)); |
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245 asm("str r0, [r3, #%a0]" : : "i" _FOFF(NThread,iAddressSpace)); |
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246 CPSIEAIF; // enable all interrupts |
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247 __JUMP(,lr); |
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248 } |