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1 // Copyright (c) 1995-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // e32test\mmu\t_imb.cia |
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15 // |
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16 // |
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17 |
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18 #include <e32test.h> |
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19 #include <u32std.h> |
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20 #include <e32math.h> |
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21 |
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22 #ifdef __CPU_ARM |
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23 __NAKED__ TInt Sqrt(TReal& /*aDest*/, const TReal& /*aSrc*/) |
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24 { |
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25 // r0=address of aDest, r1=address of aSrc |
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26 asm("stmfd sp!, {r4-r10,lr} "); |
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27 #ifdef __DOUBLE_WORDS_SWAPPED__ |
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28 asm("ldmia r1, {r3,r4} "); // low mant into r4, sign:exp:high mant into r3 |
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29 #else |
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30 asm("ldr r3, [r1, #4] "); |
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31 asm("ldr r4, [r1, #0] "); |
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32 #endif |
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33 asm("bic r5, r3, #0xFF000000 "); |
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34 asm("bic r5, r5, #0x00F00000 "); // high word of mantissa into r5 |
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35 asm("mov r2, r3, lsr #20 "); |
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36 asm("bics r2, r2, #0x800 "); // exponent now in r2 |
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37 asm("beq fastsqrt1 "); // branch if exponent zero (zero or denormal) |
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38 asm("mov r6, #0xFF "); |
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39 asm("orr r6, r6, #0x700 "); |
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40 asm("cmp r2, r6 "); // check for infinity or NaN |
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41 asm("beq fastsqrt2 "); // branch if infinity or NaN |
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42 asm("movs r3, r3 "); // test sign |
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43 asm("bmi fastsqrtn "); // branch if negative |
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44 asm("sub r2, r2, #0xFF "); // unbias the exponent |
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45 asm("sub r2, r2, #0x300 "); // |
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46 asm("fastsqrtd1: "); |
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47 asm("mov r1, #0x40000000 "); // value for comparison |
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48 asm("mov r3, #27 "); // loop counter (number of bits/2) |
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49 asm("movs r2, r2, asr #1 "); // divide exponent by 2, LSB into CF |
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50 asm("movcs r7, r5, lsl #11 "); // mantissa into r6,r7 with MSB in MSB of r7 |
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51 asm("orrcs r7, r7, r4, lsr #21 "); |
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52 asm("movcs r6, r4, lsl #11 "); |
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53 asm("movcs r4, #0 "); // r4, r5 will hold result mantissa |
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54 asm("orrcs r7, r7, #0x80000000 "); // if exponent odd, restore MSB of mantissa |
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55 asm("movcc r7, r5, lsl #12 "); // mantissa into r6,r7 with MSB in MSB of r7 |
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56 asm("orrcc r7, r7, r4, lsr #20 "); // if exponent even, shift mantissa left an extra |
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57 asm("movcc r6, r4, lsl #12 "); // place, lose top bit, and |
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58 asm("movcc r4, #1 "); // set MSB of result, and |
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59 asm("mov r5, #0 "); // r4, r5 will hold result mantissa |
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60 asm("mov r8, #0 "); // r8, r9 will be comparison accumulator |
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61 asm("mov r9, #0 "); |
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62 asm("bcc fastsqrt4 "); // if exponent even, calculate one less bit |
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63 // as result MSB already known |
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64 |
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65 // Main mantissa square-root loop |
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66 asm("fastsqrt3: "); // START OF MAIN LOOP |
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67 asm("subs r10, r7, r1 "); // subtract result:01 from acc:mant |
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68 asm("sbcs r12, r8, r4 "); // result into r14:r12:r10 |
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69 asm("sbcs r14, r9, r5 "); |
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70 asm("movcs r7, r10 "); // if no borrow replace accumulator with result |
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71 asm("movcs r8, r12 "); |
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72 asm("movcs r9, r14 "); |
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73 asm("adcs r4, r4, r4 "); // shift result left one, putting in next bit |
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74 asm("adcs r5, r5, r5 "); |
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75 asm("mov r9, r9, lsl #2 "); // shift acc:mant left by 2 bits |
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76 asm("orr r9, r9, r8, lsr #30 "); |
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77 asm("mov r8, r8, lsl #2 "); |
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78 asm("orr r8, r8, r7, lsr #30 "); |
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79 asm("mov r7, r7, lsl #2 "); |
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80 asm("orr r7, r7, r6, lsr #30 "); |
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81 asm("mov r6, r6, lsl #2 "); |
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82 asm("fastsqrt4: "); // Come in here if we need to do one less iteration |
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83 asm("subs r10, r7, r1 "); // subtract result:01 from acc:mant |
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84 asm("sbcs r12, r8, r4 "); // result into r14:r12:r10 |
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85 asm("sbcs r14, r9, r5 "); |
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86 asm("movcs r7, r10 "); // if no borrow replace accumulator with result |
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87 asm("movcs r8, r12 "); |
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88 asm("movcs r9, r14 "); |
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89 asm("adcs r4, r4, r4 "); // shift result left one, putting in next bit |
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90 asm("adcs r5, r5, r5 "); |
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91 asm("mov r9, r9, lsl #2 "); // shift acc:mant left by 2 bits |
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92 asm("orr r9, r9, r8, lsr #30 "); |
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93 asm("mov r8, r8, lsl #2 "); |
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94 asm("orr r8, r8, r7, lsr #30 "); |
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95 asm("mov r7, r7, lsl #2 "); |
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96 asm("orr r7, r7, r6, lsr #30 "); |
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97 asm("mov r6, r6, lsl #2 "); |
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98 asm("subs r3, r3, #1 "); // decrement loop counter |
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99 asm("bne fastsqrt3 "); // do necessary number of iterations |
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100 |
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101 asm("movs r4, r4, lsr #1 "); // shift result mantissa right 1 place |
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102 asm("orr r4, r4, r5, lsl #31 "); // LSB (=rounding bit) into carry |
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103 asm("mov r5, r5, lsr #1 "); |
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104 asm("adcs r4, r4, #0 "); // round the mantissa to 53 bits |
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105 asm("adcs r5, r5, #0 "); |
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106 asm("cmp r5, #0x00200000 "); // check for mantissa overflow |
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107 asm("addeq r2, r2, #1 "); // if so, increment exponent - can never overflow |
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108 asm("bic r5, r5, #0x00300000 "); // remove top bit of mantissa - it is implicit |
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109 asm("add r2, r2, #0xFF "); // re-bias the exponent |
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110 asm("add r3, r2, #0x300 "); // and move into r3 |
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111 asm("orr r3, r5, r3, lsl #20 "); // r3 now contains exponent + top of mantissa |
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112 asm("fastsqrt_ok: "); |
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113 #ifdef __DOUBLE_WORDS_SWAPPED__ |
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114 asm("stmia r0, {r3,r4} "); // store the result |
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115 #else |
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116 asm("str r3, [r0, #4] "); |
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117 asm("str r4, [r0, #0] "); |
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118 #endif |
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119 asm("mov r0, #0 "); // error code KErrNone |
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120 __POPRET("r4-r10,"); |
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121 |
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122 asm("fastsqrt1: "); |
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123 asm("orrs r6, r5, r4 "); // exponent zero - test mantissa |
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124 asm("beq fastsqrt_ok "); // if zero, return 0 |
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125 |
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126 asm("movs r3, r3 "); // denormal - test sign |
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127 asm("bmi fastsqrtn "); // branch out if negative |
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128 asm("sub r2, r2, #0xFE "); // unbias the exponent |
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129 asm("sub r2, r2, #0x300 "); // |
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130 asm("fastsqrtd: "); |
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131 asm("adds r4, r4, r4 "); // shift mantissa left |
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132 asm("adcs r5, r5, r5 "); |
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133 asm("sub r2, r2, #1 "); // and decrement exponent |
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134 asm("tst r5, #0x00100000 "); // test if normalised |
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135 asm("beq fastsqrtd "); // loop until normalised |
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136 asm("b fastsqrtd1 "); // now treat as a normalised number |
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137 asm("fastsqrt2: "); // get here if infinity or NaN |
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138 asm("orrs r6, r5, r4 "); // if mantissa zero, infinity |
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139 asm("bne fastsqrtnan "); // branch if not - must be NaN |
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140 asm("movs r3, r3 "); // test sign of infinity |
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141 asm("bmi fastsqrtn "); // branch if -ve |
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142 #ifdef __DOUBLE_WORDS_SWAPPED__ |
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143 asm("stmia r0, {r3,r4} "); // store the result |
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144 #else |
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145 asm("str r3, [r0, #4] "); |
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146 asm("str r4, [r0, #0] "); |
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147 #endif |
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148 asm("mov r0, #-9 "); // return KErrOverflow |
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149 asm("b fastsqrt_end "); |
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150 |
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151 asm("fastsqrtn: "); // get here if negative or QNaN operand |
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152 asm("mov r3, #0xFF000000 "); // generate "real indefinite" QNaN |
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153 asm("orr r3, r3, #0x00F80000 "); // sign=1, exp=7FF, mantissa = 1000...0 |
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154 asm("mov r4, #0 "); |
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155 asm("fastsqrtxa: "); |
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156 #ifdef __DOUBLE_WORDS_SWAPPED__ |
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157 asm("stmia r0, {r3,r4} "); // store the result |
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158 #else |
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159 asm("str r3, [r0, #4] "); |
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160 asm("str r4, [r0, #0] "); |
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161 #endif |
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162 asm("mov r0, #-6 "); // return KErrArgument |
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163 asm("fastsqrt_end: "); |
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164 __POPRET("r4-r10,"); |
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165 |
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166 asm("fastsqrtnan: "); // operand is a NaN |
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167 asm("tst r5, #0x00080000 "); // test MSB of mantissa |
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168 asm("bne fastsqrtn "); // if set it is a QNaN - so return "real indefinite" |
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169 asm("bic r3, r3, #0x00080000 "); // else convert SNaN to QNaN |
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170 asm("b fastsqrtxa "); // and return KErrArgument |
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171 |
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172 asm("Sqrt__FRdRCd_end: "); |
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173 |
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174 } |
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175 |
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176 __NAKED__ TUint Sqrt_Length() |
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177 { |
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178 asm("adr r0, Sqrt__FRdRCd_end "); |
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179 asm("adr r1, Sqrt__FRdRCd "); |
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180 asm("sub r0, r0, r1 "); |
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181 __JUMP(,lr); |
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182 } |
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183 |
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184 __NAKED__ TInt Divide(TRealX& /*aDividend*/, const TRealX& /*aDivisor*/) |
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185 { |
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186 asm("stmfd sp!, {r0,r4-r9,lr} "); |
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187 asm("ldmia r1, {r4,r5,r6} "); |
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188 asm("ldmia r0, {r1,r2,r3} "); |
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189 asm("bl TRealXDivide "); |
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190 asm("ldmfd sp!, {r0,r4-r9,lr} "); |
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191 asm("stmia r0, {r1,r2,r3} "); |
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192 asm("mov r0, r12 "); |
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193 __JUMP(,lr); |
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194 |
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195 // TRealX division r1,r2,r3 / r4,r5,r6 result in r1,r2,r3 |
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196 // Error code returned in r12 |
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197 // Registers r0-r9,r12 modified |
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198 // NB This function is purely internal to EUSER and therefore IS ONLY EVER CALLED IN ARM MODE. |
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199 asm("TRealXDivide: "); |
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200 asm("mov r12, #0 "); // initialise return value to KErrNone |
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201 asm("bic r3, r3, #0x300 "); // clear rounding flags |
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202 asm("tst r6, #1 "); |
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203 asm("eorne r3, r3, #1 "); // Exclusive-OR signs |
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204 asm("cmn r3, #0x10000 "); // check if dividend is NaN or infinity |
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205 asm("bcs TRealXDivide1 "); // branch if it is |
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206 asm("cmn r6, #0x10000 "); // check if divisor is NaN or infinity |
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207 asm("bcs TRealXDivide2 "); // branch if it is |
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208 asm("cmp r6, #0x10000 "); // check if divisor zero |
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209 asm("bcc TRealXDivide3 "); // branch if it is |
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210 asm("cmp r3, #0x10000 "); // check if dividend zero |
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211 __JUMP(cc,lr); // if zero, exit |
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212 asm("tst r3, #1 "); |
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213 asm("orrne lr, lr, #1 "); // save sign in bottom bit of lr |
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214 |
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215 // calculate result exponent |
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216 asm("mov r0, r3, lsr #16 "); // r0=dividend exponent |
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217 asm("sub r0, r0, r6, lsr #16 "); // r0=dividend exponent - divisor exponent |
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218 asm("add r0, r0, #0x7F00 "); |
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219 asm("add r0, r0, #0x00FF "); // r0 now contains result exponent |
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220 asm("mov r6, r1 "); // move dividend into r6,r7,r8 |
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221 asm("mov r7, r2 "); |
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222 asm("mov r8, #0 "); // use r8 to hold extra bit shifted up |
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223 // r2:r1 will hold result mantissa |
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224 asm("mov r2, #1 "); // we will make sure first bit is 1 |
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225 asm("cmp r7, r5 "); // compare dividend mantissa to divisor mantissa |
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226 asm("cmpeq r6, r4 "); |
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227 asm("bcs TRealXDivide4 "); // branch if dividend >= divisor |
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228 asm("adds r6, r6, r6 "); // else shift dividend left one |
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229 asm("adcs r7, r7, r7 "); // ignore carry here |
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230 asm("sub r0, r0, #1 "); // decrement result exponent by one |
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231 asm("TRealXDivide4: "); |
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232 asm("subs r6, r6, r4 "); // subtract divisor from dividend |
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233 asm("sbcs r7, r7, r5 "); |
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234 |
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235 // Main mantissa division code |
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236 // First calculate the top 32 bits of the result |
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237 // Top bit is 1, do 10 lots of 3 bits the one more bit |
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238 asm("mov r12, #10 "); |
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239 asm("TRealXDivide5: "); |
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240 asm("adds r6, r6, r6 "); // shift accumulator left by one |
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241 asm("adcs r7, r7, r7 "); |
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242 asm("adcs r8, r8, r8 "); |
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243 asm("subs r9, r6, r4 "); // subtract divisor from accumulator, result in r9,r3 |
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244 asm("sbcs r3, r7, r5 "); |
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245 asm("movccs r8, r8, lsr #1 "); // if borrow, check for carry from shift |
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246 asm("movcs r6, r9 "); // if no borrow, replace accumulator with result |
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247 asm("movcs r7, r3 "); |
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248 asm("adcs r2, r2, r2 "); // shift in new result bit |
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249 asm("adds r6, r6, r6 "); // shift accumulator left by one |
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250 asm("adcs r7, r7, r7 "); |
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251 asm("adcs r8, r8, r8 "); |
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252 asm("subs r9, r6, r4 "); // subtract divisor from accumulator, result in r9,r3 |
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253 asm("sbcs r3, r7, r5 "); |
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254 asm("movccs r8, r8, lsr #1 "); // if borrow, check for carry from shift |
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255 asm("movcs r6, r9 "); // if no borrow, replace accumulator with result |
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256 asm("movcs r7, r3 "); |
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257 asm("adcs r2, r2, r2 "); // shift in new result bit |
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258 asm("adds r6, r6, r6 "); // shift accumulator left by one |
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259 asm("adcs r7, r7, r7 "); |
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260 asm("adcs r8, r8, r8 "); |
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261 asm("subs r9, r6, r4 "); // subtract divisor from accumulator, result in r9,r3 |
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262 asm("sbcs r3, r7, r5 "); |
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263 asm("movccs r8, r8, lsr #1 "); // if borrow, check for carry from shift |
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264 asm("movcs r6, r9 "); // if no borrow, replace accumulator with result |
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265 asm("movcs r7, r3 "); |
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266 asm("adcs r2, r2, r2 "); // shift in new result bit |
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267 asm("subs r12, r12, #1 "); |
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268 asm("bne TRealXDivide5 "); // iterate the loop |
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269 asm("adds r6, r6, r6 "); // shift accumulator left by one |
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270 asm("adcs r7, r7, r7 "); |
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271 asm("adcs r8, r8, r8 "); |
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272 asm("subs r9, r6, r4 "); // subtract divisor from accumulator, result in r9,r3 |
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273 asm("sbcs r3, r7, r5 "); |
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274 asm("movccs r8, r8, lsr #1 "); // if borrow, check for carry from shift |
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275 asm("movcs r6, r9 "); // if no borrow, replace accumulator with result |
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276 asm("movcs r7, r3 "); |
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277 asm("adcs r2, r2, r2 "); // shift in new result bit - now have 32 bits |
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278 |
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279 // Now calculate the bottom 32 bits of the result |
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280 // Do 8 lots of 4 bits |
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281 asm("mov r12, #8 "); |
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282 asm("TRealXDivide5a: "); |
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283 asm("adds r6, r6, r6 "); // shift accumulator left by one |
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284 asm("adcs r7, r7, r7 "); |
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285 asm("adcs r8, r8, r8 "); |
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286 asm("subs r9, r6, r4 "); // subtract divisor from accumulator, result in r9,r3 |
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287 asm("sbcs r3, r7, r5 "); |
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288 asm("movccs r8, r8, lsr #1 "); // if borrow, check for carry from shift |
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289 asm("movcs r6, r9 "); // if no borrow, replace accumulator with result |
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290 asm("movcs r7, r3 "); |
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291 asm("adcs r1, r1, r1 "); // shift in new result bit |
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292 asm("adds r6, r6, r6 "); // shift accumulator left by one |
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293 asm("adcs r7, r7, r7 "); |
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294 asm("adcs r8, r8, r8 "); |
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295 asm("subs r9, r6, r4 "); // subtract divisor from accumulator, result in r9,r3 |
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296 asm("sbcs r3, r7, r5 "); |
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297 asm("movccs r8, r8, lsr #1 "); // if borrow, check for carry from shift |
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298 asm("movcs r6, r9 "); // if no borrow, replace accumulator with result |
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299 asm("movcs r7, r3 "); |
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300 asm("adcs r1, r1, r1 "); // shift in new result bit |
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301 asm("adds r6, r6, r6 "); // shift accumulator left by one |
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302 asm("adcs r7, r7, r7 "); |
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303 asm("adcs r8, r8, r8 "); |
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304 asm("subs r9, r6, r4 "); // subtract divisor from accumulator, result in r9,r3 |
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305 asm("sbcs r3, r7, r5 "); |
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306 asm("movccs r8, r8, lsr #1 "); // if borrow, check for carry from shift |
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307 asm("movcs r6, r9 "); // if no borrow, replace accumulator with result |
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308 asm("movcs r7, r3 "); |
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309 asm("adcs r1, r1, r1 "); // shift in new result bit |
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310 asm("adds r6, r6, r6 "); // shift accumulator left by one |
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311 asm("adcs r7, r7, r7 "); |
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312 asm("adcs r8, r8, r8 "); |
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313 asm("subs r9, r6, r4 "); // subtract divisor from accumulator, result in r9,r3 |
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314 asm("sbcs r3, r7, r5 "); |
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315 asm("movccs r8, r8, lsr #1 "); // if borrow, check for carry from shift |
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316 asm("movcs r6, r9 "); // if no borrow, replace accumulator with result |
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317 asm("movcs r7, r3 "); |
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318 asm("adcs r1, r1, r1 "); // shift in new result bit |
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319 asm("subs r12, r12, #1 "); |
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320 asm("bne TRealXDivide5a "); // iterate the loop |
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321 |
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322 // r2:r1 now contains a 64-bit normalised mantissa |
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323 // need to do rounding now |
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324 asm("and r3, lr, #1 "); // result sign back into r3 |
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325 asm("orrs r9, r6, r7 "); // check if accumulator zero |
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326 asm("beq TRealXDivide6 "); // if it is, result is exact, else generate next bit |
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327 asm("adds r6, r6, r6 "); // shift accumulator left by one |
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328 asm("adcs r7, r7, r7 "); |
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329 asm("adcs r8, r8, r8 "); |
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330 asm("subs r6, r6, r4 "); // subtract divisor from accumulator |
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331 asm("sbcs r7, r7, r5 "); |
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332 asm("movccs r8, r8, lsr #1 "); // if borrow, check for carry from shift |
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333 asm("orrcc r3, r3, #0x100 "); // if borrow, round down and set round-down flag |
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334 asm("bcc TRealXDivide6 "); |
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335 asm("orrs r9, r6, r7 "); // if no borrow, check if exactly half-way |
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336 asm("moveqs r9, r1, lsr #1 "); // if exactly half-way, round to even |
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337 asm("orrcc r3, r3, #0x100 "); // if C=0, round result down and set round-down flag |
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338 asm("bcc TRealXDivide6 "); |
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339 asm("orr r3, r3, #0x200 "); // else set round-up flag |
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340 asm("adds r1, r1, #1 "); // and round mantissa up |
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341 asm("adcs r2, r2, #0 "); |
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342 asm("movcs r2, #0x80000000 "); // if carry, mantissa = 80000000 00000000 |
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343 asm("addcs r0, r0, #1 "); // and increment exponent |
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344 |
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345 // check for overflow or underflow and assemble final result |
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346 asm("TRealXDivide6: "); |
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347 asm("add r4, r0, #1 "); // need to add 1 to get usable threshold |
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348 asm("cmp r4, #0x10000 "); // check if exponent >= 0xFFFF |
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349 asm("bge TRealXMultiply6 "); // if so, overflow |
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350 asm("cmp r0, #0 "); // check for underflow |
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351 asm("orrgt r3, r3, r0, lsl #16 "); // if no underflow, result exponent into r3, ... |
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352 asm("movgt r12, #0 "); // ... return KErrNone ... |
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353 __JUMP(gt,lr); |
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354 |
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355 // underflow |
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356 asm("and r3, r3, #1 "); // set exponent=0, keep sign |
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357 asm("mvn r12, #9 "); // return KErrUnderflow |
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358 __JUMP(,lr); |
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359 |
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360 // come here if divisor is zero, dividend finite |
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361 asm("TRealXDivide3: "); |
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362 asm("cmp r3, #0x10000 "); // check if dividend also zero |
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363 asm("bcc TRealXRealIndefinite "); // if so, return 'real indefinite' |
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364 asm("orr r3, r3, #0xFF000000 "); // else return infinity with xor sign |
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365 asm("orr r3, r3, #0x00FF0000 "); |
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366 asm("mov r2, #0x80000000 "); |
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367 asm("mov r1, #0 "); |
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368 asm("mvn r12, #40 "); // return KErrDivideByZero |
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369 __JUMP(,lr); |
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370 |
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371 // Dividend is NaN or infinity |
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372 asm("TRealXDivide1: "); |
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373 asm("cmp r2, #0x80000000 "); // check for infinity |
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374 asm("cmpeq r1, #0 "); |
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375 asm("bne TRealXBinOpNan "); // branch if NaN |
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376 asm("cmn r6, #0x10000 "); // check 2nd operand for NaN/infinity |
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377 asm("mvncc r12, #8 "); // if not, return KErrOverflow |
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378 __JUMP(cc,lr); |
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379 |
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380 // Dividend=infinity, divisor=NaN or infinity |
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381 asm("cmp r5, #0x80000000 "); // check 2nd operand for infinity |
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382 asm("cmpeq r4, #0 "); |
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383 asm("bne TRealXBinOpNan "); // branch if NaN |
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384 asm("b TRealXRealIndefinite "); // else return 'real indefinite' |
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385 |
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386 // Divisor is NaN or infinity, dividend finite |
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387 asm("TRealXDivide2: "); |
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388 asm("cmp r5, #0x80000000 "); // check for infinity |
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389 asm("cmpeq r4, #0 "); |
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390 asm("bne TRealXBinOpNan "); // branch if NaN |
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391 asm("and r3, r3, #1 "); // else return zero with xor sign |
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392 __JUMP(,lr); |
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393 |
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394 asm("TRealXBinOpNan: "); // generic routine to process NaNs in binary |
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395 // operations |
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396 asm("cmn r3, #0x10000 "); // check if first operand is NaN |
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397 asm("movcc r0, r1 "); // if not, swap the operands |
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398 asm("movcc r1, r4 "); |
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399 asm("movcc r4, r0 "); |
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400 asm("movcc r0, r2 "); |
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401 asm("movcc r2, r5 "); |
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402 asm("movcc r5, r0 "); |
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403 asm("movcc r0, r3 "); |
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404 asm("movcc r3, r6 "); |
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405 asm("movcc r6, r0 "); |
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406 asm("cmn r6, #0x10000 "); // both operands NaNs? |
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407 asm("bcc TRealXBinOpNan1 "); // skip if not |
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408 asm("cmp r2, r5 "); // if so, compare the significands |
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409 asm("cmpeq r1, r4 "); |
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410 asm("movcc r1, r4 "); // r1,r2,r3 will get NaN with larger significand |
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411 asm("movcc r2, r5 "); |
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412 asm("movcc r3, r6 "); |
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413 asm("TRealXBinOpNan1: "); |
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414 asm("orr r2, r2, #0x40000000 "); // convert an SNaN to a QNaN |
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415 asm("mvn r12, #5 "); // return KErrArgument |
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416 __JUMP(,lr); |
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417 |
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418 // Return 'real indefinite' |
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419 asm("TRealXRealIndefinite: "); |
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420 asm("ldr r3, __RealIndefiniteExponent "); |
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421 asm("mov r2, #0xC0000000 "); |
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422 asm("mov r1, #0 "); |
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423 asm("mvn r12, #5 "); // return KErrArgument |
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424 __JUMP(,lr); |
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425 |
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426 // overflow |
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427 asm("TRealXMultiply6: "); |
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428 asm("bic r3, r3, #0x0000FF00 "); // clear rounding flags |
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429 asm("orr r3, r3, #0xFF000000 "); // make exponent FFFF for infinity |
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430 asm("orr r3, r3, #0x00FF0000 "); |
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431 asm("mov r2, #0x80000000 "); // mantissa = 80000000 00000000 |
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432 asm("mov r1, #0 "); |
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433 asm("mvn r12, #8 "); // return KErrOverflow |
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434 __JUMP(,lr); |
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435 |
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436 asm("__RealIndefiniteExponent: "); |
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437 asm(".word 0xFFFF0001 "); |
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438 |
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439 asm("Divide__FR6TRealXRC6TRealX_end: "); |
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440 } |
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441 |
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442 __NAKED__ TUint Divide_Length() |
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443 { |
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444 asm("adr r0, Divide__FR6TRealXRC6TRealX_end "); |
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445 asm("adr r1, Divide__FR6TRealXRC6TRealX "); |
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446 asm("sub r0, r0, r1 "); |
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447 __JUMP(,lr); |
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448 } |
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449 |
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450 __NAKED__ TInt SDummy(TInt) |
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451 { |
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452 __JUMP(,lr); |
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453 asm("SDummy__Fi_end: "); |
|
454 } |
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455 |
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456 __NAKED__ TUint SDummy_Length() |
|
457 { |
|
458 asm("adr r0, SDummy__Fi_end "); |
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459 asm("adr r1, SDummy__Fi "); |
|
460 asm("sub r0, r0, r1 "); |
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461 __JUMP(,lr); |
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462 } |
|
463 |
|
464 __NAKED__ TInt Increment(TInt) |
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465 { |
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466 asm("add r0, r0, #1 "); |
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467 __JUMP(,lr); |
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468 asm("Increment__Fi_end: "); |
|
469 } |
|
470 |
|
471 __NAKED__ TUint Increment_Length() |
|
472 { |
|
473 asm("adr r0, Increment__Fi_end "); |
|
474 asm("adr r1, Increment__Fi "); |
|
475 asm("sub r0, r0, r1 "); |
|
476 __JUMP(,lr); |
|
477 } |
|
478 |
|
479 #endif |