kerneltest/e32test/realtime/d_latncy.cia
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     1 // Copyright (c) 1999-2009 Nokia Corporation and/or its subsidiary(-ies).
       
     2 // All rights reserved.
       
     3 // This component and the accompanying materials are made available
       
     4 // under the terms of the License "Eclipse Public License v1.0"
       
     5 // which accompanies this distribution, and is available
       
     6 // at the URL "http://www.eclipse.org/legal/epl-v10.html".
       
     7 //
       
     8 // Initial Contributors:
       
     9 // Nokia Corporation - initial contribution.
       
    10 //
       
    11 // Contributors:
       
    12 //
       
    13 // Description:
       
    14 // e32test\realtime\d_latncy.cia
       
    15 // 
       
    16 //
       
    17 
       
    18 #include <platform.h>
       
    19 
       
    20 #if defined(__MEIG__)
       
    21 #include <cl7211.h>
       
    22 #elif defined(__MAWD__)
       
    23 #include <windermere.h>
       
    24 #elif defined(__MISA__)
       
    25 #include <sa1100.h>
       
    26 #elif defined(__MCOT__)
       
    27 #include <cotulla.h>
       
    28 #elif defined(__MI920__) || defined(__NI1136__)
       
    29 #include <integratorap.h>
       
    30 #elif defined(__RVEMUBOARD__)
       
    31 #include <rvemuboard.h>
       
    32 #endif
       
    33 
       
    34 #include <kernel/kern_priv.h>		//temporary
       
    35 #include "d_latncy.h"
       
    36 
       
    37 #if !defined(__SMP__)
       
    38 #if !defined(__EPOC32__) || !defined(__CPU_X86)
       
    39 __NAKED__ TUint IntStackPtr()
       
    40 	{
       
    41 	asm("mrs r1, cpsr ");
       
    42 	asm("bic r3, r1, #0x1f ");
       
    43 #ifdef __MISA__
       
    44 	asm("orr r3, r3, #0xd1 ");		// mode_fiq, all interrupts off
       
    45 #else
       
    46 	asm("orr r3, r3, #0xd2 ");		// mode_irq, all interrupts off
       
    47 #endif
       
    48 	asm("msr cpsr, r3 ");
       
    49 	asm("mov r0, sp ");				// r0=sp_irq or sp_fiq
       
    50 	asm("msr cpsr, r1 ");			// restore interrupts
       
    51 	__JUMP(,lr);
       
    52 	}
       
    53 #endif
       
    54 
       
    55 #ifdef __CAPTURE_EXTRAS
       
    56 #include <arm.h>
       
    57 
       
    58 __NAKED__ void CaptureExtras(SLatencyResults&)
       
    59 	{
       
    60 	asm("mrs r1, spsr ");			// r1=interrupted mode
       
    61 	asm("mrs r2, cpsr ");			// r2=current PSR
       
    62 	asm("tst r1, #0x0f ");			// check if we interrupted user mode
       
    63 	asm("orr ip, r1, #%a0" : : "i" ((TInt)KAllInterruptsMask));		// ip=interrupted mode with interrupts off
       
    64 	asm("orreq ip, ip, #0x1f ");	// if we interrupted user mode, go to system mode instead
       
    65 	asm("bic ip, ip, #0x20 ");		// make sure we don't go into THUMB mode
       
    66 	asm("msr cpsr, ip ");			// switch to interrupted mode with ints off
       
    67 	asm("mov r3, lr ");				// r3=interrupted mode R14
       
    68 	asm("msr cpsr, r2 ");			// back to interrupt mode
       
    69 	asm("str r1, [r0, #%a0]" : : "i" _FOFF(SLatencyResults,iIntSpsr));
       
    70 	asm("str r3, [r0, #%a0]" : : "i" _FOFF(SLatencyResults,iIntR14));
       
    71 	__JUMP(,lr);
       
    72 	}
       
    73 #endif
       
    74 #endif	// __SMP__
       
    75 
       
    76 #if defined (__MISA__) || defined (__MCOT__)
       
    77 __NAKED__ void DLatency::MsCallBack(TAny* aPtr)
       
    78 	{
       
    79 	asm("ldr ip, __KHwBaseOst");
       
    80 	asm("ldr r3, [r0, #%a0]" : : "i" _FOFF(DLatency,iTickIncrement));
       
    81 	asm("ldr r1, [ip, #0x10] ");		// r1=OSCR
       
    82 	asm("ldr r2, [ip, #0x00] ");		// r2=OSMR0
       
    83 	asm("sub r1, r1, r2 ");				// r1=int latency in ticks
       
    84 	asm("str r1, [r0, #%a0]" : : "i" _FOFF(DLatency,iResults.iIntTicks));
       
    85 	asm("str r2, [r0, #%a0]" : : "i" _FOFF(DLatency,iTriggerTime));
       
    86 	asm("add r2, r2, r3 ");				// add increment to OSMR0
       
    87 	asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(DLatency,iIntStackTop));
       
    88 	asm("ldrb r3, [r0, #%a0]" : : "i" _FOFF(DLatency,iOff));
       
    89 	asm("str r2, [ip, #0x00] ");
       
    90 	asm("ldr r1, [r1, #-4] ");			// r1=interrupt return address
       
    91 	asm("mov r2, #1 ");
       
    92 	asm("cmp r3, #0 ");
       
    93 	asm("str r1, [r0, #%a0]" : : "i" _FOFF(DLatency,iResults.iIntRetAddr));
       
    94 	asm("str r2, [ip, #0x14] ");		// clear interrupt
       
    95 	asm("add r0, r0, #%a0" : : "i" _FOFF(DLatency,iMsDfc));
       
    96 	asm("beq Add__4TDfc ");
       
    97 	__JUMP(,lr);
       
    98 
       
    99 	asm("__KHwBaseOst: ");	//OS timer register locations
       
   100 #ifdef __MISA__
       
   101 	#ifdef __MEMMODEL_DIRECT__
       
   102 		asm(".word 0x90000000");		//Assabet direct MM
       
   103 	#else
       
   104 		asm(".word 0x63008000");		//Assabet non-direct MM
       
   105 	#endif
       
   106 #else
       
   107 	#ifdef __MEMMODEL_DIRECT__
       
   108 		asm(".word 0x40A00000");		//Lubbock direct MM
       
   109 	#else
       
   110 		asm(".word 0x6300A000");		//Lubbock non-direct MM
       
   111 	#endif
       
   112 #endif
       
   113 	}
       
   114 #endif
       
   115