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1 // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // template\template_assp\i2spsl.cpp |
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15 // |
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16 // |
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17 |
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18 #include <kernel/kernel.h> |
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19 #include <drivers/i2s.h> |
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20 |
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21 // TO DO: (mandatory) |
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22 // If your ASIC supports multiple I2S interfaces you need to design the most appropriate way of handling that: |
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23 // - it is possible that a common register per function is used on some of the functions, e.g. a single Control |
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24 // Register is used to select Master/Slave roles, Transmitter/Receiver/Bidirectional/Controller mode, word |
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25 // length etc for all interfaces supported. In this case handling the interface Id typically involves the use |
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26 // of shifts and masks; |
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27 // - some functions can never be covered by a single register common to all interfaces (e.g. the transmit/receive |
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28 // registers). Even if it was possible to use single registers to cover a number of interfaces the ASIC designer |
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29 // may decide to have separate registers for each interface. In this case each of the below APIs could be implemented |
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30 // as a switch(interface)-case and then use different sets of register addresses for each interface. This model makes |
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31 // sense when a single developer is responsible for implementing all interfaces (typically in a single source file). |
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32 // - when each interface is implemented independently it makes sense to separate the implementation into a interface |
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33 // independent layer and a specific layer and redirect each call from the interface independent layer into the relavant |
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34 // interface. This is exemplified with the NAVIENGINE implementation. |
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35 // |
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36 |
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37 enum TIs2Panic |
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38 { |
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39 ECalledFromIsr |
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40 }; |
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41 |
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42 EXPORT_C TInt I2s::ConfigureInterface(TInt aInterfaceId, TDes8* aConfig) |
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43 // |
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44 // Configures the interface: its type (Transmitter/Receiver/Bidirectional/Controller) and the role played by it (Master/Slave). |
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45 // |
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46 { |
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47 __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); |
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48 // TO DO: (mandatory) |
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49 // |
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50 // Extracts the configuration information from aConfig and programs the relevant registers for the interface identified by aInterfaceId. |
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51 // |
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52 return KErrNone; |
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53 } |
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54 |
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55 EXPORT_C TInt I2s::GetInterfaceConfiguration(TInt aInterfaceId, TDes8& aConfig) |
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56 // |
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57 // Reads the current configuration. |
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58 // |
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59 { |
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60 __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); |
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61 // TO DO: (optional) |
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62 // |
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63 // Reads the relevant registers and assembles configuration information to be returned in aConfig. |
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64 // |
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65 return KErrNotSupported; |
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66 } |
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67 |
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68 EXPORT_C TInt I2s::SetSamplingRate(TInt aInterfaceId, TI2sSamplingRate aSamplingRate) |
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69 // |
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70 // Sets the sampling rate. |
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71 // |
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72 { |
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73 __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); |
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74 // TO DO: (mandatory) |
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75 // |
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76 // Programs the required sampling rate onto the relevant registers for the interface identified by aInterfaceId . |
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77 // |
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78 return KErrNone; |
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79 } |
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80 |
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81 EXPORT_C TInt I2s::GetSamplingRate(TInt aInterfaceId, TInt& aSamplingRate) |
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82 // |
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83 // Reads the sampling rate. |
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84 // |
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85 { |
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86 __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); |
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87 // TO DO: (optional) |
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88 // |
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89 // Reads the relevant registers to obtain the currently programmed sampling rate to be returned in aSamplingRate. |
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90 // |
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91 return KErrNotSupported; |
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92 } |
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93 |
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94 EXPORT_C TInt I2s::SetFrameLengthAndFormat(TInt aInterfaceId, TI2sFrameLength aFrameLength, TInt aLeftFramePhaseLength) |
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95 // |
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96 // Sets the frame format. |
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97 // |
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98 { |
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99 __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); |
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100 // TO DO: (mandatory) |
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101 // |
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102 // If the interface only allows symmetrical frame lengths this function programs the required |
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103 // overall frame length onto the relevant registers for the interface identified by aInterfaceId. |
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104 // In this case aLeftFramePhaseLength can be ignored. |
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105 // If the interface supports asymmetrical frame lengths, calculates the righ frame length as |
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106 // (aFrameLength-aLeftFramePhaseLength) and programs both the left and right frame lengths onto |
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107 // the relevant registers for the interface identified by aInterfaceId. |
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108 // |
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109 return KErrNone; |
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110 } |
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111 |
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112 EXPORT_C TInt I2s::GetFrameFormat(TInt aInterfaceId, TInt& aLeftFramePhaseLength, TInt& aRightFramePhaseLength) |
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113 // |
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114 // Reads the frame format. |
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115 // |
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116 { |
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117 __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); |
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118 // TO DO: (optional) |
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119 // |
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120 // If the interface only supports symmetrical frame lengths this function reads the relevant registers to obtain |
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121 // the currently programmed overall frame length for the interface identified by aInterfaceId: it returns the same |
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122 // value in both aLeftFramePhaseLength and aRightFramePhaseLength (that is overal frame length/2). |
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123 // If the interface supports asymmetrical frame lngths, reads the appropriate registers to obtain the left and right |
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124 // frame lengths to be returned in aLeftFramePhaseLength and aRightFramePhaseLength. |
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125 // |
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126 return KErrNotSupported; |
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127 } |
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128 |
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129 EXPORT_C TInt I2s::SetSampleLength(TInt aInterfaceId, TI2sFramePhase aFramePhase, TI2sSampleLength aSampleLength) |
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130 // |
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131 // Sets the sample length for a frame phase. |
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132 // |
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133 { |
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134 __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); |
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135 // TO DO: (mandatory) |
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136 // |
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137 // Programs the required sample length for the frame phase specified (left or right) onto the relevant registers for the interface identified by aInterfaceId . |
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138 // |
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139 return KErrNone; |
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140 } |
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141 |
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142 EXPORT_C TInt I2s::GetSampleLength(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt& aSampleLength) |
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143 // |
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144 // Reads the sample length for a frame phase. |
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145 // |
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146 { |
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147 __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); |
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148 // TO DO: (optional) |
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149 // |
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150 // Reads the relevant registers to obtain the sample length for the frame phase specified (left or right) to be returned in aSampleLength. |
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151 // |
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152 return KErrNotSupported; |
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153 } |
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154 |
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155 EXPORT_C TInt I2s::SetDelayCycles(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt aDelayCycles) |
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156 // |
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157 // Sets the number of delay cycles for a frame phase. |
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158 // |
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159 { |
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160 __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); |
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161 // TO DO: (optional) |
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162 // |
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163 // If the interface supports delaying the start of a frame by a specified number of bit clock cycles this function programs the required |
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164 // delay cycles for the frame phase specified (left or right) onto the relevant registers for the interface identified by aInterfaceId . |
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165 // |
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166 return KErrNotSupported; |
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167 } |
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168 |
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169 EXPORT_C TInt I2s::GetDelayCycles(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt& aDelayCycles) |
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170 // |
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171 // Reads the sample length for a frame phase. |
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172 // |
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173 { |
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174 __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); |
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175 // TO DO: (optional) |
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176 // |
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177 // If the interface supports delaying the start of a frame by a specified number of bit clock cycles this function reads the relevant |
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178 // registers to obtain the number of delay cycles for the frame phase specified (left or right) to be returned in aSampleLength. |
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179 // |
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180 return KErrNotSupported; |
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181 } |
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182 |
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183 EXPORT_C TInt I2s::ReadReceiveRegister(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt& aData) |
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184 // |
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185 // Reads the receive data register for a frame phase. |
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186 // |
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187 { |
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188 // TO DO: (mandatory) |
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189 // |
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190 // Reads the contents of the receive register to obtain the data for the frame phase specified (left or right) to be returned in aData. |
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191 // If the implementation only supports a single receive register for both frame phases, the aFramePhase argument can be ignored and the |
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192 // function returns the contents of the single register. |
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193 // |
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194 return KErrNone; |
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195 } |
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196 |
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197 EXPORT_C TInt I2s::WriteTransmitRegister(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt aData) |
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198 // |
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199 // Writes to the transmit data register for a frame phase. |
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200 // |
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201 { |
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202 // TO DO: (mandatory) |
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203 // |
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204 // Writes the Audio data passed in aData to the transmit register for the frame phase specified (left or right) for the interface identified |
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205 // by aInterfaceId. |
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206 // If the implementation only supports a single transmit register for both frame phases, the aFramePhase argument can be ignored and the |
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207 // function writes to the single register. |
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208 // |
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209 return KErrNone; |
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210 } |
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211 |
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212 EXPORT_C TInt I2s::ReadTransmitRegister(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt& aData) |
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213 // |
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214 // Reads the transmit data register for a frame phase. |
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215 // |
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216 { |
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217 // TO DO: (optional) |
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218 // |
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219 // Reads the contents of the transmit register to obtain the data for the frame phase specified (left or right) to be returned in aData. |
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220 // If the implementation only supports a single receive register for both frame phases, the aFramePhase argument can be ignored and the |
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221 // function returns the contents of the single transmit register. |
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222 // If the implementation does not support reading the transmit register simply return KErrNotSupported. |
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223 // |
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224 return KErrNotSupported; |
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225 } |
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226 |
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227 EXPORT_C TInt I2s::ReadRegisterModeStatus(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt& aFlags) |
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228 // |
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229 // Reads the Register PIO access mode status flags for a frame phase. |
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230 // |
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231 { |
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232 // TO DO: (optional) |
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233 // |
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234 // If the implementation supports Register PIO mode this function reads the contents of the Register PIO mode status register to obtain |
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235 // the status flags for the frame phase specified (left or right) to be returned in aFlags. The mode flags are described in TI2sFlags. |
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236 // If the implementation does not support Register PIO mode simply return KErrNotSupported. |
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237 // |
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238 return KErrNotSupported; |
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239 } |
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240 |
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241 EXPORT_C TInt I2s::EnableRegisterInterrupts(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt aInterrupt) |
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242 // |
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243 // Enables Register PIO access mode related interrupts for a frame phase. |
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244 // |
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245 { |
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246 __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); |
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247 // TO DO: (optional) |
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248 // |
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249 // If the implementation supports Register PIO mode this function enables the mode interrupts specified by the bitmask aInterrupt |
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250 // for the frame phase specified (left or right). The mode interrupts are described in TI2sFlags. Bits set to "1" enable the |
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251 // corresponding interrupts |
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252 // If the implementation only supports a single transmit register for both frame phases, the aFramePhase argument can be ignored. |
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253 // If the implementation does not support Register PIO mode simply return KErrNotSupported. |
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254 // |
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255 return KErrNotSupported; |
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256 } |
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257 |
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258 EXPORT_C TInt I2s::DisableRegisterInterrupts(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt aInterrupt) |
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259 // |
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260 // Disables Register PIO access mode related interrupts for a frame phase. |
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261 // |
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262 { |
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263 __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); |
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264 // TO DO: (optional) |
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265 // |
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266 // If the implementation supports Register PIO mode this function disables the mode interrupts specified by the bitmask aInterrupt |
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267 // for the frame phase specified (left or right). The mode interrupts are described in TI2sFlags. Bits set to "1" disable the |
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268 // corresponding interrupts |
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269 // If the implementation only supports a single transmit register for both frame phases, the aFramePhase argument can be ignored. |
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270 // If the implementation does not support Register PIO mode simply return KErrNotSupported. |
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271 // |
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272 return KErrNotSupported; |
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273 } |
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274 |
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275 EXPORT_C TInt I2s::IsRegisterInterruptEnabled(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt& aEnabled) |
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276 // |
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277 // Reads the Register PIO access mode interrupt mask for a frame phase. |
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278 // |
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279 { |
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280 // TO DO: (optional) |
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281 // |
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282 // If the implementation supports Register PIO mode this function reads the relevant registers to find out which mode interrupts |
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283 // are enabled for the frame phase specified (left or right), and returns a bitmask of enabled interrupts in aEnabled. |
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284 // The mode interrupts are described in TI2sFlags. A bit set to "1" indicates the corresponding interrupt is enabled |
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285 // If the implementation only supports a single transmit register for both frame phases, the aFramePhase argument can be ignored. |
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286 // If the implementation does not support Register PIO mode simply return KErrNotSupported. |
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287 // |
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288 return KErrNotSupported; |
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289 } |
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290 |
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291 EXPORT_C TInt I2s::EnableFIFO(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt aFifoMask) |
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292 // |
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293 // Enables receive and/or transmit FIFO on a per frame phase basis. |
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294 // |
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295 { |
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296 __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); |
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297 // TO DO: (optional) |
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298 // |
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299 // If the implementation supports FIFO mode this function enables the FIFOs for the directions specified in the bitmask aFifoMask |
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300 // (Transmit and/or Receive) for the frame phase specified (left or right). Bits set to "1" enable the corresponding FIFO. |
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301 // If the implementation has a combined receive/transmit FIFO - half duplex operation only - then aFifoMask can be ignored. |
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302 // If the implementation only supports a single FIFO for both frame phases then aFramePhase can be ignored. |
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303 // |
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304 return KErrNotSupported; |
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305 } |
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306 |
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307 EXPORT_C TInt I2s::DisableFIFO(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt aFifoMask) |
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308 // |
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309 // Disables receive and/or transmit FIFO on a per frame phase basis. |
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310 // |
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311 { |
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312 __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); |
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313 // TO DO: (optional) |
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314 // |
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315 // If the implementation supports FIFO mode this function disables the FIFOs for the directions specified in the bitmask aFifoMask |
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316 // (Transmit and/or Receive) for the frame phase specified (left or right). Bits set to "1" disable the corresponding FIFO. |
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317 // If the implementation has a combined receive/transmit FIFO - half duplex operation only - then aFifoMask can be ignored. |
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318 // If the implementation only supports a single FIFO for both frame phases then aFramePhase can be ignored. |
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319 // |
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320 return KErrNotSupported; |
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321 } |
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322 |
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323 EXPORT_C TInt I2s::IsFIFOEnabled(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt& aEnabled) |
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324 // |
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325 // Reads the enabled state of a frame phase's FIFOs. |
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326 // |
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327 { |
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328 __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); |
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329 // TO DO: (optional) |
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330 // |
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331 // If the implementation supports FIFO mode this function reads the relevant registers to find out which FIFOs |
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332 // are enabled (Transmit and/or Receive FIFO) for the frame phase specified (left or right), and returns a bitmask of enabled FIFOs in aEnabled. |
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333 // The mode interrupts are described in TI2sFlags. A bit set to "1" indicates the corresponding interrupt is enabled |
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334 // If the implementation has a combined receive/transmit FIFO then aEnabled should have both Rx and Tx bits set when the FIFO is enabled. |
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335 // If the implementation only supports a single FIFO for both frame phases then aFramePhase is ignore. |
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336 // |
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337 return KErrNotSupported; |
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338 } |
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339 |
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340 EXPORT_C TInt I2s::SetFIFOThreshold(TInt aInterfaceId, TI2sFramePhase aFramePhase, TI2sDirection aDirection, TInt aThreshold) |
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341 // |
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342 // Sets the receive or transmit FIFO threshold on a per frame phase basis. |
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343 // |
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344 { |
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345 __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); |
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346 // TO DO: (optional) |
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347 // |
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348 // If the implementation supports FIFO mode this function sets the FIFO threshold for the direction specified in aDirection |
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349 // (Transmit or Receive) for the frame phase specified (left or right). |
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350 // If the implementation has a combined receive/transmit FIFO - half duplex operation only - then aDirection can be ignored. |
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351 // If the implementation only supports a single FIFO for both frame phases then aFramePhase can be ignored. |
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352 // |
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353 return KErrNotSupported; |
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354 } |
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355 |
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356 EXPORT_C TInt I2s::ReadFIFOModeStatus(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt& aFlags) |
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357 // |
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358 // Reads the FIFO PIO access mode status flags for a frame phase. |
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359 // |
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360 { |
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361 // TO DO: (optional) |
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362 // |
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363 // If the implementation supports FIFO mode this function reads the contents of the FIFO mode status register to obtain |
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364 // the status flags for the frame phase specified (left or right) to be returned in aFlags. The mode flags are described in TI2sFlags. |
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365 // A bit set to "1" indicates the condition described by the corresponding flag is occurring. |
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366 // If the implementation has a combined receive/transmit FIFO then aFlags should be set according to which operation (receive/transmit) is |
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367 // currently undergoing. |
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368 // If the implementation only supports a single FIFO for both frame phases then aFramePhase is ignored. |
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369 // |
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370 return KErrNotSupported; |
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371 } |
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372 |
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373 EXPORT_C TInt I2s::EnableFIFOInterrupts(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt aInterrupt) |
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374 // |
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375 // Enables FIFO related interrupts for a frame phase. |
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376 // |
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377 { |
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378 __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); |
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379 // TO DO: (optional) |
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380 // |
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381 // If the implementation supports FIFO mode this function enables the mode interrupts specified by the bitmask aInterrupt |
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382 // for the frame phase specified (left or right). The mode interrupts are described in TI2sFlags. Bits set to "1" enable the |
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383 // corresponding interrupts |
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384 // If the implementation only supports a single transmit FIFO for both frame phases, the aFramePhase argument can be ignored. |
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385 // |
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386 return KErrNotSupported; |
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387 } |
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388 |
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389 EXPORT_C TInt I2s::DisableFIFOInterrupts(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt aInterrupt) |
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390 // |
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391 // Disables FIFO related interrupts for a frame phase. |
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392 // |
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393 { |
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394 __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); |
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395 // TO DO: (optional) |
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396 // |
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397 // If the implementation supports FIFO mode this function disables the mode interrupts specified by the bitmask aInterrupt |
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398 // for the frame phase specified (left or right). The mode interrupts are described in TI2sFlags. Bits set to "1" disable the |
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399 // corresponding interrupts |
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400 // If the implementation only supports a single transmit FIFO for both frame phases, the aFramePhase argument can be ignored. |
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401 // |
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402 return KErrNotSupported; |
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403 } |
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404 |
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405 EXPORT_C TInt I2s::IsFIFOInterruptEnabled(TInt aInterfaceId, TI2sFramePhase aFramePhase, TInt& aEnabled) |
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406 // |
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407 // Reads the FIFO interrupt masks for a frame phase. |
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408 // |
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409 { |
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410 // TO DO: (optional) |
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411 // |
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412 // If the implementation supports FIFO mode this function reads the relevant registers to find out which mode interrupts |
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413 // are enabled for the frame phase specified (left or right), and returns a bitmask of enabled interrupts in aEnabled. |
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414 // The mode interrupts are described in TI2sFlags. A bit set to "1" indicates the corresponding interrupt is enabled |
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415 // If the implementation only supports a single transmit FIFO for both frame phases, the aFramePhase argument can be ignored. |
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416 // |
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417 return KErrNotSupported; |
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418 } |
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419 |
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420 EXPORT_C TInt I2s::ReadFIFOLevel(TInt aInterfaceId, TI2sFramePhase aFramePhase, TI2sDirection aDirection, TInt& aLevel) |
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421 // |
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422 // Reads the receive or transmit FIFO current level on a per frame phase basis. |
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423 // |
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424 { |
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425 __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); |
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426 // TO DO: (optional) |
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427 // |
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428 // If the implementation supports FIFO mode this function reads the relevant registers to find out the current FIFO level |
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429 // for the direction specified and for the frame phase specified (left or right), and returns it in aLevel. |
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430 // If the implementation has a combined receive/transmit FIFO then aDirection is ignored. |
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431 // If the implementation only supports a single transmit FIFO for both frame phases, the aFramePhase argument can be ignored. |
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432 // |
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433 return KErrNotSupported; |
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434 } |
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435 |
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436 EXPORT_C TInt I2s::EnableDMA(TInt aInterfaceId, TInt aFifoMask) |
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437 // |
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438 // Enables receive and/or transmit DMA. |
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439 // |
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440 { |
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441 __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); |
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442 // TO DO: (optional) |
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443 // |
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444 // If the implementation supports FIFO DMA mode this function enables DMA in the directions (Transmit and/or Receive) specified |
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445 // by the bitmask aFifoMask for the frame phase specified (left or right). Bits set to "1" enable DMA. |
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446 // If the implementation has a combined receive/transmit FIFO then aFifoMask can be ignored. |
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447 // |
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448 return KErrNotSupported; |
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449 } |
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450 |
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451 EXPORT_C TInt I2s::DisableDMA(TInt aInterfaceId, TInt aFifoMask) |
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452 // |
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453 // Disables receive and/or transmit DMA. |
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454 // |
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455 { |
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456 __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); |
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457 // TO DO: (optional) |
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458 // |
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459 // If the implementation supports FIFO DMA mode this function disables DMA in the directions (Transmit and/or Receive) specified |
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460 // by the bitmask aFifoMask for the frame phase specified (left or right). Bits set to "1" disable DMA. |
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461 // If the implementation has a combined receive/transmit FIFO then aFifoMask can be ignored. |
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462 // |
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463 return KErrNotSupported; |
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464 } |
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465 |
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466 EXPORT_C TInt I2s::IsDMAEnabled(TInt aInterfaceId, TInt& aEnabled) |
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467 // |
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468 // Reads the enabled state of DMA. |
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469 // |
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470 { |
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471 __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); |
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472 // TO DO: (optional) |
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473 // |
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474 // If the implementation supports FIFO DMA mode this function reads the relevant registers to find out which directions |
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475 // (Transmit and/or Receive) DMA is enabled for the frame phase specified (left or right), and returns a bitmask of enabled |
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476 // directions in aEnabled. A bit set to "1" indicates DMA is enabled for the corresponding direction. |
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477 // If the implementation has a combined receive/transmit FIFO then aEnabled should have both Rx and Tx bits set when the DMA is enabled. |
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478 // |
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479 return KErrNotSupported; |
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480 } |
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481 |
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482 EXPORT_C TInt I2s::Start(TInt aInterfaceId, TInt aDirection) |
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483 // |
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484 // Starts data transmission and/or data reception unless interface is a Controller; |
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485 // if the device is also a Master, starts generation of data synchronisation signals. |
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486 // |
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487 { |
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488 __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); |
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489 // TO DO: (optional) |
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490 // |
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491 // Programs the appropriate registers to start operation in the direction specified by aDirection. |
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492 // Should check if the interface has been configured coherently. |
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493 // |
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494 return KErrNotSupported; |
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495 } |
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496 |
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497 EXPORT_C TInt I2s::Stop(TInt aInterfaceId, TInt aDirection) |
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498 // |
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499 // Stops data transmission and/or data reception; |
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500 // if device is also a Master, stops generation of data synchronisation signals. |
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501 // |
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502 { |
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503 __ASSERT_DEBUG(NKern::CurrentContext() == NKern::EThread, Kern::Fault("I2s Interface", ECalledFromIsr)); |
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504 // TO DO: (optional) |
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505 // |
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506 // If the interface has been started, programs the appropriate registers to stop operation in the direction specified by aDirection. |
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507 // |
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508 return KErrNotSupported; |
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509 } |
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510 |
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511 EXPORT_C TInt I2s::IsStarted(TInt aInterfaceId, TI2sDirection aDirection, TBool& aStarted) |
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512 // |
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513 // Checks if a transmission or a reception is underway. |
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514 // |
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515 { |
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516 // TO DO: (optional) |
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517 // |
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518 // Reads the appropriate registers to check if the interface speficied by aInterfaceId is started in the direction |
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519 // specified by aDirection. Returns teh result (as TRUE or FALSE) in aStarted. |
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520 // If the interface is a Controller and a bus operation is underway, ETrue should be returned regardless of aDirection. |
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521 // |
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522 return KErrNotSupported; |
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523 } |
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524 |
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525 // dll entry point.. |
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526 DECLARE_STANDARD_EXTENSION() |
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527 { |
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528 // TO DO: (optional) |
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529 // |
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530 // The Kernel extension entry point: if your interface requires any early intialisation do it here. |
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531 // |
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532 return KErrNone; |
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533 } |