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1 // Copyright (c) 1997-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // template\template_assp\template_assp.h |
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15 // Definitions for Template ASSP |
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16 // |
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17 // WARNING: This file contains some APIs which are internal and are subject |
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18 // to change without notice. Such APIs should therefore not be used |
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19 // outside the Kernel and Hardware Services package. |
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20 // |
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21 |
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22 #ifndef __A32TEMPLATEV1_H__ |
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23 #define __A32TEMPLATEV1_H__ |
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24 #include <e32const.h> |
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25 #include <platform.h> |
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26 #include <e32hal.h> |
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27 #include <assp.h> |
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28 #include <kernel/kern_priv.h> |
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29 |
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30 //---------------------------------------------------------------------------- |
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31 // Constant conventions: |
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32 //---------------------------------------------------------------------------- |
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33 |
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34 // KH Hardware definition |
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35 // KHw 4-byte word definition prefix |
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36 // KHb Byte definition prefix |
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37 // KHt Bit definition prefix |
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38 // KHm Mask definition prefix |
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39 // KHs Shift definition prefix |
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40 // KHo Offset definition prefix |
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41 // KHwRo Read-only register |
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42 // KHwWo Write-only register |
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43 // KHwRw Read/write register |
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44 // KHwBase Base address within memory map |
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45 // _i Input suffix |
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46 // _o Output suffix |
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47 // _b Input/output suffix |
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48 |
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49 //---------------------------------------------------------------------------- |
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50 // Memory map: physical addresses |
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51 //---------------------------------------------------------------------------- |
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52 // NB: these are just examples |
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53 |
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54 const TUint KHwBaseCs0 = 0x00000000; |
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55 const TUint KHwBaseCs1 = KHwBaseCs0 + 128*KMega; |
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56 const TUint KHwBaseCs2 = KHwBaseCs1 + 128*KMega; |
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57 const TUint KHwBaseCs3 = KHwBaseCs2 + 128*KMega; |
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58 |
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59 const TUint KHwBaseMemBank0 = 0x20000000; |
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60 const TUint KHwBaseMemBank1 = KHwBaseMemBank0 + 256*KMega; |
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61 |
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62 const TUint KHwBaseRegisters = 0x80000000; |
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63 const TUint KHwBasePeripherals = KHwBaseRegisters; // 8000.0000 |
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64 const TUint KHwBasePeripheralsA = KHwBasePeripherals + 256*KMega; // 9000.0000 |
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65 const TUint KHwBasePeripheralsB = KHwBasePeripheralsA + 256*KMega; // A000.0000 |
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66 const TUint KHwBasePeripheralsC = KHwBasePeripheralsB + 256*KMega; // B000.0000 |
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67 |
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68 // etc... |
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69 |
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70 //---------------------------------------------------------------------------- |
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71 // Memory map: linear addresses |
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72 //---------------------------------------------------------------------------- |
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73 |
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74 #if defined (__MEMMODEL_MULTIPLE__) |
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75 const TUint KHwLinBaseRegisters = 0xc6000000; // as mapped by bootstrap |
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76 const TUint KHwLinSeparation = 0x1000; |
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77 #elif defined(__MEMMODEL_DIRECT__) |
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78 const TUint KHwLinBaseRegisters = 0x10000000; // physical address (example only) |
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79 const TUint KHwLinSeparation = 0x01000000; // physical offsets (example only) |
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80 #else |
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81 const TUint KHwLinBaseRegisters = 0x63000000; // as mapped by bootstrap |
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82 const TUint KHwLinSeparation = 0x1000; |
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83 #endif |
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84 |
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85 // EXAMPLE ONLY: |
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86 const TUint KHwLinBasePeriphGroupA = KHwLinBaseRegisters; |
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87 const TUint KHwLinBasePeripheral1 = KHwLinBasePeriphGroupA + 0x00*KHwLinSeparation; |
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88 const TUint KHwLinBasePeripheral2 = KHwLinBasePeriphGroupA + 0x01*KHwLinSeparation; |
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89 const TUint KHwLinBasePeripheral3 = KHwLinBasePeriphGroupA + 0x02*KHwLinSeparation; |
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90 const TUint KHwLinBasePeripheral4 = KHwLinBasePeriphGroupA + 0x03*KHwLinSeparation; |
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91 |
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92 const TUint KHwLinBasePeriphGroupB = KHwLinBaseRegisters + 0x20*KHwLinSeparation; |
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93 |
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94 const TUint KHwBaseSerial1 = KHwLinBasePeriphGroupB + 0x00*KHwLinSeparation; |
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95 const TUint KHwBaseSerial2 = KHwLinBasePeriphGroupB + 0x01*KHwLinSeparation; |
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96 const TUint KHwBaseSerial3 = KHwLinBasePeriphGroupB + 0x02*KHwLinSeparation; |
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97 |
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98 const TUint KHwLinBasePeriphGroupC = KHwLinBaseRegisters + 0x30*KHwLinSeparation; |
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99 |
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100 const TUint KHwBaseInterrupts = KHwLinBasePeriphGroupC + 0x00*KHwLinSeparation; |
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101 const TUint KHwInterruptsMaskRo = KHwBaseInterrupts + 0x00; |
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102 const TUint KHwInterruptsMaskSet = KHwBaseInterrupts + 0x04; |
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103 const TUint KHwInterruptsMaskClear = KHwBaseInterrupts + 0x08; |
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104 const TUint KHoInterruptsIrqPending = 0x0C; |
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105 const TUint KHwInterruptsIrqPending = KHwBaseInterrupts + KHoInterruptsIrqPending; |
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106 const TUint KHoInterruptsFiqPending = 0x10; |
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107 const TUint KHwInterruptsFiqending = KHwBaseInterrupts + KHoInterruptsFiqPending; |
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108 |
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109 |
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110 // Other device specifc constants, register offsets, bit masks, general-purpose I/O allocations, |
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111 // interrupt sources, Memory settings and geometries, etc |
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112 |
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113 |
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114 class TTemplate |
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115 { |
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116 /** |
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117 * Accessor functions to hardware resources managed by ASSP (ASIC). Auxiliary and information functions which |
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118 * are commonly used by Device Drivers or ASSP/Variant code. |
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119 * Some examples below. These examples assume that the hardware blocks they access (e.g. Interrupt controller |
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120 * RTC, Clock Control Module, UART, etc) are part of the ASSP. |
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121 */ |
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122 public: |
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123 /** |
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124 * initialisation |
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125 */ |
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126 static void Init3(); |
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127 /** |
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128 * Active waiting loop (not to be used after System Tick timer has been set up - Init3() |
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129 * @param aDuration A wait time in milliseconds |
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130 */ |
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131 IMPORT_C static void BootWaitMilliSeconds(TInt aDuration); |
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132 /** |
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133 * Read and return the Startup reason of the Hardware |
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134 * @return A TMachineStartupType enumerated value |
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135 */ |
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136 IMPORT_C static TMachineStartupType StartupReason(); |
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137 /** |
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138 * Read and return the the CPU ID |
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139 * @return An integer containing the CPU ID string read off the hardware |
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140 */ |
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141 IMPORT_C static TInt CpuVersionId(); |
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142 /** |
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143 * Read Linear base address of debug UART (as selected in obey file or with eshell debugport command). |
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144 * @return An integer containing the Linear address of debug Serial Port |
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145 */ |
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146 IMPORT_C static TUint DebugPortAddr(); |
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147 /** |
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148 * Read CPU clock period in picoseconds |
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149 * @return An integer containing the CPU clock period in picoseconds |
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150 */ |
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151 IMPORT_C static TUint ProcessorPeriodInPs(); |
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152 /** |
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153 * Set the Hardware Interrupt masks |
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154 * @param aValue A new interrupt mask value |
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155 */ |
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156 IMPORT_C static void SetIntMask(TUint aValue); |
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157 /** |
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158 * Modify the Hardware Interrupt masks |
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159 * @param aClearMask A mask with interrupt source bits to clear (disable) |
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160 * @param aSetMask A mask with interrupt source bits to set (enable) |
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161 */ |
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162 IMPORT_C static void ModifyIntMask(TUint aClearMask,TUint aSetMask); |
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163 /** |
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164 * Read the state of pending interrupts |
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165 * @return A mask containing bits set for all pending interrupts |
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166 */ |
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167 IMPORT_C static TUint IntsPending(); |
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168 /** |
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169 * Read the current time of the RTC |
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170 * @return A value that is the real time as given by a RTC |
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171 */ |
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172 IMPORT_C static TUint RtcData(); |
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173 /** |
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174 * Set the RTC time |
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175 * @param aValue The real time to set the RTC |
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176 */ |
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177 IMPORT_C static void SetRtcData(TUint aValue); |
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178 /** |
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179 * Obtain the physical start address of Video Buffer |
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180 * @return the physical start address of Video Buffer |
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181 */ |
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182 IMPORT_C static TPhysAddr VideoRamPhys(); |
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183 private: |
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184 /** |
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185 * Assp-specific implementation for Kern::NanoWait function |
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186 */ |
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187 static void NanoWait(TUint32 aInterval); |
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188 }; |
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189 |
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190 // TO DO: (optional) |
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191 // |
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192 // Enumerate here all ASSP interrupt souces. It could be a good idea to enumerate them in a way that facilitates |
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193 // operating on the corresponding interrupt controller registers (e.g using their value as a shift count) |
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194 // |
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195 // EXAMPLE ONLY |
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196 enum TTemplateAsspInterruptId |
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197 { |
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198 // ASSP or first-level Interrupt IDs |
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199 EAsspIntIdA=0, |
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200 EAsspIntIdB=1, |
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201 EAsspIntIdC=2, |
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202 EAsspIntIdD=3, |
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203 EAsspIntIdE=4, |
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204 // ... |
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205 EAsspIntIdUsb=11, |
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206 EAsspIntIdDma=12, |
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207 // ... |
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208 EAsspIntIdZ=25 |
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209 }; |
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210 |
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211 // |
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212 // TO DO: (optional) |
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213 // |
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214 // Define here some commonly used ASSP interrupts |
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215 // |
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216 // EXAMPLE ONLY |
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217 const TInt KIntIdExpansion=EAsspIntIdA; // this is the ASSP interrupt which connects to second-level (Variant) |
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218 // Interrupt controller: all 2nd level interrupts come through this interrupt |
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219 const TInt KIntIdOstMatchMsTimer=EAsspIntIdB; |
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220 const TInt KIntIdDigitiser=EAsspIntIdC; |
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221 const TInt KIntIdSound=EAsspIntIdD; |
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222 const TInt KIntIdTimer1=EAsspIntIdE; |
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223 |
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224 |
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225 #endif |
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226 |