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1 // Copyright (c) 1994-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // e32\nkern\arm\ncutils.cia |
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15 // |
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16 // |
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17 |
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18 #include <e32cia.h> |
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19 #include <arm.h> |
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20 |
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21 //#define __DBG_MON_FAULT__ |
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22 //#define __RAM_LOADED_CODE__ |
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23 //#define __EARLY_DEBUG__ |
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24 |
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25 #ifdef _DEBUG |
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26 #define ASM_KILL_LINK(rp,rs) asm("mov "#rs", #0xdf ");\ |
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27 asm("orr "#rs", "#rs", "#rs", lsl #8 ");\ |
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28 asm("orr "#rs", "#rs", "#rs", lsl #16 ");\ |
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29 asm("str "#rs", ["#rp"] ");\ |
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30 asm("str "#rs", ["#rp", #4] "); |
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31 #else |
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32 #define ASM_KILL_LINK(rp,rs) |
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33 #endif |
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34 |
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35 |
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36 #ifdef __PRI_LIST_MACHINE_CODED__ |
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37 /** Return the priority of the highest priority item present on a priority list. |
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38 |
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39 @return The highest priority present or -1 if the list is empty. |
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40 */ |
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41 EXPORT_C __NAKED__ TInt TPriListBase::HighestPriority() |
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42 { |
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43 #ifdef __CPU_ARM_HAS_CLZ |
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44 asm("ldr r2, [r0, #4] "); // r2=iPresent MSW |
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45 asm("ldr r1, [r0, #0] "); // r1=iPresent LSW |
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46 CLZ(0,2); // r0=31-MSB(r2) |
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47 asm("subs r0, r0, #32 "); // r0=-1-MSB(r2), 0 if r2=0 |
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48 CLZcc(CC_EQ,0,1); // if r2=0, r0=31-MSB(r1) |
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49 asm("rsb r0, r0, #31 "); // r0=highest priority |
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50 #else |
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51 asm("ldmia r0, {r1,r2} "); // r2:r1=iPresent |
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52 asm("mov r0, #31 "); // start at 31 |
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53 asm("cmp r2, #0 "); // high word non-zero? |
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54 asm("movne r0, #63 "); // if so, start at 63 |
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55 asm("movne r1, r2 "); // and set r1=high word |
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56 asm("cmp r1, #0 "); |
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57 asm("beq highest_pri_0 "); |
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58 asm("cmp r1, #0x00010000 "); |
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59 asm("movcc r1, r1, lsl #16 "); |
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60 asm("subcc r0, r0, #16 "); |
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61 asm("cmp r1, #0x01000000 "); |
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62 asm("movcc r1, r1, lsl #8 "); |
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63 asm("subcc r0, r0, #8 "); |
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64 asm("cmp r1, #0x10000000 "); |
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65 asm("movcc r1, r1, lsl #4 "); |
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66 asm("subcc r0, r0, #4 "); |
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67 asm("cmp r1, #0x40000000 "); |
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68 asm("movcc r1, r1, lsl #2 "); |
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69 asm("subcc r0, r0, #2 "); |
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70 asm("cmp r1, #0x80000000 "); |
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71 asm("subcc r0, r0, #1 "); |
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72 __JUMP(,lr); |
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73 asm("highest_pri_0: "); |
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74 asm("mvn r0, #0 "); // if list empty, return -1 |
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75 #endif |
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76 __JUMP(,lr); |
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77 } |
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78 |
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79 /** Find the highest priority item present on a priority list. |
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80 If multiple items at the same priority are present, return the first to be |
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81 added in chronological order. |
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82 |
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83 @return a pointer to the item or NULL if the list is empty. |
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84 */ |
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85 EXPORT_C __NAKED__ TPriListLink* TPriListBase::First() |
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86 { |
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87 #ifdef __CPU_ARM_HAS_CLZ |
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88 asm("ldr r2, [r0, #4] "); // r2=iPresent MSW |
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89 asm("ldr r1, [r0], #8 "); // r1=iPresent LSW, r0=&iQueue[0] |
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90 CLZ(3,2); // r3=31-MSB(r2) |
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91 asm("subs r3, r3, #32 "); // r3=-1-MSB(r2), 0 if r2=0 |
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92 CLZcc(CC_EQ,3,1); // if r2=0, r3=31-MSB(r1) |
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93 asm("rsbs r3, r3, #31 "); // r3=highest priority |
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94 asm("ldrpl r0, [r0, r3, lsl #2] "); // if r3>=0 list is nonempty, r0->first entry |
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95 asm("movmi r0, #0 "); // if r3<0 list empty, return NULL |
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96 #else |
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97 asm("ldmia r0!, {r1,r2} "); // r2:r1=iPresent, r0=&iQueue[0] |
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98 asm("cmp r2, #0 "); // high word non-zero? |
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99 asm("addne r0, r0, #128 "); // if so, r0=&iQueue[32] |
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100 asm("movne r1, r2 "); // and set r1=high word |
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101 asm("cmp r1, #0x00010000 "); |
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102 asm("movcc r1, r1, lsl #16 "); |
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103 asm("addcs r0, r0, #0x40 "); // if iPresent>=0x00010000, step r0 on by 16 words |
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104 asm("cmp r1, #0x01000000 "); |
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105 asm("movcc r1, r1, lsl #8 "); |
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106 asm("addcs r0, r0, #0x20 "); // if iPresent>=0x01000000, step r0 on by 8 words |
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107 asm("cmp r1, #0x10000000 "); |
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108 asm("movcc r1, r1, lsl #4 "); |
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109 asm("addcs r0, r0, #0x10 "); // if iPresent>=0x10000000, step r0 on by 4 words |
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110 asm("cmp r1, #0x40000000 "); |
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111 asm("movcc r1, r1, lsl #2 "); |
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112 asm("addcs r0, r0, #0x08 "); // if iPresent>=0x40000000, step r0 on by 2 words |
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113 asm("cmp r1, #0 "); |
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114 asm("addmi r0, r0, #4 "); // if iPresent>=0x80000000, step r0 on by 1 word |
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115 asm("ldrne r0, [r0] "); // if iPresent was not zero, r0 points to first entry |
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116 asm("moveq r0, #0 "); // else r0=NULL |
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117 #endif |
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118 __JUMP(,lr); |
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119 } |
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120 |
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121 /** Add an item to a priority list. |
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122 |
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123 @param aLink = a pointer to the item - must not be NULL |
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124 */ |
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125 EXPORT_C __NAKED__ void TPriListBase::Add(TPriListLink* /*aLink*/) |
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126 { |
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127 asm("ldrb r2, [r1, #8]" ); // r2=priority of aLink |
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128 asm("add ip, r0, #8 "); // ip=&iQueue[0] |
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129 asm("ldr r3, [ip, r2, lsl #2]! "); // r3->first entry at this priority |
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130 asm("cmp r3, #0 "); // is this first entry at this priority? |
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131 asm("bne pri_list_add_1 "); // branch if not |
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132 asm("str r1, [ip] "); // if queue originally empty, iQueue[pri]=aThread |
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133 asm("ldrb ip, [r0, r2, lsr #3]! "); // ip=relevant byte of present mask, r0->same |
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134 asm("and r2, r2, #7 "); |
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135 asm("mov r3, #1 "); |
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136 asm("str r1, [r1, #0] "); // aThread->next=aThread |
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137 asm("orr ip, ip, r3, lsl r2 "); // ip |= 1<<(pri&7) |
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138 asm("str r1, [r1, #4] "); // aThread->iPrev=aThread |
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139 asm("strb ip, [r0] "); // update relevant byte of present mask |
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140 __JUMP(,lr); |
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141 asm("pri_list_add_1: "); |
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142 asm("ldr ip, [r3, #4] "); // if nonempty, ip=last |
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143 asm("str r1, [r3, #4] "); // first->prev=aThread |
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144 asm("stmia r1, {r3,ip} "); // aThread->next=r3=first, aThread->prev=ip=last |
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145 asm("str r1, [ip, #0] "); // last->next=aThread |
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146 __JUMP(,lr); |
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147 } |
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148 |
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149 /** Change the priority of an item on a priority list |
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150 |
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151 @param aLink = pointer to the item to act on - must not be NULL |
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152 @param aNewPriority = new priority for the item |
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153 */ |
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154 EXPORT_C __NAKED__ void TPriListBase::ChangePriority(TPriListLink* /*aLink*/, TInt /*aNewPriority*/) |
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155 { |
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156 asm("ldrb r3, [r1, #8] "); // r3=old priority |
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157 asm("stmfd sp!, {r4-r6,lr} "); |
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158 asm("cmp r3, r2 "); |
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159 asm("ldmeqfd sp!, {r4-r6,pc} "); // if old priority=new, finished |
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160 asm("ldmia r1, {r4,r12} "); // r4=next, r12=prev |
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161 asm("ldmia r0!, {r6,lr} "); // lr:r6=present mask, r0=&iQueue[0] |
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162 asm("subs r5, r4, r1 "); // check if aLink is only one at that priority, r5=0 if it is |
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163 asm("beq change_pri_1 "); // branch if it is |
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164 asm("ldr r5, [r0, r3, lsl #2] "); // r5=iQueue[old priority] |
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165 asm("str r4, [r12, #0] "); // prev->next=next |
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166 asm("str r12, [r4, #4] "); // next->prev=prev |
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167 asm("cmp r5, r1 "); // was aLink first? |
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168 asm("streq r4, [r0, r3, lsl #2] "); // if it was, iQueue[old priority]=aLink->next |
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169 asm("b change_pri_2 "); |
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170 asm("change_pri_1: "); |
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171 asm("str r5, [r0, r3, lsl #2] "); // if empty, set iQueue[old priority]=NULL |
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172 asm("mov r12, #0x80000000 "); |
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173 asm("rsbs r3, r3, #31 "); // r3=31-priority |
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174 asm("bicmi lr, lr, r12, ror r3 "); // if pri>31, clear bit is MS word |
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175 asm("bicpl r6, r6, r12, ror r3 "); // if pri<=31, clear bit in LS word |
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176 asm("change_pri_2: "); |
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177 asm("ldr r4, [r0, r2, lsl #2] "); // r4=iQueue[new priority] |
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178 asm("strb r2, [r1, #8] "); // store new priority |
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179 asm("cmp r4, #0 "); // new priority queue empty? |
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180 asm("bne change_pri_3 "); // branch if not |
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181 asm("str r1, [r0, r2, lsl #2] "); // if new priority queue was empty, iQueue[new p]=aLink |
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182 asm("mov r12, #0x80000000 "); |
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183 asm("str r1, [r1, #0] "); // aLink->next=aLink |
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184 asm("rsbs r2, r2, #31 "); // r2=31-priority |
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185 asm("str r1, [r1, #4] "); // aLink->prev=aLink |
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186 asm("orrmi lr, lr, r12, ror r2 "); // if pri>31, set bit is MS word |
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187 asm("orrpl r6, r6, r12, ror r2 "); // if pri<=31, set bit in LS word |
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188 asm("stmdb r0!, {r6,lr} "); // store present mask and restore r0 |
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189 asm("ldmfd sp!, {r4-r6,pc} "); |
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190 asm("change_pri_3: "); |
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191 asm("ldr r12, [r4, #4] "); // r12->last link at this priority |
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192 asm("str r1, [r4, #4] "); // first->prev=aLink |
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193 asm("str r1, [r12, #0] "); // old last->next=aLink |
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194 asm("stmia r1, {r4,r12} "); // aLink->next=r3=first, aLink->prev=r12=old last |
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195 asm("stmdb r0!, {r6,lr} "); // store present mask and restore r0 |
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196 asm("ldmfd sp!, {r4-r6,pc} "); |
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197 } |
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198 #endif |
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199 |
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200 __NAKED__ void initialiseState() |
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201 { |
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202 // entry in mode_svc with irqs and fiqs off |
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203 asm("mrs r0, cpsr "); |
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204 asm("bic r1, r0, #0x1f "); |
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205 asm("orr r1, r1, #0xd3 "); // mode_svc |
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206 asm("msr cpsr, r1 "); |
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207 __JUMP(,lr); |
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208 } |
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209 |
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210 // Called by a thread when it first runs |
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211 __NAKED__ void __StartThread() |
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212 { |
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213 // On entry r4->current thread, r5->entry point, r6->parameter block |
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214 asm("mov r0, r6 "); |
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215 USER_MEMORY_GUARD_OFF_IF_MODE_USR(r6); |
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216 ERRATUM_353494_MODE_CHANGE(,r6); |
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217 asm("mov lr, pc "); |
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218 asm("movs pc, r5 "); |
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219 asm("b " CSM_ZN5NKern4ExitEv); |
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220 } |
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221 |
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222 // Called by a thread which has been forced to exit |
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223 // Interrupts off here, kernel unlocked |
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224 __NAKED__ void __DoForcedExit() |
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225 { |
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226 asm("mov r0, #0x13 "); |
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227 asm("msr cpsr, r0 "); // interrupts back on |
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228 asm("bic sp, sp, #4 "); // align stack since it may be misaligned on return from scheduler |
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229 asm("bl " CSM_ZN5NKern4LockEv); // lock the kernel (must do this before setting iCsCount=0) |
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230 asm("ldr r0, __TheScheduler "); // r0 points to scheduler data |
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231 asm("mov r1, #0 "); |
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232 asm("ldr r0, [r0, #%a0]" : : "i" _FOFF(TScheduler,iCurrentThread)); // r0=iCurrentThread |
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233 asm("str r1, [r0, #%a0]" : : "i" _FOFF(NThreadBase,iCsCount)); // set iCsCount=0 |
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234 asm("b " CSM_ZN11NThreadBase4ExitEv); // exit |
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235 |
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236 asm("__TheScheduler: "); |
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237 asm(".word TheScheduler "); |
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238 asm("__BTraceData: "); |
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239 asm(".word BTraceData "); |
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240 asm("__DBTraceFilter2_iCleanupHead:"); |
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241 #ifdef __EABI__ |
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242 asm(".word _ZN14DBTraceFilter212iCleanupHeadE"); |
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243 #else |
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244 asm(".word _14DBTraceFilter2.iCleanupHead"); |
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245 #endif |
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246 } |
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247 |
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248 |
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249 /** @internalTechnology |
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250 |
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251 Called to indicate that the system has crashed and all CPUs should be |
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252 halted and should dump their registers. |
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253 |
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254 */ |
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255 __NAKED__ void NKern::NotifyCrash(const TAny* /*a0*/, TInt /*a1*/) |
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256 { |
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257 asm("stmfd sp!, {r0-r1} "); // save parameters |
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258 asm("ldr r0, __CrashState "); |
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259 asm("mov r1, #1 "); |
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260 asm("str r1, [r0] "); // CrashState = ETrue |
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261 asm("ldr r0, __TheScheduler "); |
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262 asm("ldr r0, [r0, #%a0]" : : "i" _FOFF(TScheduler,i_Regs)); |
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263 asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet, iExcCode)); |
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264 asm("cmp r1, #0 "); // context already saved? |
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265 asm("bge state_already_saved "); // skip if so |
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266 asm("mov r1, lr "); |
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267 asm("bl " CSM_ZN3Arm9SaveStateER14SFullArmRegSet ); |
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268 asm("str r1, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet, iN.iR15)); |
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269 asm("ldmia sp!, {r2-r3} "); // original R0,R1 |
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270 asm("stmia r0, {r2-r3} "); // save original R0,R1 |
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271 asm("add r1, r0, #%a0" : : "i" _FOFF(SFullArmRegSet, iExcCode)); |
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272 asm("stmib r1, {r2-r3} "); // save a0, a1 in iCrashArgs |
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273 asm("mov r1, #13 "); // r1 = regnum |
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274 asm("mrs r2, cpsr "); // r2 = mode |
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275 asm("bl " CSM_ZN3Arm3RegER14SFullArmRegSetim ); // r0 = pointer to exception mode R13 |
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276 asm("str sp, [r0] "); // save correct original value for exception mode R13 |
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277 asm("b state_save_complete "); |
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278 |
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279 asm("state_already_saved: "); |
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280 asm("ldmia sp!, {r2-r3} "); // original R0,R1 |
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281 asm("add r1, r0, #%a0" : : "i" _FOFF(SFullArmRegSet, iExcCode)); |
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282 asm("ldr r4, [r1, #4]! "); |
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283 asm("cmp r4, #0 "); |
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284 asm("stmeqia r1, {r2-r3} "); // save a0, a1 in iCrashArgs, provided iCrashArgs not already set |
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285 asm("state_save_complete: "); |
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286 |
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287 asm("mov r2, #0xd1 "); |
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288 asm("msr cpsr, r2 "); // mode_fiq, interrupts off |
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289 asm("mov r4, r0 "); |
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290 asm("bic sp, sp, #4 "); // align stack to multiple of 8 |
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291 |
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292 asm("mov r0, #0 "); |
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293 asm("mov r1, #0 "); |
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294 asm("mov r2, #0 "); |
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295 asm("bl NKCrashHandler "); |
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296 |
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297 asm("mov r0, #1 "); |
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298 asm("ldr r1, [r4, #%a0] " : : "i" _FOFF(SFullArmRegSet,iN.iR0)); // original R0 = a0 parameter |
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299 asm("ldr r2, [r4, #%a0] " : : "i" _FOFF(SFullArmRegSet,iN.iR1)); // original R1 = a1 parameter |
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300 asm("bl NKCrashHandler "); |
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301 |
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302 // shouldn't get back here |
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303 __ASM_CRASH(); |
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304 |
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305 asm("__CrashState: "); |
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306 asm(".word %a0" : : "i" ((TInt)&CrashState)); |
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307 } |
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308 |
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309 |
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310 |
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311 __NAKED__ EXPORT_C TBool BTrace::Out(TUint32 a0, TUint32 a1, TUint32 a2, TUint32 a3) |
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312 { |
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313 asm("ldr r12, __BTraceData"); |
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314 asm("stmdb sp!, {r2,r3,r4,lr}"); |
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315 asm("and r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8)))); |
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316 asm("ldrb r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8))); |
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317 asm("mov r3, r1"); // r3 = a1 (ready for call to handler) |
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318 asm("adr lr, 9f"); |
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319 asm("cmp r2, #0"); |
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320 asm("moveq r0, #0"); |
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321 asm("ldrne pc, [r12, #%a0]" : : "i" _FOFF(SBTraceData,iHandler)); |
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322 asm("9:"); |
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323 __POPRET("r2,r3,r4,"); |
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324 } |
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325 |
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326 __NAKED__ EXPORT_C TBool BTrace::OutN(TUint32 a0, TUint32 a1, TUint32 a2, const TAny* aData, TInt aDataSize) |
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327 { |
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328 asm("ldr r12, __BTraceData"); |
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329 asm("stmdb sp!, {r2,r3,r4,lr}"); |
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330 asm("and r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8)))); |
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331 asm("ldrb r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8))); |
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332 asm("ldr r4, [sp, #16]"); // r2 = aDataSize |
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333 asm("cmp r2, #0"); |
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334 asm("moveq r0, #0"); |
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335 __CPOPRET(eq,"r2,r3,r4,"); |
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336 |
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337 asm("cmp r4, #%a0" : : "i" ((TInt)KMaxBTraceDataArray)); |
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338 asm("movhi r4, #%a0" : : "i" ((TInt)KMaxBTraceDataArray)); |
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339 asm("orrhi r0, r0, #%a0" : : "i" ((TInt)(BTrace::ERecordTruncated<<(BTrace::EFlagsIndex*8)))); |
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340 asm("add r0, r0, r4"); |
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341 asm("subs r4, r4, #1"); |
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342 asm("ldrhs r2, [r3]"); // get first word of aData is aDataSize!=0 |
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343 asm("mov r3, r1"); // r3 = a1 (ready for call to handler) |
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344 asm("cmp r4, #4"); |
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345 asm("strlo r2, [sp, #4]"); // replace aData with first word if aDataSize is 1-4 |
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346 |
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347 asm("mov lr, pc"); |
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348 asm("ldr pc, [r12, #%a0]" : : "i" _FOFF(SBTraceData,iHandler)); |
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349 __POPRET("r2,r3,r4,"); |
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350 } |
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351 |
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352 __NAKED__ EXPORT_C TBool BTrace::OutX(TUint32 a0, TUint32 a1, TUint32 a2, TUint32 a3) |
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353 { |
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354 asm("ldr r12, __BTraceData"); |
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355 asm("stmdb sp!, {r2,r3,r4,lr}"); |
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356 asm("and r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8)))); |
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357 asm("ldrb r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8))); |
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358 asm("mov r3, r1"); // r3 = a1 (ready for call to handler) |
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359 asm("ldr lr, __TheScheduler"); |
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360 asm("cmp r2, #0"); |
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361 asm("moveq r0, #0"); |
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362 __CPOPRET(eq,"r2,r3,r4,"); |
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363 |
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364 // set r2 = context id |
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365 asm("ldrb r4, [lr, #%a0]" : : "i" _FOFF(TScheduler,iInIDFC)); |
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366 asm("mrs r2, cpsr"); |
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367 asm("and r2, r2, #3"); |
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368 asm("cmp r2, #3"); |
|
369 asm("cmpeq r4, #0"); |
|
370 asm("ldreq r2, [lr, #%a0]" : : "i" _FOFF(TScheduler,iCurrentThread)); |
|
371 |
|
372 asm("mov lr, pc"); |
|
373 asm("ldr pc, [r12, #%a0]" : : "i" _FOFF(SBTraceData,iHandler)); |
|
374 __POPRET("r2,r3,r4,"); |
|
375 } |
|
376 |
|
377 __NAKED__ EXPORT_C TBool BTrace::OutNX(TUint32 a0, TUint32 a1, TUint32 a2, const TAny* aData, TInt aDataSize) |
|
378 { |
|
379 asm("ldr r12, __BTraceData"); |
|
380 asm("stmdb sp!, {r2,r3,r4,lr}"); |
|
381 asm("and r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8)))); |
|
382 asm("ldrb r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8))); |
|
383 asm("ldr r4, [sp, #16]"); // r2 = aDataSize |
|
384 asm("ldr lr, __TheScheduler"); |
|
385 asm("cmp r2, #0"); |
|
386 asm("moveq r0, #0"); |
|
387 __CPOPRET(eq,"r2,r3,r4,"); |
|
388 |
|
389 asm("cmp r4, #%a0" : : "i" ((TInt)KMaxBTraceDataArray)); |
|
390 asm("movhi r4, #%a0" : : "i" ((TInt)KMaxBTraceDataArray)); |
|
391 asm("orrhi r0, r0, #%a0" : : "i" ((TInt)(BTrace::ERecordTruncated<<(BTrace::EFlagsIndex*8)))); |
|
392 asm("add r0, r0, r4"); |
|
393 asm("subs r4, r4, #1"); |
|
394 asm("ldrhs r2, [r3]"); // get first word of aData is aDataSize!=0 |
|
395 asm("mov r3, r1"); // r3 = a1 (ready for call to handler) |
|
396 asm("cmp r4, #4"); |
|
397 asm("strlo r2, [sp, #4]"); // replace aData with first word if aDataSize is 1-4 |
|
398 |
|
399 // set r2 = context id |
|
400 asm("ldrb r4, [lr, #%a0]" : : "i" _FOFF(TScheduler,iInIDFC)); |
|
401 asm("mrs r2, cpsr"); |
|
402 asm("and r2, r2, #3"); |
|
403 asm("cmp r2, #3"); |
|
404 asm("cmpeq r4, #0"); |
|
405 asm("ldreq r2, [lr, #%a0]" : : "i" _FOFF(TScheduler,iCurrentThread)); |
|
406 |
|
407 asm("mov lr, pc"); |
|
408 asm("ldr pc, [r12, #%a0]" : : "i" _FOFF(SBTraceData,iHandler)); |
|
409 __POPRET("r2,r3,r4,"); |
|
410 } |
|
411 |
|
412 __NAKED__ EXPORT_C TBool BTrace::OutBig(TUint32 a0, TUint32 a1, const TAny* aData, TInt aDataSize) |
|
413 { |
|
414 asm("ldr r12, __BTraceData"); |
|
415 asm("stmdb sp!, {r4,lr}"); |
|
416 asm("and r4, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8)))); |
|
417 asm("ldrb r4, [r12, r4, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8))); |
|
418 asm("cmp r4, #0"); |
|
419 asm("moveq r0, #0"); |
|
420 __CPOPRET(eq,"r4,"); |
|
421 |
|
422 asm("ldr r12, __TheScheduler"); |
|
423 asm("stmdb sp!, {lr}"); |
|
424 asm("ldrb lr, [r12, #%a0]" : : "i" _FOFF(TScheduler,iInIDFC)); |
|
425 asm("mrs r4, cpsr"); |
|
426 asm("and r4, r4, #3"); |
|
427 asm("cmp r4, #3"); |
|
428 asm("cmpeq lr, #0"); |
|
429 asm("ldreq r4, [r12, #%a0]" : : "i" _FOFF(TScheduler,iCurrentThread)); |
|
430 asm("stmdb sp!, {r4}"); |
|
431 asm("bl " CSM_ZN6BTrace8DoOutBigEmmPKvimm); |
|
432 asm("add sp, sp, #8"); |
|
433 __POPRET("r4,"); |
|
434 } |
|
435 |
|
436 |
|
437 __NAKED__ TBool DBTraceFilter2::Check(TUint32 aUid) |
|
438 { |
|
439 asm("stmdb sp!, {lr}"); |
|
440 asm("ldr r3, [r0,#%a0]" : : "i" _FOFF(DBTraceFilter2,iNumUids)); |
|
441 asm("add r0, r0, #%a0" : : "i" _FOFF(DBTraceFilter2,iUids)); |
|
442 asm("mov r2, #0"); |
|
443 asm("0:"); |
|
444 asm("cmp r3, r2"); |
|
445 asm("bls 9f"); |
|
446 asm("add r12, r2, r3"); |
|
447 asm("mov r12, r12, asr #1"); |
|
448 asm("ldr lr, [r0, r12, lsl #2]"); |
|
449 asm("cmp r1, lr"); |
|
450 asm("addhi r2, r12, #1"); |
|
451 asm("movlo r3, r12"); |
|
452 asm("bne 0b"); |
|
453 asm("movs r0, #1"); |
|
454 __POPRET(""); |
|
455 asm("9:"); |
|
456 asm("movs r0, #0"); |
|
457 __POPRET(""); |
|
458 } |
|
459 |
|
460 |
|
461 __NAKED__ TBool SBTraceData::CheckFilter2(TUint32 aUid) |
|
462 { |
|
463 asm("btrace_check_filter2:"); |
|
464 // returns r0 = 0 or 1 indicating if trace passed the filter check |
|
465 // returns r2 = trace context id |
|
466 |
|
467 asm("ldr r12, __TheScheduler"); |
|
468 asm("stmdb sp!, {r4-r6,lr}"); |
|
469 asm("mrs r2, cpsr"); |
|
470 // r2 = cpsr |
|
471 asm("ldrb lr, [r12, #%a0]" : : "i" _FOFF(TScheduler,iInIDFC)); |
|
472 asm("and r4, r2, #3"); |
|
473 asm("cmp r4, #3"); |
|
474 asm("cmpeq lr, #0"); |
|
475 asm("ldreq lr, [r12, #%a0]" : : "i" _FOFF(TScheduler,iKernCSLocked)); |
|
476 asm("ldreq r4, [r12, #%a0]" : : "i" _FOFF(TScheduler,iCurrentThread)); |
|
477 asm("cmpeq lr, #0"); |
|
478 // r4 = context value for trace |
|
479 // zero flag set if we need to enter a critical section |
|
480 |
|
481 // NKern::ThreadEnterCS() |
|
482 asm("ldreq r5, [r4, #%a0]" : : "i" _FOFF(NThreadBase,iCsCount)); |
|
483 asm("movne r5, #0"); |
|
484 asm("addeq r5, r5, #1"); |
|
485 asm("streq r5, [r4, #%a0]" : : "i" _FOFF(NThreadBase,iCsCount)); |
|
486 // r5 = true if we entered a critical section |
|
487 |
|
488 // DBTraceFilter2::Open() |
|
489 INTS_OFF(r12, r2, INTS_ALL_OFF); |
|
490 asm("ldr r0, [r0, #%a0]" : : "i" (_FOFF(SBTraceData,iFilter2))); |
|
491 asm("cmp r0, #1"); |
|
492 asm("ldrhi r12, [r0, #%a0]" : : "i" _FOFF(DBTraceFilter2,iAccessCount)); |
|
493 asm("addhi r12, r12, #1"); |
|
494 asm("strhi r12, [r0, #%a0]" : : "i" _FOFF(DBTraceFilter2,iAccessCount)); |
|
495 asm("msr cpsr_c, r2"); |
|
496 asm("bls 8f"); |
|
497 |
|
498 |
|
499 asm("mov r6, r0"); |
|
500 asm("bl Check__14DBTraceFilter2Ul"); |
|
501 // r0 = result |
|
502 |
|
503 |
|
504 // DBTraceFilter2::Close() |
|
505 asm("mrs r2, cpsr"); |
|
506 INTS_OFF(r12, r2, INTS_ALL_OFF); |
|
507 asm("ldr r12, [r6, #%a0]" : : "i" _FOFF(DBTraceFilter2,iAccessCount)); |
|
508 asm("ldr r1, __DBTraceFilter2_iCleanupHead"); |
|
509 asm("subs r12, r12, #1"); |
|
510 asm("str r12, [r6, #%a0]" : : "i" _FOFF(DBTraceFilter2,iAccessCount)); |
|
511 asm("ldreq r12, [r1]"); |
|
512 asm("streq r6, [r1]"); |
|
513 asm("streq r12, [r6, #%a0]" : : "i" _FOFF(DBTraceFilter2,iCleanupLink)); |
|
514 asm("msr cpsr_c, r2"); |
|
515 |
|
516 // NKern::ThreadLeaveCS() |
|
517 asm("8:"); |
|
518 asm("cmp r5, #0"); |
|
519 asm("beq 9f"); |
|
520 asm("mov r5, r0"); |
|
521 asm("bl " CSM_ZN5NKern13ThreadLeaveCSEv); |
|
522 asm("mov r0, r5"); |
|
523 asm("9:"); |
|
524 asm("mov r2, r4"); // r2 = context id |
|
525 __POPRET("r4-r6,"); |
|
526 } |
|
527 |
|
528 |
|
529 __NAKED__ EXPORT_C TBool BTrace::OutFiltered(TUint32 a0, TUint32 a1, TUint32 a2, TUint32 a3) |
|
530 { |
|
531 // fall through to OutFilteredX... |
|
532 } |
|
533 |
|
534 __NAKED__ EXPORT_C TBool BTrace::OutFilteredX(TUint32 a0, TUint32 a1, TUint32 a2, TUint32 a3) |
|
535 { |
|
536 asm("ldr r12, __BTraceData"); |
|
537 asm("stmdb sp!, {r2,r3,r4,lr}"); |
|
538 asm("and r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8)))); |
|
539 asm("ldrb r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8))); |
|
540 asm("mov r3, r1"); // r3 = a1 (ready for call to handler) |
|
541 asm("cmp r2, #0"); |
|
542 asm("moveq r0, #0"); |
|
543 __CPOPRET(eq,"r2,r3,r4,"); |
|
544 |
|
545 asm("stmdb sp!, {r0,r3,r12}"); |
|
546 asm("mov r0, r12"); |
|
547 asm("bl btrace_check_filter2"); |
|
548 asm("cmp r0, #0"); |
|
549 asm("ldmia sp!, {r0,r3,r12}"); |
|
550 asm("moveq r0, #0"); |
|
551 __CPOPRET(eq,"r2,r3,r4,"); |
|
552 |
|
553 asm("adr lr, 9f"); |
|
554 asm("ldr pc, [r12, #%a0]" : : "i" _FOFF(SBTraceData,iHandler)); |
|
555 asm("9:"); |
|
556 __POPRET("r2,r3,r4,"); |
|
557 } |
|
558 |
|
559 __NAKED__ EXPORT_C TBool BTrace::OutFilteredN(TUint32 a0, TUint32 a1, TUint32 a2, const TAny* aData, TInt aDataSize) |
|
560 { |
|
561 // fall through to OutFilteredNX... |
|
562 } |
|
563 |
|
564 __NAKED__ EXPORT_C TBool BTrace::OutFilteredNX(TUint32 a0, TUint32 a1, TUint32 a2, const TAny* aData, TInt aDataSize) |
|
565 { |
|
566 asm("ldr r12, __BTraceData"); |
|
567 asm("stmdb sp!, {r2,r3,r4,lr}"); |
|
568 asm("and r2, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8)))); |
|
569 asm("ldrb r2, [r12, r2, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8))); |
|
570 asm("cmp r2, #0"); |
|
571 asm("moveq r0, #0"); |
|
572 __CPOPRET(eq,"r2,r3,r4,"); |
|
573 |
|
574 asm("stmdb sp!, {r0,r1,r3,r12}"); |
|
575 asm("mov r0, r12"); |
|
576 asm("bl btrace_check_filter2"); |
|
577 asm("cmp r0, #0"); |
|
578 asm("ldmia sp!, {r0,r1,r3,r12}"); |
|
579 asm("moveq r0, #0"); |
|
580 __CPOPRET(eq,"r2,r3,r4,"); |
|
581 |
|
582 asm("ldr r4, [sp, #16]"); // r4 = aDataSize |
|
583 asm("cmp r4, #%a0" : : "i" ((TInt)KMaxBTraceDataArray)); |
|
584 asm("movhi r4, #%a0" : : "i" ((TInt)KMaxBTraceDataArray)); |
|
585 asm("orrhi r0, r0, #%a0" : : "i" ((TInt)(BTrace::ERecordTruncated<<(BTrace::EFlagsIndex*8)))); |
|
586 asm("add r0, r0, r4"); |
|
587 asm("subs r4, r4, #1"); |
|
588 asm("ldrhs lr, [r3]"); // get first word of aData is aDataSize!=0 |
|
589 asm("mov r3, r1"); // r3 = a1 (ready for call to handler) |
|
590 asm("cmp r4, #4"); |
|
591 asm("strlo lr, [sp, #4]"); // replace aData with first word if aDataSize is 1-4 |
|
592 |
|
593 asm("mov lr, pc"); |
|
594 asm("ldr pc, [r12, #%a0]" : : "i" _FOFF(SBTraceData,iHandler)); |
|
595 __POPRET("r2,r3,r4,"); |
|
596 } |
|
597 |
|
598 __NAKED__ EXPORT_C TBool BTrace::OutFilteredBig(TUint32 a0, TUint32 a1, const TAny* aData, TInt aDataSize) |
|
599 { |
|
600 asm("ldr r12, __BTraceData"); |
|
601 asm("stmdb sp!, {r4,lr}"); |
|
602 asm("and r4, r0, #%a0" : : "i" ((TInt)(0xff<<(BTrace::ECategoryIndex*8)))); |
|
603 asm("ldrb r4, [r12, r4, lsr #%a0]" : : "i" ((TInt)(BTrace::ECategoryIndex*8))); |
|
604 asm("cmp r4, #0"); |
|
605 asm("moveq r0, #0"); |
|
606 __CPOPRET(eq,"r4,"); |
|
607 |
|
608 asm("stmdb sp!, {r0-r3,r4,lr}"); |
|
609 asm("mov r0, r12"); |
|
610 asm("bl btrace_check_filter2"); |
|
611 asm("cmp r0, #0"); |
|
612 asm("mov r12, r2"); |
|
613 asm("ldmia sp!, {r0-r3,r4,lr}"); |
|
614 asm("moveq r0, #0"); |
|
615 __CPOPRET(eq,"r4,"); |
|
616 |
|
617 asm("stmdb sp!, {r12,lr}"); |
|
618 asm("bl " CSM_ZN6BTrace8DoOutBigEmmPKvimm); |
|
619 asm("add sp, sp, #8"); |
|
620 __POPRET("r4,"); |
|
621 } |
|
622 |
|
623 |
|
624 __NAKED__ EXPORT_C TBool BTrace::OutFilteredPcFormatBig(TUint32 a0, TUint32 aModuleUid, TUint32 aPc, TUint16 aFormatId, const TAny* aData, TInt aDataSize) |
|
625 { |
|
626 asm("mov r0, #0"); //kernel side not implemented yet |
|
627 } |
|
628 |
|
629 /******************************************************************************/ |
|
630 |
|
631 /** Save all the ARM registers |
|
632 |
|
633 @internalTechnology |
|
634 */ |
|
635 __NAKED__ void Arm::SaveState(SFullArmRegSet&) |
|
636 { |
|
637 asm("stmia r0, {r0-r14}^ "); // save R0-R7, R8_usr-R14_usr |
|
638 asm("str lr, [r0, #60]! "); // save R15 |
|
639 asm("mrs r1, cpsr "); |
|
640 asm("str r1, [r0, #4]! "); // save CPSR |
|
641 asm("bic r2, r1, #0x1f "); |
|
642 asm("orr r2, r2, #0xd3 "); // mode_svc, all interrupts off |
|
643 asm("msr cpsr, r2 "); |
|
644 asm("stmib r0!, {r13,r14} "); // save R13_svc, R14_svc |
|
645 asm("mrs r3, spsr "); |
|
646 asm("str r3, [r0, #4]! "); // save SPSR_svc |
|
647 asm("bic r2, r1, #0x1f "); |
|
648 asm("orr r2, r2, #0xd7 "); // mode_abt, all interrupts off |
|
649 asm("msr cpsr, r2 "); |
|
650 asm("stmib r0!, {r13,r14} "); // save R13_abt, R14_abt |
|
651 asm("mrs r3, spsr "); |
|
652 asm("str r3, [r0, #4]! "); // save SPSR_abt |
|
653 asm("bic r2, r1, #0x1f "); |
|
654 asm("orr r2, r2, #0xdb "); // mode_und, all interrupts off |
|
655 asm("msr cpsr, r2 "); |
|
656 asm("stmib r0!, {r13,r14} "); // save R13_und, R14_und |
|
657 asm("mrs r3, spsr "); |
|
658 asm("str r3, [r0, #4]! "); // save SPSR_und |
|
659 asm("bic r2, r1, #0x1f "); |
|
660 asm("orr r2, r2, #0xd2 "); // mode_irq, all interrupts off |
|
661 asm("msr cpsr, r2 "); |
|
662 asm("stmib r0!, {r13,r14} "); // save R13_irq, R14_irq |
|
663 asm("mrs r3, spsr "); |
|
664 asm("str r3, [r0, #4]! "); // save SPSR_irq |
|
665 asm("bic r2, r1, #0x1f "); |
|
666 asm("orr r2, r2, #0xd1 "); // mode_fiq, all interrupts off |
|
667 asm("msr cpsr, r2 "); |
|
668 asm("stmib r0!, {r8-r14} "); // save R8_fiq ... R14_fiq |
|
669 asm("mrs r3, spsr "); |
|
670 asm("str r3, [r0, #4]! "); // save SPSR_fiq |
|
671 asm("bic r2, r1, #0x1f "); |
|
672 asm("orr r2, r2, #0xd3 "); // mode_svc, all interrupts off |
|
673 asm("msr cpsr, r2 "); |
|
674 |
|
675 asm("mov r4, #0 "); |
|
676 asm("mov r5, #0 "); |
|
677 asm("mov r6, #0 "); |
|
678 asm("mov r7, #0 "); |
|
679 asm("mov r8, #0 "); |
|
680 asm("mov r9, #0 "); |
|
681 asm("mov r10, #0 "); |
|
682 asm("mov r11, #0 "); |
|
683 |
|
684 // monitor mode - skip for now |
|
685 asm("mov r3, #0 "); |
|
686 asm("stmib r0!, {r4-r6} "); // R13_mon, R14_mon, SPSR_mon |
|
687 |
|
688 // zero spare words |
|
689 asm("mov r3, #0 "); |
|
690 asm("stmib r0!, {r4-r11} "); |
|
691 asm("add r0, r0, #4 "); // r0 = &a.iA |
|
692 |
|
693 #ifdef __CPU_ARMV7 |
|
694 asm("mrc p14, 6, r3, c1, c0, 0 "); |
|
695 #else |
|
696 asm("mov r3, #0 "); |
|
697 #endif |
|
698 asm("str r3, [r0], #4 "); // TEEHBR |
|
699 #ifdef __CPU_HAS_COPROCESSOR_ACCESS_REG |
|
700 GET_CAR(,r3); |
|
701 #else |
|
702 asm("mov r3, #0 "); |
|
703 #endif |
|
704 asm("str r3, [r0], #4 "); // CPACR |
|
705 |
|
706 // skip SCR, SDER, NSACR, PMCR, MVBAR for now |
|
707 asm("mov r3, #0 "); |
|
708 asm("stmia r0!, {r4-r8} "); // SCR, SDER, NSACR, PMCR, MVBAR |
|
709 |
|
710 // zero spare words |
|
711 asm("mov r3, #0 "); |
|
712 asm("stmia r0!, {r3-r11} "); // r0 = &a.iB[0] |
|
713 |
|
714 // just fill in iB[0] |
|
715 #ifdef __CPU_HAS_MMU |
|
716 asm("mrc p15, 0, r3, c1, c0, 0 "); |
|
717 asm("str r3, [r0], #4 "); // SCTLR |
|
718 #ifdef __CPU_HAS_ACTLR |
|
719 asm("mrc p15, 0, r3, c1, c0, 1 "); |
|
720 #else |
|
721 asm("mov r3, #0 "); |
|
722 #endif |
|
723 asm("str r3, [r0], #4 "); // ACTLR |
|
724 asm("mrc p15, 0, r3, c2, c0, 0 "); |
|
725 asm("str r3, [r0], #4 "); // TTBR0 |
|
726 #ifdef __CPU_HAS_TTBR1 |
|
727 asm("mrc p15, 0, r2, c2, c0, 1 "); |
|
728 asm("mrc p15, 0, r3, c2, c0, 2 "); |
|
729 #else |
|
730 asm("mov r2, #0 "); |
|
731 asm("mov r3, #0 "); |
|
732 #endif |
|
733 asm("stmia r0!, {r2,r3} "); // TTBR1, TTBCR |
|
734 asm("mrc p15, 0, r3, c3, c0, 0 "); |
|
735 asm("str r3, [r0], #4 "); // DACR |
|
736 #ifdef __CPU_MEMORY_TYPE_REMAPPING |
|
737 asm("mrc p15, 0, r2, c10, c2, 0 "); |
|
738 asm("mrc p15, 0, r3, c10, c2, 1 "); |
|
739 #else |
|
740 asm("mov r2, #0 "); |
|
741 asm("mov r3, #0 "); |
|
742 #endif |
|
743 asm("stmia r0!, {r2,r3} "); // PRRR, NMRR |
|
744 #ifdef __CPU_ARMV7 |
|
745 asm("mrc p15, 0, r3, c12, c0, 0 "); |
|
746 #else |
|
747 asm("mov r3, #0 "); |
|
748 #endif |
|
749 asm("str r3, [r0], #4 "); // VBAR |
|
750 #if defined(__CPU_SA1) || defined(__CPU_ARM920T) || defined(__CPU_ARM925T) || defined(__CPU_ARMV5T) || defined(__CPU_ARMV6) || defined(__CPU_ARMV7) |
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751 asm("mrc p15, 0, r3, c13, c0, 0 "); |
|
752 #else |
|
753 asm("mov r3, #0 "); |
|
754 #endif |
|
755 asm("str r3, [r0], #4 "); // FCSEIDR |
|
756 #if defined(__CPU_ARMV6) || defined(__CPU_ARMV7) |
|
757 asm("mrc p15, 0, r3, c13, c0, 1 "); |
|
758 #else |
|
759 asm("mov r3, #0 "); |
|
760 #endif |
|
761 asm("str r3, [r0], #4 "); // CONTEXTIDR |
|
762 #ifdef __CPU_HAS_CP15_THREAD_ID_REG |
|
763 GET_RWRW_TID(,r2); |
|
764 GET_RWRO_TID(,r3); |
|
765 GET_RWNO_TID(,r12); |
|
766 #else |
|
767 asm("mov r2, #0 "); |
|
768 asm("mov r3, #0 "); |
|
769 asm("mov r12, #0 "); |
|
770 #endif |
|
771 asm("stmia r0!, {r2,r3,r12} "); // RWRWTID, RWROTID, RWNOTID |
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772 asm("mrc p15, 0, r2, c5, c0, 0 "); // DFSR |
|
773 #ifdef __CPU_ARM_HAS_SPLIT_FSR |
|
774 asm("mrc p15, 0, r3, c5, c0, 1 "); // IFSR |
|
775 #else |
|
776 asm("mov r3, #0 "); |
|
777 #endif |
|
778 asm("stmia r0!, {r2,r3} "); // DFSR, IFSR |
|
779 #ifdef __CPU_ARMV7 |
|
780 asm("mrc p15, 0, r2, c5, c1, 0 "); // ADFSR |
|
781 asm("mrc p15, 0, r3, c5, c1, 1 "); // AIFSR |
|
782 #else |
|
783 asm("mov r2, #0 "); |
|
784 asm("mov r3, #0 "); |
|
785 #endif |
|
786 asm("stmia r0!, {r2,r3} "); // ADFSR, AIFSR |
|
787 asm("mrc p15, 0, r2, c6, c0, 0 "); // DFAR |
|
788 #ifdef __CPU_ARM_HAS_CP15_IFAR |
|
789 asm("mrc p15, 0, r3, c6, c0, 2 "); // IFAR |
|
790 #else |
|
791 asm("mov r3, #0 "); |
|
792 #endif |
|
793 asm("stmia r0!, {r2,r3} "); // DFAR, IFAR |
|
794 |
|
795 // zero spare words |
|
796 asm("stmia r0!, {r4-r7} "); |
|
797 asm("stmia r0!, {r4-r11} "); |
|
798 #else // __CPU_HAS_MMU |
|
799 asm("stmia r0!, {r4-r11} "); // no MMU so zero fill |
|
800 asm("stmia r0!, {r4-r11} "); // no MMU so zero fill |
|
801 asm("stmia r0!, {r4-r11} "); // no MMU so zero fill |
|
802 asm("stmia r0!, {r4-r11} "); // no MMU so zero fill |
|
803 #endif // __CPU_HAS_MMU |
|
804 |
|
805 // zero iB[1] |
|
806 asm("stmia r0!, {r4-r11} "); |
|
807 asm("stmia r0!, {r4-r11} "); |
|
808 asm("stmia r0!, {r4-r11} "); |
|
809 asm("stmia r0!, {r4-r11} "); // r0 = &a.iMore[0] |
|
810 asm("add r1, r0, #62*8 "); // r1 = &a.iExcCode |
|
811 |
|
812 // Save VFP state |
|
813 // Save order: |
|
814 // FPEXC FPSCR |
|
815 // VFPv2 ONLY: FPINST FPINST2 |
|
816 // D0-D3 D4-D7 D8-D11 D12-D15 |
|
817 // VFPv3 ONLY: D16-D19 D20-D23 D24-D27 D28-D31 |
|
818 #ifdef __CPU_HAS_VFP |
|
819 GET_CAR(,r2); |
|
820 asm("bic r2, r2, #0x00f00000 "); |
|
821 #ifdef __VFP_V3 |
|
822 asm("bic r2, r2, #0xc0000000 "); // mask off ASEDIS, D32DIS |
|
823 #endif |
|
824 asm("orr r2, r2, #0x00500000 "); // enable privileged access to CP10, CP11 |
|
825 SET_CAR(,r2); |
|
826 VFP_FMRX(,2,VFP_XREG_FPEXC); // r2=FPEXC |
|
827 asm("orr r3, r2, #%a0" : : "i" ((TInt)VFP_FPEXC_EN)); |
|
828 VFP_FMXR(,VFP_XREG_FPEXC,3); // enable VFP |
|
829 __DATA_SYNC_BARRIER__(r4); |
|
830 __INST_SYNC_BARRIER__(r4); |
|
831 VFP_FMRX(,3,VFP_XREG_FPSCR); // r3=FPSCR |
|
832 asm("stmia r0!, {r2,r3} "); // |
|
833 #ifdef __VFP_V3 |
|
834 VFP_FSTMIADW(CC_AL,0,0,16); // save D0 - D15 |
|
835 VFP_FMRX(,3,VFP_XREG_MVFR0); |
|
836 asm("tst r3, #%a0" : : "i" ((TInt)VFP_MVFR0_ASIMD32)); // Check to see if all 32 Advanced SIMD registers are present |
|
837 VFP_FSTMIADW(CC_NE,0,16,16); // if so then save D16 - D31 (don't need to check CPACR.D32DIS as it is cleared above) |
|
838 #else |
|
839 VFP_FMRX(,2,VFP_XREG_FPINST); |
|
840 VFP_FMRX(,3,VFP_XREG_FPINST2); |
|
841 asm("stmia r0!, {r2,r3} "); // FPINST, FPINST2 |
|
842 VFP_FSTMIADW(CC_AL,0,0,16); // save D0 - D15 |
|
843 #endif |
|
844 #endif // __CPU_HAS_VFP |
|
845 asm("1: "); |
|
846 asm("cmp r0, r1 "); |
|
847 asm("strlo r4, [r0], #4 "); // clear up to end of iMore[61] |
|
848 asm("blo 1b "); |
|
849 asm("mov r1, #%a0" : : "i" ((TInt)KMaxTInt)); |
|
850 asm("stmia r0!, {r1,r5-r7} "); // iExcCode=KMaxTInt, iCrashArgs[0...2]=0 |
|
851 asm("sub r0, r0, #1024 "); // r0 = &a |
|
852 #ifdef __CPU_HAS_VFP |
|
853 asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iMore[0])); |
|
854 VFP_FMXR(,VFP_XREG_FPEXC,2); // restore FPEXC |
|
855 __DATA_SYNC_BARRIER__(r4); |
|
856 __INST_SYNC_BARRIER__(r4); |
|
857 asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iA.iCPACR)); |
|
858 SET_CAR(,r2); // restore CPACR |
|
859 #endif |
|
860 asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iFlags)); |
|
861 asm("orr r1, r1, #0xC0 "); // interrupts off |
|
862 asm("msr cpsr, r1 "); // restore CPSR with interrupts off |
|
863 asm("ldmia r0, {r0-r11} "); // restore R4-R11 |
|
864 __JUMP(,lr); |
|
865 } |
|
866 |
|
867 |
|
868 /** Update the saved ARM registers with information from an exception |
|
869 |
|
870 @internalTechnology |
|
871 */ |
|
872 __NAKED__ void Arm::UpdateState(SFullArmRegSet&, TArmExcInfo&) |
|
873 { |
|
874 asm("ldmia r1!, {r2,r3,r12} "); |
|
875 asm("str r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iFlags)); |
|
876 asm("str r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iExcCode)); |
|
877 asm("str r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR13Svc)); |
|
878 asm("ldmia r1!, {r2,r3,r12} "); |
|
879 asm("str r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR4)); |
|
880 asm("str r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR5)); |
|
881 asm("str r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR6)); |
|
882 asm("ldmia r1!, {r2,r3,r12} "); |
|
883 asm("str r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR7)); |
|
884 asm("str r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR8)); |
|
885 asm("str r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR9)); |
|
886 asm("ldmia r1!, {r2,r3,r12} "); |
|
887 asm("str r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR10)); |
|
888 asm("str r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR11)); |
|
889 asm("str r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR14Svc)); |
|
890 asm("ldr r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iExcCode)); |
|
891 asm("ldmia r1!, {r2,r3} "); // r2=iFaultAddress, r3=iFaultStatus |
|
892 asm("cmp r12, #%a0 " : : "i" ((TInt)EArmExceptionPrefetchAbort)); |
|
893 asm("streq r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iB[0].iIFAR)); |
|
894 asm("strne r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iB[0].iDFAR)); |
|
895 asm("streq r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iB[0].iIFSR)); |
|
896 asm("strne r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iB[0].iDFSR)); |
|
897 asm("ldmia r1!, {r2,r3,r12} "); |
|
898 asm("str r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iSpsrSvc)); |
|
899 asm("str r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR13)); |
|
900 asm("str r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR14)); |
|
901 asm("ldmia r1!, {r2,r3,r12} "); |
|
902 asm("str r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR0)); |
|
903 asm("str r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR1)); |
|
904 asm("str r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR2)); |
|
905 asm("ldmia r1!, {r2,r3,r12} "); |
|
906 asm("str r2, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR3)); |
|
907 asm("str r3, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR12)); |
|
908 asm("str r12, [r0, #%a0]" : : "i" _FOFF(SFullArmRegSet,iN.iR15)); |
|
909 __JUMP(,lr); |
|
910 } |
|
911 |
|
912 |
|
913 /** Get a pointer to a stored integer register, accounting for registers which |
|
914 are banked across modes. |
|
915 |
|
916 @param a Pointer to saved register block |
|
917 @param aRegNum Number of register required, 0-15 or -1 (indicates SPSR) |
|
918 @param aMode Bottom 5 bits indicate which processor mode |
|
919 Other bits of aMode are ignored |
|
920 @return Pointer to the required saved register value |
|
921 |
|
922 @internalTechnology |
|
923 */ |
|
924 __NAKED__ TArmReg* Arm::Reg(SFullArmRegSet& /*a*/, TInt /*aRegNum*/, TArmReg /*aMode*/) |
|
925 { |
|
926 asm("cmp r1, #8 "); // register number < 8 ? |
|
927 asm("addlo r0, r0, r1, lsl #2 "); // register R0-R7 are not banked |
|
928 asm("blo 0f "); |
|
929 asm("cmp r1, #15 "); // register number = 15 ? |
|
930 asm("addeq r0, r0, r1, lsl #2 "); // register R15 not banked |
|
931 asm("movgt r0, #0 "); // no registers > 15 |
|
932 asm("bge 0f "); |
|
933 asm("cmn r1, #1 "); |
|
934 asm("movlt r0, #0 "); // no registers < -1 |
|
935 asm("blt 0f "); |
|
936 asm("and r12, r2, #0x1F "); |
|
937 asm("cmp r12, #0x11 "); // mode_fiq? |
|
938 asm("beq 1f "); // skip if it is |
|
939 asm("cmp r1, #13 "); |
|
940 asm("addlo r0, r0, r1, lsl #2 "); // register R8-R12 are only banked in mode_fiq |
|
941 asm("blo 0f "); |
|
942 asm("cmp r12, #0x10 "); // mode_usr ? |
|
943 asm("cmpne r12, #0x1F "); // if not, mode_sys ? |
|
944 asm("bne 2f "); // skip if neither |
|
945 asm("cmp r1, #16 "); |
|
946 asm("addlo r0, r0, r1, lsl #2 "); // handle R13_usr, R14_usr |
|
947 asm("movhs r0, #0 "); // no SPSR in mode_usr or mode_sys |
|
948 asm("blo 0f "); |
|
949 asm("1: "); // mode_fiq, regnum = 8-12 |
|
950 asm("2: "); // exception mode, regnum not 0-12 or 15 |
|
951 asm("cmn r1, #1 "); // regnum = -1 ? |
|
952 asm("moveq r1, #15 "); // if so, change to 15 |
|
953 asm("sub r1, r1, #13 "); |
|
954 asm("add r0, r0, r1, lsl #2 "); // add 0 for R13, 4 for R14, 8 for SPSR |
|
955 asm("cmp r12, #0x16 "); |
|
956 asm("addeq r0, r0, #12 "); // if mon, add offset from R13Fiq to R13Mon |
|
957 asm("cmpne r12, #0x11 "); |
|
958 asm("addeq r0, r0, #32 "); // if valid but not svc/abt/und/irq, add offset from R13Irq to R13Fiq |
|
959 asm("cmpne r12, #0x12 "); |
|
960 asm("addeq r0, r0, #12 "); // if valid but not svc/abt/und, add offset from R13Und to R13Irq |
|
961 asm("cmpne r12, #0x1b "); |
|
962 asm("addeq r0, r0, #12 "); // if valid but not svc/abt, add offset from R13Abt to R13Und |
|
963 asm("cmpne r12, #0x17 "); |
|
964 asm("addeq r0, r0, #12 "); // if valid but not svc, add offset from R13Svc to R13Abt |
|
965 asm("cmpne r12, #0x13 "); |
|
966 asm("addeq r0, r0, #%a0" : : "i" _FOFF(SFullArmRegSet, iN.iR13Svc)); // if valid mode add offset to R13Svc |
|
967 asm("movne r0, #0 "); |
|
968 asm("0: "); |
|
969 __JUMP(,lr); |
|
970 } |
|
971 |
|
972 |
|
973 /** Restore all the ARM registers |
|
974 |
|
975 @internalTechnology |
|
976 */ |
|
977 __NAKED__ void Arm::RestoreState(SFullArmRegSet&) |
|
978 { |
|
979 } |
|
980 |
|
981 |
|
982 |
|
983 |
|
984 |