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1 // Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // e32\nkernsmp\arm\nctimer.cia |
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15 // Fast Millisecond Timer Implementation |
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16 // |
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17 // |
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18 |
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19 #include <e32cia.h> |
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20 #include <arm.h> |
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21 |
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22 #ifdef __MSTIM_MACHINE_CODED__ |
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23 |
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24 |
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25 #ifdef _DEBUG |
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26 #define ASM_KILL_LINK(rp,rs) asm("mov "#rs", #0xdf ");\ |
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27 asm("orr "#rs", "#rs", "#rs", lsl #8 ");\ |
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28 asm("orr "#rs", "#rs", "#rs", lsl #16 ");\ |
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29 asm("str "#rs", ["#rp"] ");\ |
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30 asm("str "#rs", ["#rp", #4] "); |
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31 |
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32 #define ASM_KILL_LINK_OFFSET(rp,rs,offset) asm("mov "#rs", #0xdf ");\ |
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33 asm("orr "#rs", "#rs", "#rs", lsl #8 ");\ |
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34 asm("orr "#rs", "#rs", "#rs", lsl #16 ");\ |
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35 asm("str "#rs", ["#rp", #"#offset"] ");\ |
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36 asm("str "#rs", ["#rp", #"#offset"+4] "); |
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37 #else |
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38 #define ASM_KILL_LINK(rp,rs) |
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39 #define ASM_KILL_LINK_OFFSET(rp,rs,offset) |
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40 #endif |
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41 |
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42 #ifdef _DEBUG |
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43 #define __DEBUG_CALLBACK(n) asm("stmfd sp!, {r0-r3,r12,lr} "); \ |
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44 asm("ldr r0, __TheTimerQ "); \ |
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45 asm("ldr r12, [r0, #%a0]!" : : "i" _FOFF(NTimerQ,iDebugFn)); \ |
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46 asm("cmp r12, #0 "); \ |
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47 asm("movne r1, #" #n ); \ |
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48 asm("ldrne r0, [r0, #4] "); \ |
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49 asm("movne lr, pc "); \ |
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50 __JUMP(ne,r12); \ |
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51 asm("ldmfd sp!, {r0-r3,r12,lr} ") |
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52 #else |
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53 #define __DEBUG_CALLBACK(n) |
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54 #endif |
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55 |
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56 |
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57 /** Start a nanokernel timer in zero-drift periodic mode with ISR or DFC callback. |
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58 Queues the timer to expire in the specified number of nanokernel ticks, |
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59 measured from the time at which it last expired. This allows exact periodic |
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60 timers to be implemented with no drift caused by delays in requeueing the |
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61 timer. |
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62 The expiry handler will be called in the same context as the previous timer |
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63 expiry. Generally the way this is used is that NTimer::OneShot() is used to start |
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64 the first time interval and this specifies whether the callback is in ISR context |
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65 or in the context of the nanokernel timer thread (DfcThread1) or other Dfc thread. |
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66 The expiry handler then uses NTimer::Again() to requeue the timer. |
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67 |
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68 @param aTime Timeout in nanokernel ticks |
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69 @return KErrNone if no error |
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70 @return KErrInUse if timer is already active |
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71 @return KErrArgument if the requested expiry time is in the past |
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72 @pre Any context |
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73 */ |
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74 __NAKED__ EXPORT_C TInt NTimer::Again(TInt /*aTime*/) |
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75 { |
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76 asm("mrs r12, cpsr "); |
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77 INTS_OFF(r3, r12, INTS_ALL_OFF); // all interrupts off |
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78 asm("ldrb r3, [r0, #%a0]" : : "i" _FOFF(NTimer,iState)); // r3=iState |
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79 asm("ldr r2, __TheTimerQ "); |
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80 asm("cmp r3, #%a0" : : "i" ((TInt)EIdle)); |
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81 asm("ldreq r3, [r0, #%a0]" : : "i" _FOFF(NTimer,iTriggerTime)); // r3=iTriggerTime |
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82 asm("bne add_mscb_in_use "); // if already queued return KErrInUse |
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83 asm("add r3, r3, r1 "); // add requested time interval |
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84 asm("ldr r1, [r2, #%a0]" : : "i" _FOFF(NTimerQ,iMsCount)); // r1=iMsCount |
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85 asm("subs r1, r3, r1 "); // r1=trigger time-next tick time |
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86 asm("strpl r3, [r0, #%a0]" : : "i" _FOFF(NTimer,iTriggerTime)); // iTriggerTime+=aTime |
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87 asm("bpl AddMsCallBack "); // if time interval positive, ok |
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88 asm("mov r0, #%a0" : : "i" ((TInt)KErrArgument)); // else return KErrArgument |
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89 asm("b add_mscb_0 "); |
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90 } |
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91 |
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92 |
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93 /** Start a nanokernel timer in one-shot mode with ISR callback. |
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94 Queues the timer to expire in the specified number of nanokernel ticks. The |
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95 actual wait time will be at least that much and may be up to one tick more. |
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96 The expiry handler will be called in ISR context. |
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97 |
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98 @param aTime Timeout in nanokernel ticks |
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99 @return KErrNone if no error |
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100 @return KErrInUse if timer is already active |
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101 @pre Any context |
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102 */ |
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103 __NAKED__ EXPORT_C TInt NTimer::OneShot(TInt /*aTime*/) |
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104 { |
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105 asm("mov r2, #0 "); |
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106 // fall through |
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107 } |
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108 |
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109 |
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110 /** Start a nanokernel timer in one-shot mode with ISR or DFC callback. |
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111 Queues the timer to expire in the specified number of nanokernel ticks. The |
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112 actual wait time will be at least that much and may be up to one tick more. |
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113 The expiry handler will be called in either ISR context or in the context |
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114 of the nanokernel timer thread (DfcThread1). |
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115 |
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116 @param aTime Timeout in nanokernel ticks |
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117 @param aDfc TRUE if DFC callback required, FALSE if ISR callback required. |
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118 @return KErrNone if no error |
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119 @return KErrInUse if timer is already active |
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120 @pre Any context |
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121 */ |
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122 __NAKED__ EXPORT_C TInt NTimer::OneShot(TInt /*aTime*/, TBool /*aDfc*/) |
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123 { |
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124 asm("mrs r12, cpsr "); |
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125 INTS_OFF(r3, r12, INTS_ALL_OFF); // all interrupts off |
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126 asm("ldrb r3, [r0, #%a0]" : : "i" _FOFF(NTimer,iState)); // r3=iState |
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127 asm("cmp r3, #%a0" : : "i" ((TInt)EIdle)); |
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128 asm("bne add_mscb_in_use "); // if already queued return KErrInUse |
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129 asm("strb r2, [r0, #%a0]" : : "i" _FOFF(NTimer,iCompleteInDfc)); // iCompleteInDfc=aDfc |
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130 asm("ldr r2, __TheTimerQ "); |
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131 asm("ldr r3, [r2, #%a0]" : : "i" _FOFF(NTimerQ,iMsCount)); // r3=iMsCount |
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132 asm("add r3, r3, r1 "); |
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133 asm("str r3, [r0, #%a0]" : : "i" _FOFF(NTimer,iTriggerTime)); // iTriggerTime=ms count + aTime |
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134 |
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135 // r0->CallBack, r2=TheTimerQ, r1=time interval, r3=trigger time |
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136 asm("AddMsCallBack: "); |
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137 asm("cmp r1, #32 "); // compare interval with 32ms |
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138 asm("bge add_mscb_holding "); // if >=32ms put it on holding queue |
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139 asm("ldrb r1, [r0, #%a0]" : : "i" _FOFF(NTimer,iCompleteInDfc)); // r1=iCompleteInDfc |
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140 asm("and r3, r3, #0x1f "); // r3=trigger time & 0x1f |
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141 asm("cmp r1, #0 "); |
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142 asm("add r1, r2, r3, lsl #4 "); // r1->IntQ corresponding to trigger time |
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143 asm("addne r1, r1, #8 "); // if (iCompleteInDfc), r1 points to DfcQ |
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144 asm("ldr r3, [r1, #4] "); // r3=pQ->iA.iPrev |
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145 asm("str r0, [r1, #4] "); // pQ->iA.iPrev=pC |
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146 asm("str r0, [r3, #0] "); // pQ->iA.iPrev->iNext=pC |
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147 asm("stmia r0, {r1,r3} "); // pC->iNext=&pQ->iA, pC->iPrev=pQ->iA.iPrev |
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148 asm("mov r1, #%a0" : : "i" ((TInt)EFinal)); |
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149 asm("strb r1, [r0, #%a0]" : : "i" _FOFF(NTimer,iState)); // iState=EFinal |
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150 asm("ldr r0, [r0, #%a0]" : : "i" _FOFF(NTimer,iTriggerTime)); // r0=iTriggerTime |
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151 asm("ldr r3, [r2, #%a0]" : : "i" _FOFF(NTimerQ,iPresent)); // r3=TheTimerQ->iPresent |
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152 asm("and r0, r0, #0x1f "); |
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153 asm("mov r1, #1 "); |
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154 asm("orr r3, r3, r1, lsl r0 "); // iPresent |= (1<<index) |
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155 asm("str r3, [r2, #%a0]" : : "i" _FOFF(NTimerQ,iPresent)); |
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156 asm("mov r0, #0 "); // return KErrNone |
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157 asm("msr cpsr, r12 "); |
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158 __JUMP(,lr); |
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159 |
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160 asm("add_mscb_holding: "); |
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161 asm("ldr r3, [r2, #%a0]!" : : "i" _FOFF(NTimerQ,iHoldingQ.iA.iPrev)); // r3=pQ->iPrev, r2=&iHoldingQ.iA.iPrev |
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162 asm("mov r1, #%a0" : : "i" ((TInt)EHolding)); |
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163 asm("strb r1, [r0, #%a0]" : : "i" _FOFF(NTimer,iState)); // iState=EHolding |
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164 asm("str r0, [r2], #-4 "); // pQ->iPrev=pC, r2=&iHoldingQ |
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165 asm("str r0, [r3, #0] "); // pQ->iPrev->iNext=pC |
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166 asm("stmia r0, {r2,r3} "); // pC->iNext=pQ, pC->iPrev=pQ->iPrev |
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167 asm("mov r0, #0 "); // return KErrNone |
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168 |
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169 asm("add_mscb_0: "); |
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170 asm("msr cpsr, r12 "); |
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171 __JUMP(,lr); |
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172 |
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173 asm("add_mscb_in_use: "); |
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174 asm("mov r0, #%a0" : : "i" ((TInt)KErrInUse)); // return KErrInUse |
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175 asm("msr cpsr, r12 "); |
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176 __JUMP(,lr); |
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177 |
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178 asm("__TheTimerQ: "); |
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179 asm(".word TheTimerQ "); |
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180 } |
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181 |
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182 |
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183 /** Starts a nanokernel timer in one-shot mode with callback in dfc thread that provided DFC belongs to. |
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184 |
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185 Queues the timer to expire in the specified number of nanokernel ticks. The |
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186 actual wait time will be at least that much and may be up to one tick more. |
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187 On expiry aDfc will be queued in ISR context. |
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188 |
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189 Note that NKern::TimerTicks() can be used to convert milliseconds to ticks. |
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190 |
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191 @param aTime Timeout in nanokernel ticks |
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192 @param aDfc - Dfc to be queued when the timer expires. |
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193 |
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194 @return KErrNone if no error; KErrInUse if timer is already active. |
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195 |
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196 @pre Any context |
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197 |
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198 @see NKern::TimerTicks() |
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199 */ |
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200 |
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201 __NAKED__ EXPORT_C TInt NTimer::OneShot(TInt /*aTime*/, TDfc& /*aDfc*/) |
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202 { |
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203 asm("mrs r12, cpsr "); |
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204 INTS_OFF(r3, r12, INTS_ALL_OFF); // all interrupts off |
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205 asm("ldrb r3, [r0, #%a0]" : : "i" _FOFF(NTimer,iState)); // r3=iState |
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206 asm("cmp r3, #%a0" : : "i" ((TInt)EIdle)); |
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207 asm("bne add_mscb_in_use "); // if already queued return KErrInUse |
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208 asm("mov r3, #0 "); |
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209 asm("strb r3, [r0, #%a0]" : : "i" _FOFF(NTimer,iCompleteInDfc)); // iCompleteInDfc=0 |
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210 asm("str r3, [r0, #%a0]" : : "i" _FOFF(NTimer,iFunction)); // iFunction=NULL |
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211 asm("str r2, [r0, #%a0]" : : "i" _FOFF(NTimer,iPtr)); // iPtr= &aDfc |
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212 asm("ldr r2, __TheTimerQ "); |
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213 asm("ldr r3, [r2, #%a0]" : : "i" _FOFF(NTimerQ,iMsCount)); // r3=iMsCount |
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214 asm("add r3, r3, r1 "); |
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215 asm("str r3, [r0, #%a0]" : : "i" _FOFF(NTimer,iTriggerTime)); // iTriggerTime=ms count + aTime |
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216 asm("b AddMsCallBack "); |
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217 } |
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218 |
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219 |
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220 /** Cancel a nanokernel timer. |
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221 Removes this timer from the nanokernel timer queue. Does nothing if the |
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222 timer is inactive or has already expired. |
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223 Note that if the timer was queued and DFC callback requested it is possible |
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224 for the expiry handler to run even after Cancel() has been called. This will |
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225 occur in the case where DfcThread1 is preempted just before calling the |
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226 expiry handler for this timer and the preempting thread/ISR/IDFC calls |
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227 Cancel() on the timer. |
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228 |
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229 @pre Any context |
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230 */ |
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231 EXPORT_C __NAKED__ void NTimer::Cancel() |
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232 { |
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233 asm("mrs r12, cpsr "); |
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234 INTS_OFF(r3, r12, INTS_ALL_OFF); // all interrupts off |
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235 asm("ldrb r3, [r0, #%a0]" : : "i" _FOFF(NTimer,iState)); |
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236 asm("mov r1, #0 "); |
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237 asm("cmp r3, #%a0" : : "i" ((TInt)ETransferring)); |
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238 asm("bcc cancel_idle "); // if EIdle, nothing to do |
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239 asm("strb r1, [r0, #%a0]" : : "i" _FOFF(NTimer,iState)); // iState=EIdle |
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240 asm("beq cancel_xfer "); // if ETransferring, branch |
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241 asm("ldmia r0, {r1,r2} "); // If queued, dequeue - r1=next, r2=prev |
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242 asm("cmp r3, #%a0" : : "i" ((TInt)ECritical)); |
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243 asm("str r1, [r2, #0] "); // if queued, prev->next=next |
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244 asm("str r2, [r1, #4] "); // and next->prev=prev |
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245 ASM_KILL_LINK(r0,r1); |
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246 asm("ldrcs r1, __TheTimerQ "); |
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247 asm("ldrhi r0, [r0, #%a0]" : : "i" _FOFF(NTimer,iTriggerTime)); // r0=iTriggerTime |
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248 asm("ldrhi r3, [r1, #%a0]" : : "i" _FOFF(NTimerQ,iMsCount)); // r3=iMsCount |
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249 asm("bcc cancel_idle "); // if EHolding or EOrdered, finished |
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250 asm("beq cancel_critical "); // if ECritical, branch |
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251 // r1->ms timer, state was EFinal |
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252 asm("subs r3, r0, r3 "); // r3=trigger time - next tick |
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253 asm("bmi cancel_idle "); // if trigger time already expired, don't touch iPresent (was on iCompletedQ) |
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254 asm("and r0, r0, #0x1f "); // r0=iTriggerTime&0x1f = queue index |
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255 asm("mov r3, r1 "); |
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256 asm("ldr r2, [r3, r0, lsl #4]! "); // r3->iIntQ for this timer, r2=iIntQ head pointer |
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257 asm("cmp r2, r3 "); |
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258 asm("bne cancel_idle "); // iIntQ not empty so finished |
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259 asm("ldr r2, [r3, #8]! "); // r2=iDfcQ head pointer |
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260 asm("cmp r2, r3 "); |
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261 asm("bne cancel_idle "); // iDfcQ not empty so finished |
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262 asm("ldr r2, [r1, #%a0]" : : "i" _FOFF(NTimerQ,iPresent)); // r2=TheTimerQ->iPresent |
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263 asm("mov r3, #1 "); |
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264 asm("bic r2, r2, r3, lsl r0 "); // iPresent &= ~(1<<index) |
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265 asm("str r2, [r1, #%a0]" : : "i" _FOFF(NTimerQ,iPresent)); |
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266 |
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267 asm("cancel_idle: "); |
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268 asm("msr cpsr, r12 "); |
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269 __JUMP(,lr); |
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270 |
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271 asm("cancel_xfer: "); |
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272 asm("ldr r1, __TheTimerQ "); // r1->ms timer, state was ETransferring |
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273 asm("strb r3, [r1, #%a0]" : : "i" _FOFF(NTimerQ,iTransferringCancelled)); |
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274 asm("msr cpsr, r12 "); |
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275 __JUMP(,lr); |
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276 |
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277 asm("cancel_critical: "); // r1->ms timer, state was ECritical |
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278 asm("strb r3, [r1, #%a0]" : : "i" _FOFF(NTimerQ,iCriticalCancelled)); |
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279 asm("msr cpsr, r12 "); |
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280 __JUMP(,lr); |
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281 } |
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282 |
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283 |
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284 /** Return the number of ticks before the next nanokernel timer expiry. |
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285 May on occasion return a pessimistic estimate (i.e. too low). |
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286 Used by base port to disable the system tick interrupt when the system |
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287 is idle. |
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288 |
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289 @return The number of ticks before the next nanokernel timer expiry. |
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290 |
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291 @pre Interrupts must be disabled. |
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292 |
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293 @post Interrupts are disabled. |
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294 */ |
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295 EXPORT_C __NAKED__ TInt NTimerQ::IdleTime() |
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296 { |
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297 ASM_CHECK_PRECONDITIONS(MASK_INTERRUPTS_DISABLED); |
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298 |
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299 asm("ldr r12, __TheTimerQ "); |
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300 asm("mvn r0, #0x80000000 "); // set r0=KMaxTInt initially |
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301 asm("ldr r2, [r12, #%a0]!" : : "i" _FOFF(NTimerQ,iOrderedQ)); // r12->iOrderedQ, r2=iOrderedQ first |
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302 asm("ldr r3, [r12, #-12] "); // r3=next tick number |
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303 asm("cmp r2, r12 "); // check if iOrderedQ empty |
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304 asm("ldrne r0, [r2, #%a0]" : : "i" _FOFF(NTimer,iTriggerTime)); // if not, r0=ordered Q first->trigger time |
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305 asm("ldr r1, [r12, #-8]! "); // r1=iHoldingQ first, r12->iHoldingQ |
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306 asm("bicne r0, r0, #0x0f "); |
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307 asm("subne r0, r0, #16 "); // r0=tick at which transfer to final queue would occur |
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308 asm("subne r0, r0, r3 "); // return value = trigger time - iMsCount |
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309 asm("cmp r1, r12 "); // holding Q empty? |
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310 asm("ldr r1, [r12, #-8] "); // r1=iPresent |
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311 asm("and r12, r3, #0x1f "); // r12=next tick mod 32 |
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312 asm("beq 1f "); // branch if holding Q empty |
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313 asm("ands r2, r3, #0x0f "); // else r2=next tick no. mod 16 |
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314 asm("rsbne r2, r2, #16 "); // if nonzero, subtract from 16 to give #ticks before next multiple of 16 |
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315 asm("cmp r2, r0 "); |
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316 asm("movlt r0, r2 "); // update result if necessary |
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317 asm("1: "); |
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318 asm("movs r1, r1, ror r12 "); // r1=iPresent rotated so that LSB corresponds to next tick |
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319 __JUMP(eq,lr); // if iPresent=0, finished |
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320 asm("mov r3, #0 "); // r3 will accumulate bit number of least significant 1 |
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321 asm("movs r2, r1, lsl #16 "); |
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322 asm("movne r1, r2 "); |
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323 asm("addeq r3, r3, #16 "); |
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324 asm("movs r2, r1, lsl #8 "); |
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325 asm("movne r1, r2 "); |
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326 asm("addeq r3, r3, #8 "); |
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327 asm("movs r2, r1, lsl #4 "); |
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328 asm("movne r1, r2 "); |
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329 asm("addeq r3, r3, #4 "); |
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330 asm("movs r2, r1, lsl #2 "); |
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331 asm("movne r1, r2 "); |
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332 asm("addeq r3, r3, #2 "); |
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333 asm("movs r2, r1, lsl #1 "); |
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334 asm("addeq r3, r3, #1 "); |
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335 asm("cmp r3, r0 "); |
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336 asm("movlt r0, r3 "); // update result if necessary |
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337 __JUMP(,lr); |
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338 } |
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339 |
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340 |
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341 /** Tick over the nanokernel timer queue. |
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342 This function should be called by the base port in the system tick timer ISR. |
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343 It should not be called at any other time. |
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344 The value of 'this' to pass is the value returned by NTimerQ::TimerAddress(). |
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345 |
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346 @see NTimerQ::TimerAddress() |
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347 */ |
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348 __NAKED__ EXPORT_C void NTimerQ::Tick() |
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349 { |
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350 // Enter with r0 pointing to NTimerQ |
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351 asm("ldr r1, __TheScheduler "); |
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352 asm("mrs r12, cpsr "); |
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353 |
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354 // do the timeslice tick - on ARM __SCHEDULER_MACHINE_CODED is mandatory |
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355 asm("ldr r2, [r1, #%a0]" : : "i" _FOFF(TScheduler,iCurrentThread)); |
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356 asm("ldr r3, [r2, #%a0]" : : "i" _FOFF(NThread,iTime)); |
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357 asm("subs r3, r3, #1 "); |
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358 asm("strge r3, [r2, #%a0]" : : "i" _FOFF(NThread,iTime)); |
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359 asm("streqb r12, [r1, #%a0]" : : "i" _FOFF(TScheduler,iRescheduleNeededFlag)); // r12 lower byte is never 0 |
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360 INTS_OFF(r3, r12, INTS_ALL_OFF); // disable all interrupts |
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361 |
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362 asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(NTimerQ,iMsCount)); // r1=iMsCount |
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363 asm("ldr r3, [r0, #%a0]" : : "i" _FOFF(NTimerQ,iPresent)); // r3=iPresent |
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364 asm("and r2, r1, #0x1f "); // r2=iMsCount & 0x1f |
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365 asm("add r1, r1, #1 "); |
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366 asm("str r1, [r0, #%a0]" : : "i" _FOFF(NTimerQ,iMsCount)); // iMsCount++ |
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367 asm("mov r1, #1 "); |
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368 asm("tst r3, r1, lsl r2 "); // test iPresent bit for this tick |
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369 asm("bic r1, r3, r1, lsl r2 "); // clear iPresent bit |
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370 asm("strne r1, [r0, #%a0]" : : "i" _FOFF(NTimerQ,iPresent)); // update iPresent if necessary |
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371 asm("bne mstim_tick_1 "); // if bit was set, we have work to do |
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372 asm("tst r2, #0x0f "); // else test for tick 0 or 16 |
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373 asm("msrne cpsr_c, r12 "); // if neither return |
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374 __JUMP(ne,lr); |
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375 |
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376 asm("mstim_tick_1: "); // get here if timers complete this tick |
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377 asm("stmfd sp!, {r4-r6,lr} "); |
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378 asm("add r1, r0, r2, lsl #4 "); // r1->IntQ for this tick |
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379 asm("ldr r3, [r1, #8]! "); // r1->DfcQ and r3=DfcQ first |
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380 asm("mov r5, #0 "); // r5=doDfc=FALSE |
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381 asm("cmp r3, r1 "); |
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382 asm("beq mstim_tick_2 "); // skip if DfcQ empty |
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383 |
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384 // Move DFC completions from iDfcQ to iCompletedQ |
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385 asm("ldr lr, [r0, #%a0]" : : "i" _FOFF(NTimerQ,iCompletedQ.iA.iPrev)); // lr=last completed |
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386 asm("ldr r4, [r1, #4] "); // r4=DfcQ last |
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387 asm("add r5, r0, #%a0" : : "i" _FOFF(NTimerQ,iDfc)); // doDfc=TRUE |
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388 asm("str r3, [lr, #0] "); // old last pending->next = DfcQ first |
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389 asm("str r4, [r0, #%a0]" : : "i" _FOFF(NTimerQ,iCompletedQ.iA.iPrev)); // last pending=DfcQ last |
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390 asm("str lr, [r3, #4] "); // DfcQ first->prev = old last pending |
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391 asm("add lr, r0, #%a0" : : "i" _FOFF(NTimerQ,iCompletedQ)); // lr=&iCompletedQ.iA |
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392 asm("str lr, [r4, #0] "); // DfcQ last->next=&iPending |
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393 asm("str r1, [r1, #0] "); // DfcQ first=&DfcQ |
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394 asm("str r1, [r1, #4] "); // DfcQ last=&DfcQ |
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395 |
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396 asm("mstim_tick_2: "); |
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397 asm("tst r2, #0x0f "); // check for tick 0 or 16 |
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398 asm("bne mstim_tick_3 "); // skip if not |
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399 |
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400 // Tick 0 or 16 - must check holding queue and ordered queue |
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401 asm("ldr r3, [r0, #%a0]" : : "i" _FOFF(NTimerQ,iHoldingQ)); // r3=iHoldingQ first |
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402 asm("add r6, r0, #%a0" : : "i" _FOFF(NTimerQ,iHoldingQ)); // r6=&iHoldingQ |
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403 asm("cmp r3, r6 "); |
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404 asm("addne r5, r0, #%a0" : : "i" _FOFF(NTimerQ,iDfc)); // if iHoldingQ nonempty, doDfc=TRUE and skip ordered queue check |
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405 asm("bne mstim_tick_3 "); // skip if iHoldingQ nonempty |
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406 asm("ldr r3, [r0, #%a0]" : : "i" _FOFF(NTimerQ,iOrderedQ)); // r3=iOrderedQ first |
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407 asm("add r6, r0, #%a0" : : "i" _FOFF(NTimerQ,iOrderedQ)); // r6=&iOrderedQ |
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408 asm("cmp r3, r6 "); |
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409 asm("beq mstim_tick_3 "); // skip if iOrderedQ empty |
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410 asm("ldr r4, [r0, #%a0]" : : "i" _FOFF(NTimerQ,iMsCount)); // else r4=iMsCount |
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411 asm("ldr r3, [r3, #%a0]" : : "i" _FOFF(NTimer,iTriggerTime)); // and r3=trigger time of first on ordered queue |
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412 asm("sub r3, r3, r4 "); // r3=trigger time-iMsCount |
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413 asm("cmp r3, #31 "); |
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414 asm("addls r5, r0, #%a0" : : "i" _FOFF(NTimerQ,iDfc)); // if first expiry in <=31ms, doDfc=TRUE |
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415 |
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416 // Check iIntQ |
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417 asm("mstim_tick_3: "); |
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418 asm("ldr r3, [r1, #-8]! "); // r1->iIntQ, r3=iIntQ first |
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419 asm("mov r6, r12 "); // r6=original cpsr |
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420 asm("cmp r3, r1 "); // test if iIntQ empty |
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421 asm("beq mstim_tick_4 "); // branch if it is |
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422 |
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423 // Transfer iIntQ to a temporary queue |
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424 asm("ldr r4, [r1, #4] "); // r4=iIntQ last |
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425 asm("str r1, [r1, #0] "); // clear iIntQ |
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426 asm("str r1, [r1, #4] "); |
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427 asm("stmfd sp!, {r3,r4} "); // copy queue onto stack |
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428 asm("str sp, [r4, #0] "); // iIntQ last->next=sp |
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429 asm("str sp, [r3, #4] "); // iIntQ first->prev=sp |
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430 INTS_OFF_1(r4, r6, INTS_ALL_OFF); // r4=cpsr with all interrupts off |
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431 |
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432 // Walk the temporary queue and complete timers |
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433 asm("mstim_tick_5: "); |
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434 INTS_OFF_2(r4, r6, INTS_ALL_OFF); // all interrupts off |
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435 asm("ldr r0, [sp, #0] "); // r0=q.iNext |
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436 asm("mov r3, #%a0" : : "i" ((TInt)NTimer::EIdle)); |
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437 asm("cmp r0, sp "); // end of queue? |
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438 asm("beq mstim_tick_6 "); // if so, branch out |
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439 asm("ldmia r0!, {r1,r2} "); // r1=next r2=prev, r0->iPtr |
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440 asm("strb r3, [r0, #%a0]" : : "i" (_FOFF(NTimer,iState)-8)); // iState=EIdle |
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441 ASM_KILL_LINK_OFFSET(r0,r12,-8); |
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442 asm("ldmia r0, {r0,r12} "); // r0=iPtr, r12=iFunction |
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443 asm("str r1, [r2, #0] "); // prev->next=next |
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444 asm("str r2, [r1, #4] "); // next->prev=prev |
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445 asm("adr lr, mstim_tick_5 "); // return to mstim_tick_5 |
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446 asm("msr cpsr, r6 "); // restore interrupts |
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447 asm("cmp r12, #0 "); // iFunction==NULL ? |
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448 asm("beq mstim_tick_7 "); // if so queue Dfc (iPtr is a pointer to TDfc ) |
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449 __JUMP(,r12); // call timer callback with r0=iPtr |
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450 asm("b mstim_tick_6 "); // skip queuing of Dfc |
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451 |
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452 asm("mstim_tick_7: "); |
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453 asm("b " CSM_ZN4TDfc3AddEv); // add the DFC with r0=iPtr - a pointer to TDfc |
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454 |
|
455 asm("mstim_tick_6: "); |
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456 asm("add sp, sp, #8 "); // take temporary queue off stack |
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457 |
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458 asm("mstim_tick_4: "); |
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459 asm("msr cpsr, r6 "); // restore original interrupt state |
|
460 asm("movs r0, r5 "); // DFC needed? if so, r0->iDfc |
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461 asm("ldmfd sp!, {r4-r6,lr} "); // restore registers |
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462 asm("bne " CSM_ZN4TDfc3AddEv); // add the DFC if required |
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463 __JUMP(,lr); // if no DFC needed, return |
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464 |
|
465 asm("__TheScheduler: "); |
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466 asm(".word TheScheduler "); |
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467 } |
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468 |
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469 __NAKED__ void NTimerQ::DfcFn(TAny* /*aPtr*/) |
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470 { |
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471 // Enter with r0 pointing to NTimerQ |
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472 asm("stmfd sp!, {r7-r11,lr} "); |
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473 SET_INTS_1(r11, MODE_SVC, INTS_ALL_ON); // always called from SVC mode |
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474 SET_INTS_1(r10, MODE_SVC, INTS_ALL_OFF); // with interruts enabled |
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475 |
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476 // First transfer entries on the Ordered queue to the Final queues |
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477 asm("mstim_dfc_0: "); |
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478 SET_INTS_2(r10, MODE_SVC, INTS_ALL_OFF); // disable interrupts |
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479 asm("ldr r1, [r0, #%a0]!" : : "i" _FOFF(NTimerQ,iOrderedQ)); // r0->iOrderedQ, r1=orderedQ first |
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480 asm("cmp r1, r0 "); |
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481 asm("beq mstim_dfc_1 "); // ordered Q empty so move to next stage |
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482 asm("ldr r2, [r1, #%a0]" : : "i" _FOFF(NTimer,iTriggerTime)); // r2=r1->trigger time |
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483 asm("ldr r3, [r0, #-12] "); // r3=iMsCount |
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484 asm("subs r3, r2, r3 "); // r3=trigger time-iMsCount |
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485 asm("cmp r3, #31 "); // test if remaining time <32ms or has already passed |
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486 asm("bgt mstim_dfc_1 "); // if >31ms, move to next stage (signed comparison to catch already passed case) |
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487 asm("sub r0, r0, #%a0" : : "i" _FOFF(NTimerQ,iOrderedQ)); // r0->NTimerQ |
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488 asm("bl dequeaddfinal "); // <=31ms, so deque and add to final queue |
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489 SET_INTS_2(r11, MODE_SVC, INTS_ALL_ON); // let interrupts in |
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490 __DEBUG_CALLBACK(0); |
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491 asm("b mstim_dfc_0 "); |
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492 |
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493 asm("mstim_dfc_1: "); |
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494 SET_INTS_2(r11, MODE_SVC, INTS_ALL_ON); // let interrupts in |
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495 asm("sub r0, r0, #%a0" : : "i" _FOFF(NTimerQ,iOrderedQ)); // r0->NTimerQ |
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496 __DEBUG_CALLBACK(1); |
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497 |
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498 // Next transfer entries on the Holding queue to the Ordered queue or final queue |
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499 asm("mstim_dfc_2: "); |
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500 SET_INTS_2(r10, MODE_SVC, INTS_ALL_OFF); // disable interrupts |
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501 asm("ldr r1, [r0, #%a0]!" : : "i" _FOFF(NTimerQ,iHoldingQ)); // r0->iHoldingQ, r1=holdingQ first |
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502 asm("cmp r1, r0 "); |
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503 asm("beq mstim_dfc_3 "); // holding Q empty so move to next stage |
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504 asm("ldr r2, [r1, #%a0]" : : "i" _FOFF(NTimer,iTriggerTime)); // r2=r1->trigger time |
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505 asm("ldr r3, [r0, #-4] "); // r3=iMsCount |
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506 asm("sub r0, r0, #%a0" : : "i" _FOFF(NTimerQ,iHoldingQ)); // r0->NTimerQ |
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507 asm("subs r3, r2, r3 "); // r3=trigger time-iMsCount |
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508 asm("cmp r3, #31 "); // test if remaining time <32ms or has already passed |
|
509 asm("bgt mstim_dfc_4 "); // if >31ms, need to put it on the ordered Q (signed comparison to catch late case) |
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510 asm("bl dequeaddfinal "); // <=31ms or already passed, so deque and add to final queue |
|
511 |
|
512 asm("mstim_dfc_7: "); |
|
513 SET_INTS_2(r11, MODE_SVC, INTS_ALL_ON); // let interrupts in |
|
514 __DEBUG_CALLBACK(2); |
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515 asm("b mstim_dfc_2 "); // process next holding Q entry |
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516 |
|
517 // need to put entry r1 trigger time r2 on the ordered Q |
|
518 asm("mstim_dfc_4: "); |
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519 asm("ldmia r1, {r3,r12} "); // r3=r1->next, r12=r1->prev |
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520 asm("mov r9, #0 "); |
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521 asm("strb r9, [r0, #%a0]" : : "i" _FOFF(NTimerQ,iTransferringCancelled)); // iTransferringCancelled=0 |
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522 asm("str r3, [r12, #0] "); // prev->next=next |
|
523 asm("str r12, [r3, #4] "); // next->prev=prev |
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524 asm("mov r3, #%a0" : : "i" ((TInt)NTimer::ETransferring)); |
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525 asm("strb r3, [r1, #%a0]" : : "i" _FOFF(NTimer,iState)); // r1->iState=ETransferring |
|
526 |
|
527 asm("mstim_dfc_5: "); |
|
528 SET_INTS_2(r11, MODE_SVC, INTS_ALL_ON); // let interrupts in |
|
529 asm("add lr, r0, #%a0" : : "i" _FOFF(NTimerQ,iOrderedQ)); // lr=&iOrderedQ.iA |
|
530 __DEBUG_CALLBACK(3); |
|
531 SET_INTS_2(r10, MODE_SVC, INTS_ALL_OFF); // disable interrupts |
|
532 |
|
533 asm("mstim_dfc_9: "); |
|
534 asm("ldrb r12, [r0, #%a0]" : : "i" _FOFF(NTimerQ,iTransferringCancelled)); |
|
535 asm("ldr r3, [lr, #0] "); // r3=iOrderedQ first |
|
536 asm("cmp r12, #0 "); |
|
537 asm("bne mstim_dfc_7 "); // Entry r1 has been cancelled so move to next one |
|
538 asm("strb r9, [r0, #%a0]" : : "i" _FOFF(NTimerQ,iCriticalCancelled)); // iCriticalCancelled=0 |
|
539 |
|
540 // Walk iOrderedQ to find correct position for this entry |
|
541 asm("mstim_dfc_6: "); |
|
542 asm("cmp r3, lr "); // reached end of ordered Q? |
|
543 asm("ldrne r12, [r3, #%a0]" : : "i" _FOFF(NTimer,iTriggerTime)); // if not, r12=r3->trigger time |
|
544 asm("beq mstim_dfc_8 "); // branch if we have |
|
545 asm("mov r8, #%a0" : : "i" ((TInt)NTimer::ECritical)); |
|
546 asm("subs r12, r12, r2 "); // r12=r3->trigger - r1->trigger |
|
547 asm("bpl mstim_dfc_8 "); // branch if r3 expires after r1 |
|
548 asm("strb r8, [r3, #%a0]" : : "i" _FOFF(NTimer,iState)); // r3->iState=ECritical |
|
549 SET_INTS_2(r11, MODE_SVC, INTS_ALL_ON); // let interrupts in |
|
550 asm("mov r8, #%a0" : : "i" ((TInt)NTimer::EOrdered)); |
|
551 __DEBUG_CALLBACK(4); |
|
552 SET_INTS_2(r10, MODE_SVC, INTS_ALL_OFF); // disable interrupts |
|
553 asm("ldr r12, [r0, #%a0]" : : "i" _FOFF(NTimerQ,iTransferringCancelled)); |
|
554 asm("tst r12, #0xff00 "); // test iCriticalCancelled |
|
555 asm("streqb r8, [r3, #%a0]" : : "i" _FOFF(NTimer,iState)); // if not set, r3->iState=EOrdered |
|
556 asm("cmp r12, #0 "); // test iTransferringCancelled and iCriticalCancelled |
|
557 asm("ldreq r3, [r3, #0] "); // if neither set r3=r3->iNext |
|
558 asm("beq mstim_dfc_6 "); // and inspect next ordered Q entry |
|
559 asm("b mstim_dfc_9 "); // if either set, start again from beginning of ordered Q |
|
560 |
|
561 asm("mstim_dfc_8: "); // if we get to here we need to insert r1 before r3 |
|
562 asm("ldr r12, [r3, #4] "); // r12=r3->iPrev |
|
563 asm("mov r8, #%a0" : : "i" ((TInt)NTimer::EOrdered)); |
|
564 asm("strb r8, [r1, #%a0]" : : "i" _FOFF(NTimer,iState)); // r1->iState=EOrdered |
|
565 asm("str r1, [r3, #4] "); // r3->prev=r1 |
|
566 asm("str r1, [r12, #0] "); // r3->prev->next=r1 |
|
567 asm("stmia r1, {r3,r12} "); // r1->next=r3, r1->prev=r3->prev |
|
568 SET_INTS_2(r11, MODE_SVC, INTS_ALL_ON); // let interrupts in |
|
569 __DEBUG_CALLBACK(5); |
|
570 asm("b mstim_dfc_2 "); // process next holding Q entry |
|
571 |
|
572 // Get here when all holding Q entries processed |
|
573 asm("mstim_dfc_3: "); |
|
574 SET_INTS_2(r11, MODE_SVC, INTS_ALL_ON); // let interrupts in |
|
575 __DEBUG_CALLBACK(6); |
|
576 asm("add r8, r0, #16 "); // r8->iCompletedQ |
|
577 |
|
578 // Finally do call backs for timers which requested DFC callback |
|
579 asm("mstim_dfc_10: "); |
|
580 SET_INTS_2(r10, MODE_SVC, INTS_ALL_OFF); // disable interrupts |
|
581 asm("ldr r9, [r8, #0] "); // r9=completed Q first |
|
582 asm("mov r3, #%a0" : : "i" ((TInt)NTimer::EIdle)); |
|
583 asm("cmp r9, r8 "); // Is completed Q empty? |
|
584 asm("beq mstim_dfc_11 "); // branch out if it is |
|
585 asm("ldmia r9!, {r1,r2} "); // r1=r9->next, r2=r9->prev, r9->iPtr of completed entry |
|
586 asm("strb r3, [r9, #%a0]" : : "i" (_FOFF(NTimer,iState)-8)); // iState=EIdle for completed entry |
|
587 asm("ldmia r9, {r0,r3} "); // r0=iPtr, r3=function address |
|
588 ASM_KILL_LINK_OFFSET(r9,r12,-8); |
|
589 asm("str r1, [r2, #0] "); // prev->next=next |
|
590 asm("str r2, [r1, #4] "); // next->prev=prev |
|
591 SET_INTS_2(r11, MODE_SVC, INTS_ALL_ON); // let interrupts in |
|
592 __DEBUG_CALLBACK(7); |
|
593 asm("adr lr, mstim_dfc_10 "); // return to mstim_dfc_10 |
|
594 __JUMP(,r3); // call back with r0=iPtr |
|
595 |
|
596 // All done |
|
597 asm("mstim_dfc_11: "); |
|
598 SET_INTS_2(r11, MODE_SVC, INTS_ALL_ON); // let interrupts in |
|
599 asm("ldmfd sp!, {r7-r11,pc} "); // and return |
|
600 |
|
601 // Subroutine dequeaddfinal |
|
602 // Deque the NTimer pointed to by r1 and put it on its final queue |
|
603 // Enter with r0->NTimerQ, r1->NTimer, r2=r1->iTriggerTime |
|
604 // Enter and leave with interrupts disabled |
|
605 // Can modify r1-r3,r8,r9,r12 |
|
606 asm("dequeaddfinal: "); |
|
607 asm("ldmia r1, {r8,r9} "); // r8=r1->next, r9=r1->prev |
|
608 asm("mov r3, #%a0" : : "i" ((TInt)NTimer::EFinal)); |
|
609 asm("strb r3, [r1, #%a0]" : : "i" _FOFF(NTimer,iState)); // iState=EFinal |
|
610 asm("str r8, [r9, #0] "); // prev->next=next |
|
611 asm("str r9, [r8, #4] "); // next->prev=prev |
|
612 asm("ldr r12, [r0, #%a0]" : : "i" _FOFF(NTimerQ,iPresent)); // r12=timer iPresent |
|
613 asm("and r2, r2, #0x1f "); // r2=trigger time & 0x1f |
|
614 asm("mov r3, #1 "); |
|
615 asm("orr r12, r12, r3, lsl r2 "); // set bit in iPresent |
|
616 asm("ldrb r3, [r1, #%a0]" : : "i" _FOFF(NTimer,iCompleteInDfc)); // r3=iCompleteInDfc |
|
617 asm("str r12, [r0, #%a0]" : : "i" _FOFF(NTimerQ,iPresent)); |
|
618 asm("add r2, r0, r2, lsl #4 "); // r2->iIntQ for this timer |
|
619 asm("cmp r3, #0 "); |
|
620 asm("addne r2, r2, #8 "); // if iCompleteInDfc, r2->iDfcQ for this timer |
|
621 asm("ldr r12, [r2, #4] "); // r12->last on queue |
|
622 asm("str r1, [r2, #4] "); // queue->last=this |
|
623 asm("str r1, [r12, #0] "); // last->next=this |
|
624 asm("stmia r1, {r2,r12} "); // this->next=&queue, this->prev=last on queue |
|
625 __JUMP(,lr); |
|
626 } |
|
627 #endif |
|
628 |