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1 // Copyright (c) 2005-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // e32test\debug\d_debugapi.cia |
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15 // |
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16 // |
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17 |
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18 #include <arm.h> |
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19 #include "d_debugapi.h" |
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20 |
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21 __NAKED__ TInt DDebugAPIChecker::ReadFromOtherProcessArmv6() |
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22 { |
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23 |
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24 //Save regs. |
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25 asm("stmfd sp!,{r4-r7,lr}"); |
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26 |
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27 //Copy all data we need into regs. We can not access the memory of ... |
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28 //...the current process once we start changing MMU content. |
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29 asm("ldr r1, [r0, #%a0]" : : "i" _FOFF(DDebugAPIChecker, iOtherProcess_OsAsid)); |
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30 asm("ldr r2, [r0, #%a0]" : : "i" _FOFF(DDebugAPIChecker, iOtherProcess_LocalPageDir)); |
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31 asm("ldr r3, [r0, #%a0]" : : "i" _FOFF(DDebugAPIChecker, iCurrentProcess_OsAsid)); |
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32 asm("ldr r4, [r0, #%a0]" : : "i" _FOFF(DDebugAPIChecker, iCurrentProcess_LocalPageDir)); |
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33 asm("ldr r5, [r0, #%a0]" : : "i" _FOFF(DDebugAPIChecker, iAddress)); |
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34 |
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35 asm("mrc p15, 0, r6, c2, c0, 0 "); |
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36 asm("and r6, r6, #0x7f "); // r6 = page table cache/sharing attributes |
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37 asm("orr r2, r2, r6 "); // add in to other process page directory address |
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38 asm("orr r4, r4, r6 "); // add in to this process page directory address |
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39 asm("mov r6, #0 "); |
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40 |
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41 //Disable interrupts |
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42 asm("mov r7, #0xd3 "); |
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43 asm("msr cpsr, r7 "); |
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44 |
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45 //Switch MMU to the-other-process |
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46 asm("mcr p15, 0, r6, c7, c10, 4 "); // drain write buffer before changing MMU registers (see ARMv6 specs) |
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47 //! asm("orr r2, r2 #0x18"); //Uncomment this line on 1136 (r0p2) with L2 cache due to Erratum 317041. |
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48 asm("mcr p15, 0, r2, c2, c0, 0 "); // set TTBR0 - no TLB flush required due to ASID |
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49 asm("mcr p15, 0, r1, c13, c0, 1 "); // set ASID |
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50 |
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51 //Read the memory from the-other-process |
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52 asm("ldr r0, [r5]"); |
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53 |
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54 //Switch MMU back to the-current-process |
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55 asm("mcr p15, 0, r6, c7, c10, 4 "); // drain write buffer before changing MMU registers (see ARMv6 specs) |
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56 //! asm("orr r4, r4 #0x18"); //Uncomment this line on 1136 (r0p2) with L2 cache due to Erratum 317041. |
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57 asm("mcr p15, 0, r4, c2, c0, 0 "); // set TTBR0 - no TLB flush required due to ASID |
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58 asm("mcr p15, 0, r3, c13, c0, 1 "); // set ASID |
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59 |
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60 |
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61 //Re-enable interrupts |
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62 asm("mov r7, #0x13 "); |
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63 asm("msr cpsr, r7 "); |
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64 |
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65 //Return |
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66 asm("ldmfd sp!,{r4-r7,pc}"); |
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67 } |