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1 // Copyright (c) 2006-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // e32test\mmu\d_cache.cia |
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15 // See e32test\mmu\t_cache.cpp for details |
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16 // |
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17 // |
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18 |
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19 |
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20 #ifndef __KERNEL_MODE__ |
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21 #include <u32std.h> |
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22 #else |
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23 #include <u32std.h> |
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24 #include "nk_cpu.h" |
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25 |
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26 |
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27 #if defined(__CPU_ARMV7) |
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28 /**Returns Cache Type Register content*/ |
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29 __NAKED__ TUint32 CacheTypeRegister() |
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30 { |
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31 asm("mrc p15, 0, r0, c0, c0, 1 "); |
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32 __JUMP(,lr); |
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33 } |
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34 |
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35 /**Returns Cache Level ID Register content*/ |
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36 __NAKED__ TUint32 CacheLevelIDRegister() |
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37 { |
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38 asm("mrc p15, 1, r0, c0, c0, 1 "); |
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39 __JUMP(,lr); |
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40 } |
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41 |
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42 /** |
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43 Returns Cache Size Id Register content for the given cache level/type |
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44 @param aType Cache type: 0=data/unified, 1=code |
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45 @param aLevel Cache level: 0=Level1 ... 7=Level8 |
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46 */ |
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47 __NAKED__ TUint32 CacheSizeIdRegister(TUint32 /*aType*/, TUint32 /*aLevel*/) |
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48 { |
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49 asm("orr r0, r1, lsl #1"); // r0 = entry for Cache Size Selection Reg. |
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50 asm("mcr p15, 2, r0, c0, c0, 0 "); // set Cache Size Selection Register |
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51 ARM_ISBSY; |
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52 asm("mrc p15, 1, r0, c0, c0, 0 "); // read Cache Size Id Register |
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53 __JUMP(,lr); |
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54 } |
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55 #endif |
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56 |
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57 |
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58 #if defined(__CPU_MEMORY_TYPE_REMAPPING) |
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59 /** Returns Coprocessor Control Register*/ |
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60 __NAKED__ TUint32 CtrlRegister() |
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61 { |
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62 asm("mrc p15, 0, r0, c1, c0, 0 ");//read CR reg. |
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63 __JUMP(,lr); |
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64 } |
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65 |
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66 /** Returns PRRR Register*/ |
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67 __NAKED__ TUint32 PRRRRegister() |
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68 { |
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69 asm("mrc p15, 0, r0, c10, c2, 0 "); |
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70 __JUMP(,lr); |
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71 } |
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72 |
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73 /** Returns NRRR Register*/ |
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74 __NAKED__ TUint32 NRRRRegister() |
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75 { |
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76 asm("mrc p15, 0, r0, c10, c2, 1 "); |
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77 __JUMP(,lr); |
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78 } |
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79 |
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80 /** Sets PRRR Register*/ |
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81 __NAKED__ void SetPRRR(TUint32) |
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82 { |
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83 asm("mcr p15, 0, r0, c10, c2, 0 "); |
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84 #if defined(__CPU_ARMV7) |
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85 UTLBIALL; |
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86 ARM_ISBSY; |
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87 #else |
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88 FLUSH_DTLB(,r0); |
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89 #endif |
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90 __JUMP(,lr); |
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91 } |
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92 |
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93 /** Sets NRRR Register*/ |
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94 __NAKED__ void SetNRRR(TUint32) |
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95 { |
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96 asm("mcr p15, 0, r0, c10, c2, 1 "); |
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97 __JUMP(,lr); |
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98 } |
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99 #endif |
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100 |
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101 |
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102 |
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103 #ifdef __CPU_HAS_CACHE_TYPE_REGISTER |
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104 __NAKED__ TUint32 GetCacheType() |
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105 { |
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106 asm("mrc p15, 0, r0, c0, c0, 1 "); |
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107 __JUMP(,lr); |
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108 } |
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109 #endif |
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110 |
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111 |
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112 #ifdef __XSCALE_L2_CACHE__ |
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113 /** Returns L2 Cache Type Register Content */ |
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114 __NAKED__ TUint32 L2CacheTypeReg() |
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115 { |
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116 asm("mrc p15, 1, r0, c0, c0, 1 "); |
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117 __JUMP(,lr); |
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118 } |
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119 #endif // __XSCALE_L2_CACHE__ |
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120 |
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121 #define NOP_8() \ |
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122 asm("nop"); \ |
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123 asm("nop"); \ |
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124 asm("nop"); \ |
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125 asm("nop"); \ |
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126 asm("nop"); \ |
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127 asm("nop"); \ |
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128 asm("nop"); \ |
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129 asm("nop"); \ |
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130 |
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131 #define NOP_64() \ |
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132 NOP_8() \ |
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133 NOP_8() \ |
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134 NOP_8() \ |
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135 NOP_8() \ |
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136 NOP_8() \ |
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137 NOP_8() \ |
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138 NOP_8() \ |
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139 NOP_8() \ |
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140 |
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141 #define NOP_512() \ |
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142 NOP_64() \ |
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143 NOP_64() \ |
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144 NOP_64() \ |
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145 NOP_64() \ |
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146 NOP_64() \ |
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147 NOP_64() \ |
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148 NOP_64() \ |
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149 NOP_64() \ |
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150 |
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151 __NAKED__ void TestCodeFunc() |
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152 { |
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153 asm("testcodestart: "); |
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154 NOP_512(); //512 nops * 4 bytes/nop = 2K (800h) of code |
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155 __JUMP(,lr); //+ 4 bytes |
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156 asm("testcodeend: "); |
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157 } |
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158 |
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159 __NAKED__ TInt TestCodeFuncSize() |
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160 { |
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161 asm("ldr r0, = testcodeend - testcodestart"); //This should return 804h |
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162 __JUMP(,lr); |
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163 } |
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164 |
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165 #endif //#ifdef __KERNEL_MODE__ |
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166 |
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167 // It assumes that aSize and aBase are aligned to 4 bytes. Also, aSize must be > 0. |
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168 __NAKED__ void DataSegmetTestFunct(void* /*aBase*/, TInt /*aSize*/) |
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169 { |
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170 asm("add r1,r1,r0"); // r1 = end address (excluding) |
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171 asm("mov r2, #50"); // Will take 50 cycles |
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172 asm("mvn r12, #1"); // r12 = -2 |
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173 |
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174 asm("next_cycle:"); |
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175 |
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176 asm("mov r3, r0"); // r3 = aBase |
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177 asm("write_loop:"); |
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178 asm("str r12, [r3],#4"); |
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179 |
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180 asm("cmp r3, r1"); |
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181 asm("blo write_loop"); |
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182 |
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183 asm("mov r3, r0"); // r3 = aBase |
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184 asm("read_loop:"); |
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185 asm("ldr r12, [r3],#4"); |
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186 asm("cmp r3, r1"); |
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187 asm("blo read_loop"); |
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188 |
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189 asm("subs r2,r2,#1"); |
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190 asm("bne next_cycle"); |
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191 |
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192 __JUMP(,lr); |
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193 } |