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1 // Copyright (c) 2006-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // e32test\mmu\d_cache.h |
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15 // |
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16 // |
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17 |
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18 #ifndef __D_CACHE_H__ |
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19 #define __D_CACHE_H__ |
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20 |
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21 #include <e32cmn.h> |
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22 #ifndef __KERNEL_MODE__ |
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23 #include <e32std.h> |
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24 #endif |
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25 |
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26 _LIT(KCacheTestDriverName,"d_cache"); |
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27 const TInt KMaxThresholdTypes = 5; // 1.Instruction/Unified, 2.Data, 3.AltD 4.Data_IMB 5.L210/L2XScale |
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28 |
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29 |
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30 const TInt KSingleCacheDescSize = 30;//Desc. of each particular cache. Must be *2 as t_cache converts TDes8 into TDes16. |
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31 const TInt KCacheDescSize = 200;//Desc. of the cache as a whole on the platforms. Must be *2 as t_cache converts TDes8 into TDes16. |
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32 const TInt KMaxCaches = 8; //Max number of caches. In theory, could be more but... |
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33 /**User side channel to Device Driver.*/ |
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34 class RCacheTestDevice : public RBusLogicalChannel |
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35 { |
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36 public: |
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37 enum TControl |
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38 { |
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39 EGetCacheInfo, |
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40 ETestDataChunk, |
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41 ETestCodeChunk, |
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42 ETestWriteBackReadAllocate, |
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43 ETestWriteBackWriteAllocate, |
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44 ETesL2Maintenance, |
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45 EGetThreshold, |
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46 ESetThreshold, |
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47 ETestUseCase |
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48 }; |
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49 |
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50 struct TThresholdInfo |
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51 { |
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52 TInt iCacheType; |
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53 TUint32 iPurge; |
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54 TUint32 iClean; |
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55 TUint32 iFlush; |
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56 }; |
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57 |
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58 //Description of a single cache |
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59 struct TCacheSingle |
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60 { |
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61 TInt8 iLevel; // Cache level (1-8) |
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62 TInt8 iData; // 1 if it is data (or unified) cache, 0 otherwise |
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63 TInt8 iCode; // 1 if this is instruction (or unified) cache, 0 otherwise |
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64 TInt iSize; // In bytes. Should be = iLineLength * iWays * iSets |
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65 TInt iLineSize; // In bytes |
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66 TInt iWays; // Number of sets in cache |
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67 TInt iSets; // Number of ways in cache |
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68 TBuf8<2*KSingleCacheDescSize> iDesc; // Description, eg. L1_Instr_Inner L1_Data L2_Unified L210_Unified_Outer |
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69 }; |
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70 |
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71 struct TCacheInfo |
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72 { |
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73 TBuf8<2*KCacheDescSize> iDesc; // General decription of the platform. E.g. '1176 with L210'. |
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74 TInt iCacheCount; // How many caches are there all together. |
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75 TInt iMaxCacheSize; // All caches considered. In bytes |
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76 TInt iMemoryRemapping; // 1 if memory remapping is ON. |
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77 TInt iOuterCache; // 1 if there is outer cache |
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78 TInt iDmaBufferAlignment; // Maximum size of any data cache line |
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79 TCacheSingle iCache[KMaxCaches];// Info for each separate cache. |
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80 }; |
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81 |
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82 enum TCacheAttr//Specifies cache attributes |
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83 |
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84 { //CacheAttr BC(armv5) TEX:BC(armv6) memory_remapping(armv6K, armv7) |
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85 // Non-cached mapping |
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86 E_FullyBlocking, //00 00 SO/Shared T0 |
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87 E_Buffered_NC, //01 00 Device/Shared T1 |
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88 E_Buffered_C, //02 01 Normal-Uncached T1 |
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89 |
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90 // Inner cache |
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91 E_InnerWT, //05 10 Normal-InnerWT T2 |
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92 E_InnerWBRA, //06 11 Normal-InnerWB-RA T3 |
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93 E_InnerWB, //07 11 Normal-InnerWB-RAWA T3 |
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94 // Outer cache |
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95 E_OuterWT, //50 10 Normal/OuterWT T2 |
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96 E_OuterWBRA, //60 11 Normal/OuterBW-RA T2 |
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97 E_OuterWB, //70 11 Normal/OuterBW-RAWA T2 |
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98 // All cache |
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99 E_InOutWT, //55 10 Normal/FullyWT T2 |
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100 E_InOutWBRA, //66 11 Normal/FullyWB-RA T3 |
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101 E_InOutWB, //77 11 Normal/FullyWB-RAWA T3 |
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102 |
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103 // Memory remapped attributes |
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104 E_StronglyOrder, //-- T0/00 SO T0 |
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105 E_Device, //-- T0/00 Device T1 |
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106 E_Normal_Uncached, //-- T0/01 Normal/Uncached T2 |
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107 E_Normal_Cached, //-- T0/11 Normal/FullyBW T3 |
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108 E_KernelInternal4, //-- ----- --- T4 |
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109 E_PlatformSpecific5, //-- ----- --- T5 |
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110 E_PlatformSpecific6, //-- ----- --- T6 |
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111 E_PlatformSpecific7, //-- ----- --- T7 |
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112 |
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113 // Inner cache |
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114 E_InnerWT_Remapped, //-- -- -- T4/Normal/InnerWT-OuterNC |
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115 E_InnerWBRA_Remapped, //-- -- -- T4/Normal/InnerWBRA-OuterNC |
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116 E_InnerWB_Remapped, //-- -- -- T4/Normal/InnerWB-OuterNC |
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117 // Outer cache |
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118 E_OuterWT_Remapped, //-- -- -- T4/Normal/InnerNC-OuterWT |
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119 E_OuterWBRA_Remapped, //-- -- -- T4/Normal/InnerNC-OuterWBRA |
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120 E_OuterWB_Remapped, //-- -- -- T4/Normal/InnerNC-OuterWBRA |
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121 // All cache |
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122 E_InOutWT_Remapped, //-- -- -- T4/Normal/InnerWT-OuterWT |
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123 E_InOutWBRA_Remapped, //-- -- -- T4/Normal/InnerWBRA-OuterWBRA |
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124 E_InOutWB_Remapped, //-- -- -- T4/Normal/InnerWB-OuterWB |
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125 |
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126 // Kernel heap for data test / rom-image for code test |
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127 E_Default, |
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128 }; |
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129 |
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130 struct TChunkTest |
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131 { |
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132 TChunkTest() {iShared=EFalse; iUseCase=0; iLoops=0;} |
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133 TChunkTest(TInt aUseCase, TInt aSize, TInt aLoops) {iShared=EFalse;iUseCase=aUseCase;iLoops=aLoops;iSize=aSize;} |
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134 |
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135 TInt iSize; //Defines the size of memory (either code or data) to test against. |
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136 TCacheAttr iCacheAttr; //Defines cache attributes of the memory to test. |
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137 TBool iShared; //Defines the shared bit |
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138 TInt iUseCase; //Specifies which test to execute. |
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139 TInt iLoops; //The number of loops to execute. |
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140 |
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141 TUint32 iActualMapAttr; //The actual mapping attributes of the chunk. Will be set by the driver. |
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142 TInt iTime; //The number of kernel ticks. Will be set by the driver. |
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143 }; |
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144 public: |
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145 #ifndef __KERNEL_MODE__ |
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146 TInt Open() |
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147 {return DoCreate(KCacheTestDriverName,TVersion(1,0,0),KNullUnit,NULL,NULL);} |
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148 TInt GetCacheInfo (TCacheInfo& aCaches) |
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149 {return DoControl(EGetCacheInfo, reinterpret_cast<TAny*>(&aCaches));} |
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150 TInt TestDataChunk (TChunkTest& aChunkTest) |
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151 {return DoControl(ETestDataChunk, reinterpret_cast<TAny*>(&aChunkTest));} |
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152 TInt TestCodeChunk (TChunkTest& aChunkTest) |
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153 {return DoControl(ETestCodeChunk, reinterpret_cast<TAny*>(&aChunkTest));} |
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154 TInt TestWriteBackReadAllocate (TChunkTest& aChunkTest) |
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155 {return DoControl(ETestWriteBackReadAllocate, reinterpret_cast<TAny*>(&aChunkTest));} |
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156 TInt TestWriteBackWriteAllocate (TChunkTest& aChunkTest) |
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157 {return DoControl(ETestWriteBackWriteAllocate, reinterpret_cast<TAny*>(&aChunkTest));} |
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158 TInt TestL2Maintenance() |
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159 {return DoControl(ETesL2Maintenance);} |
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160 TInt GetThreshold(TThresholdInfo& aThreshold) |
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161 {return DoControl(EGetThreshold, reinterpret_cast<TAny*>(&aThreshold));} |
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162 TInt SetThreshold(TThresholdInfo& aThreshold) |
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163 {return DoControl(ESetThreshold, reinterpret_cast<TAny*>(&aThreshold));} |
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164 TInt TestUseCase (TChunkTest& aChunkTest) |
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165 {return DoControl(ETestUseCase, reinterpret_cast<TAny*>(&aChunkTest));} |
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166 #endif //__KERNEL_MODE__ |
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167 }; |
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168 #endif //__D_CACHE_H__ |