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1 // Copyright (c) 1999-2009 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // e32test\realtime\d_latncy.cpp |
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15 // |
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16 // |
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17 |
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18 #include "platform.h" |
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19 |
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20 #if defined(__MEIG__) |
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21 #include <cl7211.h> |
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22 #elif defined(__MAWD__) |
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23 #include <windermere.h> |
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24 #elif defined(__MISA__) |
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25 #include <sa1100.h> |
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26 #elif defined(__MCOT__) |
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27 #include <cotulla.h> |
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28 #elif defined(__MI920__) || defined(__NI1136__) |
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29 #include <integratorap.h> |
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30 //#define FREE_RUNNING_MODE // runs the millisecond timer in free running mode |
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31 #elif defined(__IS_OMAP1610__) |
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32 #include <omap_timer.h> |
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33 #include <omap_plat.h> |
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34 #elif defined(__IS_OMAP2420__) || defined(__WAKEUP_3430__) |
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35 #include <omap_hw.h> |
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36 #include <shared_instrtimer.h> |
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37 #elif defined(__EPOC32__) && defined(__CPU_X86) |
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38 #include <x86.h> |
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39 #include <x86pc.h> |
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40 #elif defined(__RVEMUBOARD__) |
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41 #include <rvemuboard.h> |
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42 #elif defined(__NE1_TB__) |
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43 #include <upd35001_timer.h> |
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44 #endif |
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45 |
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46 #ifdef __CPU_ARM |
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47 #include <arm.h> |
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48 #endif |
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49 |
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50 #include <kernel/kern_priv.h> //temporary |
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51 #include "d_latncy.h" |
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52 |
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53 _LIT(KLddName,"Latency"); |
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54 _LIT(KThreadName,"LatencyThreadK"); |
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55 |
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56 #if defined(__MEIG__) |
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57 const TInt KTickPeriodMs=2; |
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58 const TInt KTicksPerMillisecond=512; |
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59 #elif defined(__MAWD__) |
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60 const TInt KTickPeriodMs=1; |
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61 const TInt KTicksPerMillisecond=512; |
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62 #elif defined(__MISA__) || defined(__MCOT__) |
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63 const TInt KTicksPerMillisecond=3686; |
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64 const TInt KOstTicks=3685; // not quite 1ms, so it goes in and out of phase with ms timer |
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65 TUint TriggerTime; |
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66 #elif defined(__MI920__) || defined(__NI1136__) |
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67 const TInt KTickPeriodMs=1; |
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68 #if defined(__MI920__) || defined(__NI1136__) |
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69 #ifdef FREE_RUNNING_MODE |
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70 const TInt KTicksPerMillisecond=1500; |
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71 #else |
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72 const TInt KTicksPerMillisecond=24000; |
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73 #endif |
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74 #endif |
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75 #elif defined(__IS_OMAP1610__) |
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76 const TInt KTickPeriodMs=1; |
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77 TInt KTicksPerMillisecond = TOmapPlat::GetInputClk()/32000; |
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78 #elif defined(__IS_OMAP2420__) || defined(__WAKEUP_3430__) |
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79 const TInt KTickPeriodMs=1; // defined for compatibility but not used (ignored) |
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80 const TInt KTicksPerMillisecond = 12000; // Hard coded (12Mhz) |
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81 #elif defined(__EPOC32__) && defined(__CPU_X86) |
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82 const TInt KTickPeriodMs=1; |
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83 const TInt KTicksPerMillisecond=1193; |
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84 #elif defined(__RVEMUBOARD__) |
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85 const TInt KTickPeriodMs=1; |
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86 const TInt KTicksPerMillisecond=1000; |
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87 #elif defined(__NE1_TB__) |
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88 const TInt KTickPeriodMs=1; |
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89 const TInt KTicksPerMillisecond=66667; |
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90 #endif |
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91 |
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92 #ifdef _DEBUG |
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93 const TInt KFudgeFactor=1; |
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94 #else |
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95 const TInt KFudgeFactor=1; |
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96 #endif |
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97 |
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98 class DDeviceLatency : public DLogicalDevice |
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99 { |
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100 public: |
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101 DDeviceLatency(); |
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102 virtual TInt Install(); |
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103 virtual void GetCaps(TDes8& aDes) const; |
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104 virtual TInt Create(DLogicalChannelBase*& aChannel); |
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105 }; |
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106 |
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107 class DLatencyPowerHandler : public DPowerHandler |
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108 { |
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109 public: // from DPOwerHandler |
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110 void PowerUp(); |
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111 void PowerDown(TPowerState); |
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112 public: |
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113 DLatencyPowerHandler(DLatency* aChannel); |
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114 public: |
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115 DLatency* iChannel; |
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116 }; |
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117 |
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118 |
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119 |
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120 inline TUint DLatency::Ticks() |
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121 { |
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122 #if defined(__MEIG__) |
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123 return KTicksPerMillisecond-(*(volatile TUint*)(KEigerTimer2Data16+KEigerBaseAddress)&0xffff); |
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124 #elif defined(__MAWD__) |
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125 return KTicksPerMillisecond-(*(volatile TUint*)(KWindTimer2Value16+KWindBaseAddress)&0xffff); |
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126 #elif defined(__MISA__) || defined(__MCOT__) |
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127 return *(volatile TUint*)KHwRwOstOscr-iTriggerTime; |
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128 #elif defined(__MI920__) || defined(__NI1136__) |
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129 return KTicksPerMillisecond-(*(volatile TUint*)(KHwCounterTimer2+KHoTimerValue)&0xffff); |
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130 #elif defined(__IS_OMAP1610__) |
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131 return KTicksPerMillisecond - *(volatile TUint*)(KHwBaseOSTimer1Reg+KHoOSTimer_READ_TIM); |
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132 #elif defined(__IS_OMAP2420__) || defined(__WAKEUP_3430__) |
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133 return (*(volatile TUint*)(iTimerInfo.iAddress + KHoGpTimer_TCRR)) - iTimerLoadValue; |
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134 #elif defined(__X86PC__) |
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135 return 1194 - __HwTimer(); |
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136 #elif defined(__RVEMUBOARD__) |
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137 return KTicksPerMillisecond-(*(volatile TUint*)(KHwCounterTimer1+KHoTimerValue)&0xffff); |
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138 #elif defined(__NE1_TB__) |
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139 return NETimer::Timer(0).iTimerCount; // counts up, reset timer + interrupt on match |
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140 #endif |
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141 } |
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142 |
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143 #if !defined(__SMP__) |
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144 #if !defined(__EPOC32__) || !defined(__CPU_X86) |
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145 extern TUint IntStackPtr(); |
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146 #endif |
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147 #endif |
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148 |
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149 DECLARE_STANDARD_LDD() |
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150 { |
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151 return new DDeviceLatency; |
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152 } |
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153 |
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154 DDeviceLatency::DDeviceLatency() |
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155 // |
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156 // Constructor |
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157 // |
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158 { |
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159 //iParseMask=0; |
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160 //iUnitsMask=0; |
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161 iVersion=TVersion(1,0,1); |
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162 } |
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163 |
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164 TInt DDeviceLatency::Install() |
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165 // |
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166 // Install the device driver. |
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167 // |
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168 { |
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169 TInt r=SetName(&KLddName); |
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170 return r; |
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171 } |
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172 |
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173 void DDeviceLatency::GetCaps(TDes8& aDes) const |
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174 // |
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175 // Return the Comm capabilities. |
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176 // |
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177 { |
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178 } |
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179 |
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180 TInt DDeviceLatency::Create(DLogicalChannelBase*& aChannel) |
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181 // |
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182 // Create a channel on the device. |
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183 // |
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184 { |
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185 aChannel=new DLatency; |
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186 return aChannel?KErrNone:KErrNoMemory; |
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187 } |
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188 |
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189 DLatency::DLatency() |
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190 : iMsCallBack(MsCallBack,this), |
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191 iMsDfc(MsDfc,this,NULL,1) |
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192 // |
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193 // Constructor |
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194 // |
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195 { |
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196 #if !defined(__SMP__) |
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197 #if !defined(__EPOC32__) || !defined(__CPU_X86) |
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198 iIntStackTop=(TUint*)IntStackPtr(); |
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199 #endif |
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200 #endif |
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201 #if defined(__MISA__) || defined(__MCOT__) |
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202 iTickIncrement=KOstTicks*KFudgeFactor; |
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203 #endif |
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204 #if defined(__IS_OMAP2420__) || defined(__WAKEUP_3430__) |
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205 iTimerInfo.iAddress = 0; |
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206 #endif |
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207 } |
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208 |
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209 DLatency::~DLatency() |
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210 // |
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211 // Destructor |
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212 // |
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213 { |
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214 iOff = (TUint8)ETrue; |
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215 StopTimer(); |
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216 iMsDfc.Cancel(); |
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217 |
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218 if (iRtDfcQ) |
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219 iRtDfcQ->Destroy(); |
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220 |
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221 if (iPowerHandler) |
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222 { |
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223 iPowerHandler->Remove(); |
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224 delete iPowerHandler; |
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225 } |
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226 |
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227 Kern::SafeClose((DObject*&)iClient, NULL); |
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228 } |
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229 |
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230 TInt DLatency::DoCreate(TInt /*aUnit*/, const TDesC8* /*anInfo*/, const TVersion& aVer) |
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231 // |
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232 // Create the channel from the passed info. |
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233 // |
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234 { |
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235 if (!Kern::QueryVersionSupported(TVersion(1,0,1),aVer)) |
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236 return KErrNotSupported; |
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237 |
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238 // create the power handler |
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239 iPowerHandler = new DLatencyPowerHandler(this); |
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240 if (!iPowerHandler) |
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241 return KErrNoMemory; |
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242 iPowerHandler->Add(); |
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243 |
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244 // Allocate a kernel thread to run the DFC |
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245 TInt r = Kern::DynamicDfcQCreate(iRtDfcQ, KNumPriorities-1,KThreadName); |
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246 |
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247 if (r != KErrNone) |
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248 return r; |
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249 |
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250 iMsDfc.SetDfcQ(iRtDfcQ); |
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251 iClient=&Kern::CurrentThread(); |
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252 iClient->Open(); |
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253 Kern::SetThreadPriority(KNumPriorities-2); |
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254 return KErrNone; |
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255 } |
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256 |
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257 #if defined(__MISA__) |
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258 // For SA1100/SA1110 use a separate timer on a FIQ interrupt (OST match 0) |
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259 TInt DLatency::StartTimer() |
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260 { |
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261 TInt r=Interrupt::Bind(KIntIdOstMatchGeneral,MsCallBack,this); |
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262 if (r==KErrNone) |
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263 { |
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264 TSa1100::ModifyIntLevels(0,KHtIntsOstMatchGeneral); // route new timer interrupt to FIQ |
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265 TSa1100::SetOstMatchEOI(KHwOstMatchGeneral); |
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266 TUint oscr=TSa1100::OstData(); |
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267 iTriggerTime=oscr+KOstTicks*KFudgeFactor; |
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268 TSa1100::SetOstMatch(KHwOstMatchGeneral,iTriggerTime); |
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269 TSa1100::EnableOstInterrupt(KHwOstMatchGeneral); |
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270 Interrupt::Enable(KIntIdOstMatchGeneral); |
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271 } |
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272 return r; |
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273 } |
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274 #elif defined(__MCOT__) |
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275 // For Cotulla use a separate timer on a FIQ interrupt (OST match 0) |
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276 TInt DLatency::StartTimer() |
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277 { |
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278 TInt r=Interrupt::Bind(KIntIdOstMatchGeneral,MsCallBack,this); |
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279 if (r==KErrNone) |
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280 { |
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281 TCotulla::ModifyIntLevels(0,KHtIntsOstMatchGeneral); // route new timer interrupt to FIQ |
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282 TCotulla::SetOstMatchEOI(KHwOstMatchGeneral); |
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283 TUint oscr=TCotulla::OstData(); |
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284 iTriggerTime=oscr+KOstTicks*KFudgeFactor; |
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285 TCotulla::SetOstMatch(iTriggerTime,KHwOstMatchGeneral); |
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286 TCotulla::EnableOstInterrupt(KHwOstMatchGeneral); |
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287 Interrupt::Enable(KIntIdOstMatchGeneral); |
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288 } |
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289 return r; |
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290 } |
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291 #elif defined(__IS_OMAP2420__) || defined(__WAKEUP_3430__) |
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292 TInt DLatency::StartTimer() |
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293 /* |
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294 * For OMAP2420 initialise a new timer to generate an interrupt every 1ms |
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295 */ |
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296 { |
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297 __ASSERT_ALWAYS(!iTimerInfo.iAddress, Kern::Fault("D_Latncy: timer allocated twice.", |
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298 iTimerInfo.iAddress)); |
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299 |
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300 // Get an available Timer from the system |
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301 TInt r = OmapTimerMgr::GetTimer(iGPTimerId, iTimerInfo); |
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302 if (KErrNone != r) |
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303 { |
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304 return r; |
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305 } |
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306 |
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307 // Configure the timer |
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308 r = ConfigureTimer(); |
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309 if (KErrNone != r) |
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310 { |
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311 DisableTimer(); |
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312 return r; |
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313 } |
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314 |
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315 // Bind to timer interrupt |
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316 r = Interrupt::Bind(iTimerInfo.iInterruptId, MsCallBack, this); |
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317 if (KErrNone != r) |
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318 { |
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319 DisableTimer(); |
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320 return r; |
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321 } |
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322 |
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323 // Unmask timer IT in interrupt controller |
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324 r = Interrupt::Enable(iTimerInfo.iInterruptId); |
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325 if (KErrNone != r) |
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326 { |
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327 Interrupt::Unbind(iTimerInfo.iInterruptId); |
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328 DisableTimer(); |
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329 return r; |
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330 } |
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331 |
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332 // Start timer |
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333 TOmap::ModifyRegister32(iTimerInfo.iAddress + KHoGpTimer_TCLR, KClear32, |
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334 KHtGpTimer_TCLR_St); |
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335 |
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336 return KErrNone; |
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337 } |
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338 |
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339 void DLatency::DisableTimer() |
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340 /* |
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341 * Disable the interface and functional clock and mark the timer as available |
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342 */ |
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343 { |
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344 // Stop timer |
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345 TOmap::ModifyRegister32(iTimerInfo.iAddress + KHoGpTimer_TCLR, |
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346 KHtGpTimer_TCLR_St, KClear32); |
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347 |
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348 #if defined(__WAKEUP_3430__) |
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349 // Disable Timer clocks using Timer framework instead of using TPRcm direct calls for 3430 |
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350 TInt r = OmapTimerMgr::DisableClocks(iGPTimerId); |
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351 if (r != KErrNone) |
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352 __ASSERT_ALWAYS(r, Kern::Fault("Timer clocks disable failed", 0)) ; |
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353 #else |
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354 // Disable timer interface clock in PRCM |
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355 TPrcm::InterfaceClkCtrl(iTimerInfo.iPrcmDeviceId, EFalse); |
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356 |
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357 // Disable timer functional clock in PRCM |
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358 TPrcm::FunctionalClkCtrl(iTimerInfo.iPrcmDeviceId, EFalse); |
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359 #endif |
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360 |
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361 // Release the timer |
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362 OmapTimerMgr::ReleaseTimer(iGPTimerId); |
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363 |
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364 iTimerInfo.iAddress = 0; |
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365 } |
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366 |
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367 |
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368 TInt DLatency::ConfigureTimer() |
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369 /* |
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370 * This method will configure a timer to: |
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371 * - run at the system clock (12Mhz) |
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372 * - no prescaler (disable TCLR[PRE]) |
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373 * - autoreload and overflow interrupt enabled (TLDR will contain a |
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374 * value to generate an interrupt every 1000microsec) |
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375 */ |
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376 { |
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377 |
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378 #if defined(__WAKEUP_3430__) |
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379 // Enable Timer clocks using timer framework instead of TPrcm direct calls for 3430 |
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380 TInt r = OmapTimerMgr::EnableClocks(iGPTimerId); |
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381 if (r != KErrNone) |
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382 __ASSERT_ALWAYS(r, Kern::Fault("Timer Clocks enable failed", 0)) ; |
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383 |
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384 // Select the input clock to be system clock |
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385 r = OmapTimerMgr::SetTimerClkSrc(iGPTimerId, ESysClk); |
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386 #else |
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387 // Enable timer interface clock in PRCM |
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388 TPrcm::InterfaceClkCtrl(iTimerInfo.iPrcmDeviceId, ETrue, ETrue); |
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389 // Enable timer functional clock in PRCM |
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390 TPrcm::FunctionalClkCtrl(iTimerInfo.iPrcmDeviceId, ETrue, ETrue); |
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391 |
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392 // Select the input clock to be system clock |
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393 TInt r = OmapTimerMgr::SetTimerClkSrc(iGPTimerId, ESysClk); |
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394 #endif |
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395 |
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396 if (KErrNone != r) |
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397 return r; |
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398 |
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399 // Timer OCP configuration: - software reset |
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400 TOmap::SetRegister32( iTimerInfo.iAddress + KHoGpTimerTIOCP_CFG, |
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401 KHtGpTimer_TIOCP_CFG_SoftReset); |
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402 |
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403 // Wait for reset to be complete |
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404 TUint16 timeOut = 1000; |
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405 while ( !(TOmap::Register32(iTimerInfo.iAddress + KHoGpTimer_TISTAT) & |
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406 KHtGpTimer_TISTAT_ResetComplete) |
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407 && --timeOut); |
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408 |
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409 // Check if the timer has been reset or we hit the timeout |
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410 __ASSERT_ALWAYS((TOmap::Register32(iTimerInfo.iAddress + KHoGpTimer_TISTAT) & |
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411 KHtGpTimer_TISTAT_ResetComplete), Kern::Fault("D_Latncy: failed to reset timer.", |
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412 iGPTimerId)); |
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413 |
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414 // Set PRE to be 0, PTV value is ignored, AutoReload is enabled |
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415 TOmap::SetRegister32(iTimerInfo.iAddress + KHoGpTimer_TCLR, KHtGpTimer_TCLR_AR ); |
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416 |
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417 //PTV argument is 0 because of TCLR[PRE] = 0 (prescaling disabled) |
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418 TInt timerPTV = 0; |
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419 |
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420 // Calculate clock frequence from the ticks per ms |
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421 TInt timerClkSrcFreq = KTicksPerMillisecond * 1000; |
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422 |
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423 iTimerLoadValue = OmapTimerMgr::TimerLoadValue(/*microsecs*/1000, timerClkSrcFreq, timerPTV); |
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424 |
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425 // First, load value in TCRR and TLDR registers |
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426 TOmap::SetRegister32(iTimerInfo.iAddress + KHoGpTimer_TCRR, iTimerLoadValue); |
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427 TOmap::SetRegister32(iTimerInfo.iAddress + KHoGpTimer_TLDR, iTimerLoadValue); |
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428 |
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429 // Enable overflow interrupt |
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430 TOmap::SetRegister32(iTimerInfo.iAddress + KHoGpTimer_TIER, |
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431 KHtGpTimer_TIER_OverFlow); |
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432 |
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433 return KErrNone; |
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434 } |
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435 #else |
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436 TInt DLatency::StartTimer() |
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437 { |
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438 iMsCallBack.OneShot(KTickPeriodMs*KFudgeFactor); |
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439 return KErrNone; |
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440 } |
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441 #endif |
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442 |
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443 #if defined(__MISA__) |
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444 // For SA1100/SA1110 use a separate timer on a FIQ interrupt (OST match 0) |
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445 void DLatency::StopTimer() |
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446 { |
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447 TSa1100::ModifyIntLevels(KHtIntsOstMatchGeneral,0); |
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448 TSa1100::DisableOstInterrupt(KHwOstMatchGeneral); |
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449 Interrupt::Disable(KIntIdOstMatchGeneral); |
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450 Interrupt::Unbind(KIntIdOstMatchGeneral); |
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451 TSa1100::SetOstMatchEOI(KHwOstMatchGeneral); |
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452 } |
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453 #elif defined(__MCOT__) |
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454 // For Cotulla use a separate timer on a FIQ interrupt (OST match 0) |
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455 void DLatency::StopTimer() |
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456 { |
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457 TCotulla::ModifyIntLevels(KHtIntsOstMatchGeneral,0); |
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458 TCotulla::DisableOstInterrupt(KHwOstMatchGeneral); |
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459 Interrupt::Disable(KIntIdOstMatchGeneral); |
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460 Interrupt::Unbind(KIntIdOstMatchGeneral); |
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461 TCotulla::SetOstMatchEOI(KHwOstMatchGeneral); |
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462 } |
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463 #elif defined(__IS_OMAP2420__) || defined(__WAKEUP_3430__) |
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464 void DLatency::StopTimer() |
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465 { |
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466 Interrupt::Disable(iTimerInfo.iInterruptId); |
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467 Interrupt::Unbind(iTimerInfo.iInterruptId); |
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468 DisableTimer(); |
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469 } |
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470 #else |
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471 void DLatency::StopTimer() |
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472 { |
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473 iMsCallBack.Cancel(); |
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474 } |
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475 #endif |
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476 |
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477 TInt DLatency::Request(TInt aFunction, TAny* a1, TAny* a2) |
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478 // |
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479 // Client requests |
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480 // |
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481 { |
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482 // Kern::Printf("DLatency::Request() 0x%x)\n", aFunction); |
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483 TInt r=KErrNone; |
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484 switch (aFunction) |
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485 { |
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486 case RLatency::EControlStart: |
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487 iStarted = (TUint8)ETrue; |
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488 StartTimer(); |
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489 break; |
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490 case RLatency::EControlTicksPerMs: |
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491 r=KTicksPerMillisecond; |
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492 break; |
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493 case RLatency::EControlGetResults: |
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494 iResults.iUserThreadTicks = Ticks(); |
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495 kumemput32(a1, &iResults, sizeof(SLatencyResults)); |
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496 break; |
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497 default: |
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498 r = KErrNotSupported; |
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499 break; |
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500 } |
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501 return(r); |
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502 } |
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503 |
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504 #ifdef __CAPTURE_EXTRAS |
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505 extern void CaptureExtras(SLatencyResults&); |
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506 #endif |
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507 |
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508 #if !defined(__MISA__) && !defined(__MCOT__) |
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509 void DLatency::MsCallBack(TAny* aPtr) |
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510 { |
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511 DLatency* pL = (DLatency*)aPtr; |
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512 #if defined(__IS_OMAP2420__) || defined(__WAKEUP_3430__) |
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513 pL->iResults.iIntTicks = pL->Ticks(); |
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514 TOmap::SetRegister32(pL->iTimerInfo.iAddress + KHoGpTimer_TISR, KHtGpTimer_TISR_OverFlow); |
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515 #else |
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516 pL->iResults.iIntTicks = Ticks(); |
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517 #endif |
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518 #ifdef __CAPTURE_EXTRAS |
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519 CaptureExtras(pL->iResults); |
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520 #endif |
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521 #if defined(__EPOC32__) && defined(__CPU_X86) |
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522 pL->iResults.iIntRetAddr = X86::IrqReturnAddress(); |
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523 #elif defined(__CPU_ARM) && defined(__SMP__) |
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524 pL->iResults.iIntRetAddr = Arm::IrqReturnAddress(); |
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525 #else |
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526 pL->iResults.iIntRetAddr=(pL->iIntStackTop)[-1]; |
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527 #endif |
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528 if (!pL->iOff) |
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529 { |
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530 pL->iMsCallBack.Again(KTickPeriodMs*KFudgeFactor); |
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531 pL->iMsDfc.Add(); |
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532 } |
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533 } |
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534 #endif |
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535 |
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536 void DLatency::MsDfc(TAny* aPtr) |
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537 { |
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538 DLatency* pL = (DLatency*)aPtr; |
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539 pL->iResults.iKernThreadTicks=pL->Ticks(); |
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540 NKern::ThreadRequestSignal(&pL->iClient->iNThread); |
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541 } |
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542 |
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543 DLatencyPowerHandler::DLatencyPowerHandler(DLatency* aChannel) |
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544 : DPowerHandler(KLddName), |
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545 iChannel(aChannel) |
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546 { |
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547 } |
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548 |
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549 void DLatencyPowerHandler::PowerUp() |
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550 { |
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551 iChannel->iOff = (TUint8)EFalse; |
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552 if (iChannel->iStarted) |
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553 iChannel->StartTimer(); |
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554 PowerUpDone(); |
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555 } |
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556 |
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557 void DLatencyPowerHandler::PowerDown(TPowerState) |
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558 { |
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559 iChannel->iOff = (TUint8)ETrue; |
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560 iChannel->StopTimer(); |
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561 PowerDownDone(); |
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562 } |
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563 |
|
564 |
|
565 |