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1 // Copyright (c) 2004-2010 Nokia Corporation and/or its subsidiary(-ies). |
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2 // All rights reserved. |
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3 // This component and the accompanying materials are made available |
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4 // under the terms of the License "Eclipse Public License v1.0" |
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5 // which accompanies this distribution, and is available |
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6 // at the URL "http://www.eclipse.org/legal/epl-v10.html". |
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7 // |
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8 // Initial Contributors: |
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9 // Nokia Corporation - initial contribution. |
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10 // |
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11 // Contributors: |
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12 // |
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13 // Description: |
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14 // bsptemplate/asspvariant/template_assp/dmapsl_v2.cpp |
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15 // Template DMA Platform Specific Layer (PSL). |
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16 // |
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17 // |
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18 |
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19 |
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20 #include <kernel/kern_priv.h> |
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21 #include <template_assp.h> // /assp/template_assp/ |
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22 |
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23 #include <drivers/dma.h> |
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24 #include <drivers/dma_hai.h> |
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25 |
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26 |
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27 // Debug support |
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28 static const char KDmaPanicCat[] = "DMA PSL - " __FILE__; |
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29 |
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30 static const TInt KMaxTransferLen = 0x1FE0; // max transfer length for this DMAC |
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31 static const TInt KMemAlignMask = 7; // memory addresses passed to DMAC must be multiple of 8 |
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32 static const TInt KChannelCount = 16; // we got 16 channels |
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33 static const TInt KDesCount = 160; // Initial DMA descriptor count |
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34 |
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35 |
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36 class TDmaDesc |
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37 // |
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38 // Hardware DMA descriptor |
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39 // |
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40 { |
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41 public: |
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42 enum {KStopBitMask = 1}; |
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43 public: |
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44 TPhysAddr iDescAddr; |
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45 TPhysAddr iSrcAddr; |
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46 TPhysAddr iDestAddr; |
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47 TUint32 iCmd; |
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48 }; |
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49 |
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50 |
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51 ////////////////////////////////////////////////////////////////////////////// |
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52 // Test Support |
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53 ////////////////////////////////////////////////////////////////////////////// |
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54 |
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55 /** |
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56 TO DO: Fill in to provide information to the V1 test harness (t_dma.exe) |
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57 */ |
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58 TDmaTestInfo TestInfo = |
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59 { |
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60 0, |
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61 0, |
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62 0, |
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63 0, |
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64 NULL, |
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65 0, |
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66 NULL, |
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67 0, |
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68 NULL |
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69 }; |
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70 |
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71 |
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72 EXPORT_C const TDmaTestInfo& DmaTestInfo() |
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73 // |
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74 // |
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75 // |
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76 { |
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77 return TestInfo; |
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78 } |
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79 |
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80 /** |
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81 TO DO: Fill in to provide information to the V2 test harness (t_dma2.exe) |
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82 */ |
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83 TDmaV2TestInfo TestInfov2 = |
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84 { |
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85 0, |
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86 0, |
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87 0, |
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88 0, |
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89 {0}, |
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90 0, |
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91 {0}, |
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92 0, |
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93 {0} |
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94 }; |
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95 |
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96 EXPORT_C const TDmaV2TestInfo& DmaTestInfoV2() |
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97 { |
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98 return TestInfov2; |
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99 } |
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100 |
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101 ////////////////////////////////////////////////////////////////////////////// |
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102 // Helper Functions |
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103 ////////////////////////////////////////////////////////////////////////////// |
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104 |
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105 inline TBool IsHwDesAligned(TAny* aDes) |
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106 // |
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107 // Checks whether given hardware descriptor is 16-bytes aligned. |
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108 // |
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109 { |
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110 return ((TLinAddr)aDes & 0xF) == 0; |
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111 } |
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112 |
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113 |
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114 static TUint32 DmaCmdReg(TUint aCount, TUint aFlags, TUint32 aSrcPslInfo, TUint32 aDstPslInfo) |
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115 // |
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116 // Returns value to set in DMA command register or in descriptor command field. |
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117 // |
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118 { |
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119 // TO DO: Construct CMD word from input values. |
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120 // The return value should reflect the actual control word. |
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121 return (aCount | aFlags | aSrcPslInfo | aDstPslInfo); |
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122 } |
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123 |
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124 |
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125 ////////////////////////////////////////////////////////////////////////////// |
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126 // Derived Channel (Scatter/Gather) |
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127 ////////////////////////////////////////////////////////////////////////////// |
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128 |
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129 class TTemplateSgChannel : public TDmaSgChannel |
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130 { |
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131 public: |
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132 TDmaDesc* iTmpDes; |
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133 TPhysAddr iTmpDesPhysAddr; |
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134 }; |
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135 |
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136 |
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137 ////////////////////////////////////////////////////////////////////////////// |
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138 // Derived Controller Class |
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139 ////////////////////////////////////////////////////////////////////////////// |
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140 |
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141 class TTemplateDmac : public TDmac |
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142 { |
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143 public: |
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144 TTemplateDmac(); |
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145 TInt Create(); |
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146 private: |
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147 // from TDmac (PIL pure virtual) |
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148 virtual void StopTransfer(const TDmaChannel& aChannel); |
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149 virtual TBool IsIdle(const TDmaChannel& aChannel); |
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150 virtual TUint MaxTransferLength(TDmaChannel& aChannel, TUint aSrcFlags, |
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151 TUint aDstFlags, TUint32 aPslInfo); |
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152 virtual TUint AddressAlignMask(TDmaChannel& aChannel, TUint aSrcFlags, |
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153 TUint aDstFlags, TUint32 aPslInfo); |
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154 // from TDmac (PIL virtual) |
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155 virtual void Transfer(const TDmaChannel& aChannel, const SDmaDesHdr& aHdr); |
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156 virtual TInt InitHwDes(const SDmaDesHdr& aHdr, const TDmaTransferArgs& aTransferArgs); |
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157 virtual void ChainHwDes(const SDmaDesHdr& aHdr, const SDmaDesHdr& aNextHdr); |
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158 virtual void AppendHwDes(const TDmaChannel& aChannel, const SDmaDesHdr& aLastHdr, |
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159 const SDmaDesHdr& aNewHdr); |
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160 virtual void UnlinkHwDes(const TDmaChannel& aChannel, SDmaDesHdr& aHdr); |
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161 // other |
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162 static void Isr(TAny* aThis); |
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163 inline TDmaDesc* HdrToHwDes(const SDmaDesHdr& aHdr); |
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164 private: |
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165 static const SCreateInfo KInfo; |
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166 public: |
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167 TTemplateSgChannel iChannels[KChannelCount]; |
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168 }; |
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169 |
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170 |
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171 static TTemplateDmac Controller; |
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172 |
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173 |
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174 const TDmac::SCreateInfo TTemplateDmac::KInfo = |
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175 { |
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176 ETrue, // iCapsHwDes |
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177 KDesCount, // iDesCount |
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178 sizeof(TDmaDesc), // iDesSize |
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179 EMapAttrSupRw | EMapAttrFullyBlocking // iDesChunkAttribs |
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180 }; |
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181 |
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182 |
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183 TTemplateDmac::TTemplateDmac() |
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184 // |
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185 // Constructor. |
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186 // |
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187 : TDmac(KInfo) |
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188 {} |
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189 |
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190 |
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191 TInt TTemplateDmac::Create() |
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192 // |
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193 // Second phase construction. |
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194 // |
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195 { |
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196 TInt r = TDmac::Create(KInfo); // Base class Create() |
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197 if (r == KErrNone) |
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198 { |
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199 __DMA_ASSERTA(ReserveSetOfDes(KChannelCount) == KErrNone); |
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200 for (TInt i=0; i < KChannelCount; ++i) |
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201 { |
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202 TDmaDesc* pD = HdrToHwDes(*iFreeHdr); |
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203 iChannels[i].iTmpDes = pD; |
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204 iChannels[i].iTmpDesPhysAddr = HwDesLinToPhys(pD); |
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205 iFreeHdr = iFreeHdr->iNext; |
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206 } |
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207 r = Interrupt::Bind(EAsspIntIdDma, Isr, this); |
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208 if (r == KErrNone) |
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209 { |
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210 // TO DO: Map DMA clients (requests) to DMA channels here. |
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211 |
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212 r = Interrupt::Enable(EAsspIntIdDma); |
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213 } |
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214 } |
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215 return r; |
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216 } |
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217 |
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218 |
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219 void TTemplateDmac::Transfer(const TDmaChannel& aChannel, const SDmaDesHdr& aHdr) |
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220 // |
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221 // Initiates a (previously constructed) request on a specific channel. |
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222 // |
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223 { |
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224 const TUint8 i = static_cast<TUint8>(aChannel.PslId()); |
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225 TDmaDesc* pD = HdrToHwDes(aHdr); |
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226 |
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227 __KTRACE_OPT(KDMA, Kern::Printf(">TTemplateDmac::Transfer channel=%d des=0x%08X", i, pD)); |
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228 |
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229 // TO DO (for instance): Load the first descriptor address into the DMAC and start it |
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230 // by setting the RUN bit. |
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231 (void) *pD, (void) i; |
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232 |
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233 } |
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234 |
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235 |
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236 void TTemplateDmac::StopTransfer(const TDmaChannel& aChannel) |
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237 // |
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238 // Stops a running channel. |
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239 // |
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240 { |
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241 const TUint8 i = static_cast<TUint8>(aChannel.PslId()); |
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242 |
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243 __KTRACE_OPT(KDMA, Kern::Printf(">TTemplateDmac::StopTransfer channel=%d", i)); |
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244 |
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245 // TO DO (for instance): Clear the RUN bit of the channel. |
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246 (void) i; |
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247 |
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248 } |
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249 |
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250 |
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251 TBool TTemplateDmac::IsIdle(const TDmaChannel& aChannel) |
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252 // |
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253 // Returns the state of a given channel. |
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254 // |
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255 { |
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256 const TUint8 i = static_cast<TUint8>(aChannel.PslId()); |
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257 |
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258 __KTRACE_OPT(KDMA, Kern::Printf(">TTemplateDmac::IsIdle channel=%d", i)); |
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259 |
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260 // TO DO (for instance): Return the state of the RUN bit of the channel. |
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261 // The return value should reflect the actual state. |
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262 (void) i; |
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263 |
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264 return ETrue; |
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265 } |
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266 |
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267 |
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268 TUint TTemplateDmac::MaxTransferLength(TDmaChannel& /*aChannel*/, TUint /*aSrcFlags*/, |
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269 TUint /*aDstFlags*/, TUint32 /*aPslInfo*/) |
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270 // |
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271 // Returns the maximum transfer length in bytes for a given transfer. |
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272 // |
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273 { |
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274 // TO DO: Determine the proper return value, based on the arguments. |
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275 |
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276 // For instance: |
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277 return KMaxTransferLen; |
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278 } |
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279 |
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280 |
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281 TUint TTemplateDmac::AddressAlignMask(TDmaChannel& aChannel, TUint /*aSrcFlags*/, |
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282 TUint /*aDstFlags*/, TUint32 /*aPslInfo*/) |
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283 // |
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284 // Returns the memory buffer alignment restrictions mask for a given transfer. |
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285 // |
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286 { |
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287 // TO DO: Determine the proper return value, based on the arguments. |
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288 |
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289 // For instance: |
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290 return KMemAlignMask; |
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291 } |
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292 |
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293 |
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294 TInt TTemplateDmac::InitHwDes(const SDmaDesHdr& aHdr, const TDmaTransferArgs& aTransferArgs) |
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295 // |
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296 // Sets up (from a passed in request) the descriptor with that fragment's |
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297 // source and destination address, the fragment size, and the (driver/DMA |
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298 // controller) specific transfer parameters (mem/peripheral, burst size, |
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299 // transfer width). |
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300 // |
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301 { |
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302 TDmaDesc* pD = HdrToHwDes(aHdr); |
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303 |
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304 __KTRACE_OPT(KDMA, Kern::Printf("TTemplateDmac::InitHwDes 0x%08X", pD)); |
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305 |
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306 // Unaligned descriptor? Bug in generic layer! |
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307 __DMA_ASSERTD(IsHwDesAligned(pD)); |
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308 |
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309 const TDmaTransferConfig& src = aTransferArgs.iSrcConfig; |
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310 const TDmaTransferConfig& dst = aTransferArgs.iDstConfig; |
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311 pD->iSrcAddr = (src.iFlags & KDmaPhysAddr) ? src.iAddr : Epoc::LinearToPhysical(src.iAddr); |
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312 __DMA_ASSERTD(pD->iSrcAddr != KPhysAddrInvalid); |
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313 pD->iDestAddr = (dst.iFlags & KDmaPhysAddr) ? dst.iAddr : Epoc::LinearToPhysical(dst.iAddr); |
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314 __DMA_ASSERTD(pD->iDestAddr != KPhysAddrInvalid); |
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315 pD->iCmd = DmaCmdReg(aTransferArgs.iTransferCount, aTransferArgs.iFlags, |
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316 src.iPslTargetInfo, dst.iPslTargetInfo); |
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317 pD->iDescAddr = TDmaDesc::KStopBitMask; |
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318 |
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319 return KErrNone; |
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320 } |
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321 |
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322 |
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323 void TTemplateDmac::ChainHwDes(const SDmaDesHdr& aHdr, const SDmaDesHdr& aNextHdr) |
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324 // |
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325 // Chains hardware descriptors together by setting the next pointer of the original descriptor |
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326 // to the physical address of the descriptor to be chained. |
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327 // |
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328 { |
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329 TDmaDesc* pD = HdrToHwDes(aHdr); |
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330 TDmaDesc* pN = HdrToHwDes(aNextHdr); |
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331 |
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332 __KTRACE_OPT(KDMA, Kern::Printf("TTemplateDmac::ChainHwDes des=0x%08X next des=0x%08X", pD, pN)); |
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333 |
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334 // Unaligned descriptor? Bug in generic layer! |
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335 __DMA_ASSERTD(IsHwDesAligned(pD) && IsHwDesAligned(pN)); |
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336 |
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337 // TO DO: Modify pD->iCmd so that no end-of-transfer interrupt gets raised any longer. |
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338 |
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339 pD->iDescAddr = HwDesLinToPhys(pN); |
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340 } |
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341 |
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342 |
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343 void TTemplateDmac::AppendHwDes(const TDmaChannel& aChannel, const SDmaDesHdr& aLastHdr, |
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344 const SDmaDesHdr& aNewHdr) |
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345 // |
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346 // Appends a descriptor to the chain while the channel is running. |
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347 // |
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348 { |
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349 const TUint8 i = static_cast<TUint8>(aChannel.PslId()); |
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350 |
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351 TDmaDesc* pL = HdrToHwDes(aLastHdr); |
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352 TDmaDesc* pN = HdrToHwDes(aNewHdr); |
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353 |
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354 __KTRACE_OPT(KDMA, Kern::Printf(">TTemplateDmac::AppendHwDes channel=%d last des=0x%08X new des=0x%08X", |
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355 i, pL, pN)); |
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356 // Unaligned descriptor? Bug in generic layer! |
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357 __DMA_ASSERTD(IsHwDesAligned(pL) && IsHwDesAligned(pN)); |
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358 |
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359 TPhysAddr newPhys = HwDesLinToPhys(pN); |
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360 |
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361 const TInt irq = NKern::DisableAllInterrupts(); |
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362 StopTransfer(aChannel); |
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363 |
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364 pL->iDescAddr = newPhys; |
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365 const TTemplateSgChannel& channel = static_cast<const TTemplateSgChannel&>(aChannel); |
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366 TDmaDesc* pD = channel.iTmpDes; |
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367 |
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368 // TO DO: Implement the appropriate algorithm for appending a descriptor here. |
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369 (void) *pD, (void) i; |
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370 |
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371 NKern::RestoreInterrupts(irq); |
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372 |
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373 __KTRACE_OPT(KDMA, Kern::Printf("<TTemplateDmac::AppendHwDes")); |
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374 } |
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375 |
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376 |
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377 void TTemplateDmac::UnlinkHwDes(const TDmaChannel& /*aChannel*/, SDmaDesHdr& aHdr) |
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378 // |
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379 // Unlink the last item in the h/w descriptor chain from a subsequent chain that it was |
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380 // possibly linked to. |
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381 // |
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382 { |
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383 __KTRACE_OPT(KDMA, Kern::Printf(">TTemplateDmac::UnlinkHwDes")); |
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384 TDmaDesc* pD = HdrToHwDes(aHdr); |
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385 pD->iDescAddr = TDmaDesc::KStopBitMask; |
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386 |
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387 // TO DO: Modify pD->iCmd so that an end-of-transfer interrupt will get raised. |
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388 |
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389 } |
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390 |
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391 |
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392 void TTemplateDmac::Isr(TAny* aThis) |
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393 // |
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394 // This ISR reads the interrupt identification and calls back into the base class |
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395 // interrupt service handler with the channel identifier and an indication whether the |
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396 // transfer completed correctly or with an error. |
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397 // |
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398 { |
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399 TTemplateDmac& me = *static_cast<TTemplateDmac*>(aThis); |
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400 |
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401 // TO DO: Implement the behaviour described above, call HandleIsr(). |
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402 |
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403 HandleIsr(me.iChannels[5], EDmaCallbackRequestCompletion, ETrue); // Example |
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404 |
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405 } |
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406 |
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407 |
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408 inline TDmaDesc* TTemplateDmac::HdrToHwDes(const SDmaDesHdr& aHdr) |
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409 // |
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410 // Changes return type of base class call. |
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411 // |
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412 { |
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413 return static_cast<TDmaDesc*>(TDmac::HdrToHwDes(aHdr)); |
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414 } |
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415 |
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416 |
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417 ////////////////////////////////////////////////////////////////////////////// |
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418 // Channel Opening/Closing (Channel Allocator) |
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419 ////////////////////////////////////////////////////////////////////////////// |
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420 |
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421 TDmaChannel* DmaChannelMgr::Open(TUint32 aOpenId, TBool /*aDynChannel*/, TUint /*aPriority*/) |
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422 // |
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423 // |
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424 // |
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425 { |
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426 __KTRACE_OPT(KDMA, Kern::Printf(">DmaChannelMgr::Open aOpenId=%d", aOpenId)); |
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427 |
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428 __DMA_ASSERTA(aOpenId < static_cast<TUint32>(KChannelCount)); |
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429 |
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430 TDmaChannel* pC = Controller.iChannels + aOpenId; |
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431 if (pC->IsOpened()) |
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432 { |
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433 pC = NULL; |
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434 } |
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435 else |
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436 { |
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437 pC->iController = &Controller; |
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438 pC->iPslId = aOpenId; |
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439 } |
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440 |
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441 return pC; |
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442 } |
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443 |
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444 |
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445 void DmaChannelMgr::Close(TDmaChannel* /*aChannel*/) |
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446 // |
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447 // |
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448 // |
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449 { |
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450 // NOP |
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451 } |
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452 |
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453 |
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454 TInt DmaChannelMgr::StaticExtension(TInt /*aCmd*/, TAny* /*aArg*/) |
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455 // |
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456 // |
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457 // |
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458 { |
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459 return KErrNotSupported; |
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460 } |
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461 |
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462 |
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463 ////////////////////////////////////////////////////////////////////////////// |
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464 // DLL Exported Function |
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465 ////////////////////////////////////////////////////////////////////////////// |
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466 |
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467 DECLARE_STANDARD_EXTENSION() |
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468 // |
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469 // Creates and initializes a new DMA controller object on the kernel heap. |
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470 // |
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471 { |
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472 __KTRACE_OPT2(KBOOT, KDMA, Kern::Printf("Starting DMA Extension")); |
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473 |
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474 const TInt r = DmaChannelMgr::Initialise(); |
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475 if (r != KErrNone) |
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476 { |
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477 return r; |
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478 } |
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479 return Controller.Create(); |
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480 } |