--- a/kernel/eka/memmodel/epoc/multiple/arm/xmmu.cpp	Thu Aug 19 11:14:22 2010 +0300
+++ b/kernel/eka/memmodel/epoc/multiple/arm/xmmu.cpp	Tue Aug 31 16:34:26 2010 +0300
@@ -715,7 +715,8 @@
 			// we have an L1 data cache...
 			TUint32 csir = InternalCache::SizeIdRegister(0,0);
 			TUint sets = ((csir>>13)&0x7fff)+1;
-			TUint ways = ((csir>>3)&0x3ff)+1;
+			TUint ways = ((csir>>3)&0x3ff);
+			ways+=1;
 			TUint lineSizeShift = (csir&7)+4;
 			// assume L1 data cache is VIPT and alias checks broken and so we need data cache colouring...
 			dColourCount = (sets<<lineSizeShift)>>KPageShift;
@@ -729,7 +730,8 @@
 			// we have a separate L1 instruction cache...
 			TUint32 csir = InternalCache::SizeIdRegister(1,0);
 			TUint sets = ((csir>>13)&0x7fff)+1;
-			TUint ways = ((csir>>3)&0x3ff)+1;
+			TUint ways = ((csir>>3)&0x3ff);
+			ways+=1;
 			TUint lineSizeShift = (csir&7)+4;
 			iColourCount = (sets<<lineSizeShift)>>KPageShift;
 			__KTRACE_OPT2(KBOOT,KMMU,Kern::Printf("L1ICache = 0x%x,0x%x,%d colourCount=%d",sets,ways,lineSizeShift,(sets<<lineSizeShift)>>KPageShift));