diff -r 36bfc973b146 -r 329ab0095843 bsptemplate/asspandvariant/template_assp/dmapsl.cpp --- a/bsptemplate/asspandvariant/template_assp/dmapsl.cpp Thu Jan 07 13:38:45 2010 +0200 +++ b/bsptemplate/asspandvariant/template_assp/dmapsl.cpp Mon Jan 18 21:31:10 2010 +0200 @@ -11,23 +11,26 @@ // Contributors: // // Description: -// template\template_assp\dmapsl.cpp +// bsptemplate/asspvariant/template_assp/dmapsl.cpp // Template DMA Platform Specific Layer (PSL). -// +// // #include #include // /assp/template_assp/ + #include +#include + // Debug support -static const char KDmaPanicCat[] = "DMA PSL"; +static const char KDmaPanicCat[] = "DMA PSL - " __FILE__; -static const TInt KMaxTransferLen = 0x1FE0; // max transfer length for this DMAC -static const TInt KMemAlignMask = 7; // memory addresses passed to DMAC must be multiple of 8 -static const TInt KChannelCount = 16; // we got 16 channels -static const TInt KDesCount = 1024; // DMA descriptor count +static const TInt KMaxTransferLen = 0x1FE0; // max transfer length for this DMAC +static const TInt KMemAlignMask = 7; // memory addresses passed to DMAC must be multiple of 8 +static const TInt KChannelCount = 16; // we got 16 channels +static const TInt KDesCount = 160; // Initial DMA descriptor count class TDmaDesc @@ -49,6 +52,9 @@ // Test Support ////////////////////////////////////////////////////////////////////////////// +/** +TO DO: Fill in to provide information to the V1 test harness (t_dma.exe) +*/ TDmaTestInfo TestInfo = { 0, @@ -71,6 +77,26 @@ return TestInfo; } +/** +TO DO: Fill in to provide information to the V2 test harness (t_dma2.exe) +*/ +TDmaV2TestInfo TestInfov2 = + { + 0, + 0, + 0, + 0, + {0}, + 0, + {0}, + 0, + {0} + }; + +EXPORT_C const TDmaV2TestInfo& DmaTestInfoV2() + { + return TestInfov2; + } ////////////////////////////////////////////////////////////////////////////// // Helper Functions @@ -85,14 +111,14 @@ } -static TUint32 DcmdReg(TInt aCount, TUint aFlags, TUint32 aPslInfo) +static TUint32 DmaCmdReg(TUint aCount, TUint aFlags, TUint32 aSrcPslInfo, TUint32 aDstPslInfo) // // Returns value to set in DMA command register or in descriptor command field. // { // TO DO: Construct CMD word from input values. // The return value should reflect the actual control word. - return (aCount | aFlags | aPslInfo); + return (aCount | aFlags | aSrcPslInfo | aDstPslInfo); } @@ -119,14 +145,15 @@ TInt Create(); private: // from TDmac (PIL pure virtual) - virtual void Transfer(const TDmaChannel& aChannel, const SDmaDesHdr& aHdr); virtual void StopTransfer(const TDmaChannel& aChannel); virtual TBool IsIdle(const TDmaChannel& aChannel); - virtual TInt MaxTransferSize(TDmaChannel& aChannel, TUint aFlags, TUint32 aPslInfo); - virtual TUint MemAlignMask(TDmaChannel& aChannel, TUint aFlags, TUint32 aPslInfo); + virtual TUint MaxTransferLength(TDmaChannel& aChannel, TUint aSrcFlags, + TUint aDstFlags, TUint32 aPslInfo); + virtual TUint AddressAlignMask(TDmaChannel& aChannel, TUint aSrcFlags, + TUint aDstFlags, TUint32 aPslInfo); // from TDmac (PIL virtual) - virtual void InitHwDes(const SDmaDesHdr& aHdr, TUint32 aSrc, TUint32 aDest, TInt aCount, - TUint aFlags, TUint32 aPslInfo, TUint32 aCookie); + virtual void Transfer(const TDmaChannel& aChannel, const SDmaDesHdr& aHdr); + virtual TInt InitHwDes(const SDmaDesHdr& aHdr, const TDmaTransferArgs& aTransferArgs); virtual void ChainHwDes(const SDmaDesHdr& aHdr, const SDmaDesHdr& aNextHdr); virtual void AppendHwDes(const TDmaChannel& aChannel, const SDmaDesHdr& aLastHdr, const SDmaDesHdr& aNewHdr); @@ -140,15 +167,16 @@ TTemplateSgChannel iChannels[KChannelCount]; }; + static TTemplateDmac Controller; + const TDmac::SCreateInfo TTemplateDmac::KInfo = { - KChannelCount, - KDesCount, - TDmac::KCapsBitHwDes, - sizeof(TDmaDesc), - EMapAttrSupRw | EMapAttrFullyBlocking + ETrue, // iCapsHwDes + KDesCount, // iDesCount + sizeof(TDmaDesc), // iDesSize + EMapAttrSupRw | EMapAttrFullyBlocking // iDesChunkAttribs }; @@ -173,7 +201,7 @@ { TDmaDesc* pD = HdrToHwDes(*iFreeHdr); iChannels[i].iTmpDes = pD; - iChannels[i].iTmpDesPhysAddr = DesLinToPhys(pD); + iChannels[i].iTmpDesPhysAddr = HwDesLinToPhys(pD); iFreeHdr = iFreeHdr->iNext; } r = Interrupt::Bind(EAsspIntIdDma, Isr, this); @@ -237,9 +265,10 @@ } -TInt TTemplateDmac::MaxTransferSize(TDmaChannel& /*aChannel*/, TUint /*aFlags*/, TUint32 /*aPslInfo*/) +TUint TTemplateDmac::MaxTransferLength(TDmaChannel& /*aChannel*/, TUint /*aSrcFlags*/, + TUint /*aDstFlags*/, TUint32 /*aPslInfo*/) // -// Returns the maximum transfer size for a given transfer. +// Returns the maximum transfer length in bytes for a given transfer. // { // TO DO: Determine the proper return value, based on the arguments. @@ -249,7 +278,8 @@ } -TUint TTemplateDmac::MemAlignMask(TDmaChannel& /*aChannel*/, TUint /*aFlags*/, TUint32 /*aPslInfo*/) +TUint TTemplateDmac::AddressAlignMask(TDmaChannel& aChannel, TUint /*aSrcFlags*/, + TUint /*aDstFlags*/, TUint32 /*aPslInfo*/) // // Returns the memory buffer alignment restrictions mask for a given transfer. // @@ -261,12 +291,12 @@ } -void TTemplateDmac::InitHwDes(const SDmaDesHdr& aHdr, TUint32 aSrc, TUint32 aDest, TInt aCount, - TUint aFlags, TUint32 aPslInfo, TUint32 /*aCookie*/) +TInt TTemplateDmac::InitHwDes(const SDmaDesHdr& aHdr, const TDmaTransferArgs& aTransferArgs) // -// Sets up (from a passed in request) the descriptor with that fragment's source and destination address, -// the fragment size, and the (driver/DMA controller) specific transfer parameters (mem/peripheral, -// burst size, transfer width). +// Sets up (from a passed in request) the descriptor with that fragment's +// source and destination address, the fragment size, and the (driver/DMA +// controller) specific transfer parameters (mem/peripheral, burst size, +// transfer width). // { TDmaDesc* pD = HdrToHwDes(aHdr); @@ -276,10 +306,15 @@ // Unaligned descriptor? Bug in generic layer! __DMA_ASSERTD(IsHwDesAligned(pD)); - pD->iSrcAddr = (aFlags & KDmaPhysAddrSrc) ? aSrc : Epoc::LinearToPhysical(aSrc); - pD->iDestAddr = (aFlags & KDmaPhysAddrDest) ? aDest : Epoc::LinearToPhysical(aDest); - pD->iCmd = DcmdReg(aCount, aFlags, aPslInfo); + const TDmaTransferConfig& src = aTransferArgs.iSrcConfig; + const TDmaTransferConfig& dst = aTransferArgs.iDstConfig; + pD->iSrcAddr = (src.iFlags & KDmaPhysAddr) ? src.iAddr : Epoc::LinearToPhysical(src.iAddr); + pD->iDestAddr = (dst.iFlags & KDmaPhysAddr) ? dst.iAddr : Epoc::LinearToPhysical(dst.iAddr); + pD->iCmd = DmaCmdReg(aTransferArgs.iTransferCount, aTransferArgs.iFlags, + src.iPslTargetInfo, dst.iPslTargetInfo); pD->iDescAddr = TDmaDesc::KStopBitMask; + + return KErrNone; } @@ -299,7 +334,7 @@ // TO DO: Modify pD->iCmd so that no end-of-transfer interrupt gets raised any longer. - pD->iDescAddr = DesLinToPhys(pN); + pD->iDescAddr = HwDesLinToPhys(pN); } @@ -319,7 +354,7 @@ // Unaligned descriptor? Bug in generic layer! __DMA_ASSERTD(IsHwDesAligned(pL) && IsHwDesAligned(pN)); - TPhysAddr newPhys = DesLinToPhys(pN); + TPhysAddr newPhys = HwDesLinToPhys(pN); const TInt irq = NKern::DisableAllInterrupts(); StopTransfer(aChannel); @@ -363,7 +398,7 @@ // TO DO: Implement the behaviour described above, call HandleIsr(). - HandleIsr(me.iChannels[5], 0); // Example + HandleIsr(me.iChannels[5], EDmaCallbackRequestCompletion, ETrue); // Example } @@ -381,7 +416,7 @@ // Channel Opening/Closing (Channel Allocator) ////////////////////////////////////////////////////////////////////////////// -TDmaChannel* DmaChannelMgr::Open(TUint32 aOpenId) +TDmaChannel* DmaChannelMgr::Open(TUint32 aOpenId, TBool /*aDynChannel*/, TUint /*aPriority*/) // // // @@ -392,7 +427,9 @@ TDmaChannel* pC = Controller.iChannels + aOpenId; if (pC->IsOpened()) + { pC = NULL; + } else { pC->iController = &Controller; @@ -403,7 +440,7 @@ } -void DmaChannelMgr::Close(TDmaChannel* /* aChannel */) +void DmaChannelMgr::Close(TDmaChannel* /*aChannel*/) // // // @@ -412,7 +449,7 @@ } -TInt DmaChannelMgr::StaticExtension(TInt /* aCmd */, TAny* /* aArg */) +TInt DmaChannelMgr::StaticExtension(TInt /*aCmd*/, TAny* /*aArg*/) // // // @@ -432,5 +469,10 @@ { __KTRACE_OPT2(KBOOT, KDMA, Kern::Printf("Starting DMA Extension")); + const TInt r = DmaChannelMgr::Initialise(); + if (r != KErrNone) + { + return r; + } return Controller.Create(); }