
diff -r 000000000000 -r a41df078684a bsptemplate/asspandvariant/template_assp/bmarm/i2s.def
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/bsptemplate/asspandvariant/template_assp/bmarm/i2s.def	Mon Oct 19 15:55:17 2009 +0100
@@ -0,0 +1,34 @@
+EXPORTS
+	WriteTransmitRegister__3I2siQ23I2s14TI2sFramePhasei @ 1 NONAME R3UNUSED ; I2s::WriteTransmitRegister(int, I2s::TI2sFramePhase, int)
+	DisableDMA__3I2sii @ 2 NONAME R3UNUSED ; I2s::DisableDMA(int, int)
+	DisableFIFOInterrupts__3I2siQ23I2s14TI2sFramePhasei @ 3 NONAME R3UNUSED ; I2s::DisableFIFOInterrupts(int, I2s::TI2sFramePhase, int)
+	DisableFIFO__3I2siQ23I2s14TI2sFramePhasei @ 4 NONAME R3UNUSED ; I2s::DisableFIFO(int, I2s::TI2sFramePhase, int)
+	DisableRegisterInterrupts__3I2siQ23I2s14TI2sFramePhasei @ 5 NONAME R3UNUSED ; I2s::DisableRegisterInterrupts(int, I2s::TI2sFramePhase, int)
+	EnableDMA__3I2sii @ 6 NONAME R3UNUSED ; I2s::EnableDMA(int, int)
+	EnableFIFOInterrupts__3I2siQ23I2s14TI2sFramePhasei @ 7 NONAME R3UNUSED ; I2s::EnableFIFOInterrupts(int, I2s::TI2sFramePhase, int)
+	EnableFIFO__3I2siQ23I2s14TI2sFramePhasei @ 8 NONAME R3UNUSED ; I2s::EnableFIFO(int, I2s::TI2sFramePhase, int)
+	EnableRegisterInterrupts__3I2siQ23I2s14TI2sFramePhasei @ 9 NONAME R3UNUSED ; I2s::EnableRegisterInterrupts(int, I2s::TI2sFramePhase, int)
+	GetDelayCycles__3I2siQ23I2s14TI2sFramePhaseRi @ 10 NONAME R3UNUSED ; I2s::GetDelayCycles(int, I2s::TI2sFramePhase, int &)
+	GetFrameFormat__3I2siRiT2 @ 11 NONAME R3UNUSED ; I2s::GetFrameFormat(int, int &, int &)
+	GetInterfaceConfiguration__3I2siR5TDes8 @ 12 NONAME R3UNUSED ; I2s::GetInterfaceConfiguration(int, TDes8 &)
+	GetSampleLength__3I2siQ23I2s14TI2sFramePhaseRi @ 13 NONAME R3UNUSED ; I2s::GetSampleLength(int, I2s::TI2sFramePhase, int &)
+	GetSamplingRate__3I2siRi @ 14 NONAME R3UNUSED ; I2s::GetSamplingRate(int, int &)
+	IsDMAEnabled__3I2siRi @ 15 NONAME R3UNUSED ; I2s::IsDMAEnabled(int, int &)
+	IsFIFOEnabled__3I2siQ23I2s14TI2sFramePhaseRi @ 16 NONAME R3UNUSED ; I2s::IsFIFOEnabled(int, I2s::TI2sFramePhase, int &)
+	IsFIFOInterruptEnabled__3I2siQ23I2s14TI2sFramePhaseRi @ 17 NONAME R3UNUSED ; I2s::IsFIFOInterruptEnabled(int, I2s::TI2sFramePhase, int &)
+	IsRegisterInterruptEnabled__3I2siQ23I2s14TI2sFramePhaseRi @ 18 NONAME R3UNUSED ; I2s::IsRegisterInterruptEnabled(int, I2s::TI2sFramePhase, int &)
+	IsStarted__3I2siQ23I2s13TI2sDirectionRi @ 19 NONAME R3UNUSED ; I2s::IsStarted(int, I2s::TI2sDirection, int &)
+	ReadFIFOLevel__3I2siQ23I2s14TI2sFramePhaseQ23I2s13TI2sDirectionRi @ 20 NONAME ; I2s::ReadFIFOLevel(int, I2s::TI2sFramePhase, I2s::TI2sDirection, int &)
+	ReadFIFOModeStatus__3I2siQ23I2s14TI2sFramePhaseRi @ 21 NONAME R3UNUSED ; I2s::ReadFIFOModeStatus(int, I2s::TI2sFramePhase, int &)
+	ReadReceiveRegister__3I2siQ23I2s14TI2sFramePhaseRi @ 22 NONAME R3UNUSED ; I2s::ReadReceiveRegister(int, I2s::TI2sFramePhase, int &)
+	ReadRegisterModeStatus__3I2siQ23I2s14TI2sFramePhaseRi @ 23 NONAME R3UNUSED ; I2s::ReadRegisterModeStatus(int, I2s::TI2sFramePhase, int &)
+	ReadTransmitRegister__3I2siQ23I2s14TI2sFramePhaseRi @ 24 NONAME R3UNUSED ; I2s::ReadTransmitRegister(int, I2s::TI2sFramePhase, int &)
+	SetDelayCycles__3I2siQ23I2s14TI2sFramePhasei @ 25 NONAME R3UNUSED ; I2s::SetDelayCycles(int, I2s::TI2sFramePhase, int)
+	SetFIFOThreshold__3I2siQ23I2s14TI2sFramePhaseQ23I2s13TI2sDirectioni @ 26 NONAME ; I2s::SetFIFOThreshold(int, I2s::TI2sFramePhase, I2s::TI2sDirection, int)
+	SetFrameLengthAndFormat__3I2siQ23I2s15TI2sFrameLengthi @ 27 NONAME R3UNUSED ; I2s::SetFrameLengthAndFormat(int, I2s::TI2sFrameLength, int)
+	SetSampleLength__3I2siQ23I2s14TI2sFramePhaseQ23I2s16TI2sSampleLength @ 28 NONAME R3UNUSED ; I2s::SetSampleLength(int, I2s::TI2sFramePhase, I2s::TI2sSampleLength)
+	SetSamplingRate__3I2siQ23I2s16TI2sSamplingRate @ 29 NONAME R3UNUSED ; I2s::SetSamplingRate(int, I2s::TI2sSamplingRate)
+	Start__3I2sii @ 30 NONAME R3UNUSED ; I2s::Start(int, int)
+	Stop__3I2sii @ 31 NONAME R3UNUSED ; I2s::Stop(int, int)
+	ConfigureInterface__3I2siP5TDes8 @ 32 NONAME R3UNUSED ; I2s::ConfigureInterface(int, TDes8 *)
+




