diff -r 000000000000 -r a41df078684a bsptemplate/asspandvariant/template_variant/specific/variant.cia
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/bsptemplate/asspandvariant/template_variant/specific/variant.cia	Mon Oct 19 15:55:17 2009 +0100
@@ -0,0 +1,55 @@
+// Copyright (c) 1994-2009 Nokia Corporation and/or its subsidiary(-ies).
+// All rights reserved.
+// This component and the accompanying materials are made available
+// under the terms of the License "Eclipse Public License v1.0"
+// which accompanies this distribution, and is available
+// at the URL "http://www.eclipse.org/legal/epl-v10.html".
+//
+// Initial Contributors:
+// Nokia Corporation - initial contribution.
+//
+// Contributors:
+//
+// Description:
+// template\template_variant\specific\variant.cia
+// 
+//
+
+#include <e32cia.h>
+#include "variant.h"
+#include "mconf.h"
+
+/******************************************************************************
+ * Interrupt handling/dispatch
+ ******************************************************************************/
+__NAKED__ void XIntDispatch(TAny*)
+	{
+	// Service second-level Variant Interrupts
+	// Enter with r0->{Variant int controller base; Handlers;}
+	asm("stmfd sp!, {r4,lr} ");
+	asm("ldmia r0, {r3,r4} ");										// r3=Variant interrupt controller base, r4->handlers
+	asm("0: ");
+	asm("ldr r0, [r3, #%a0]" : : "i" ((TInt)KHoIntContEnable));		// r0=bitmask with enabled interrupts
+	asm("ldr r1, [r3, #%a0]" : : "i" ((TInt)KHoIntContPending));	// r1=bitmask with pending interrupts
+	asm("mov r2, #31 ");											// int id
+	asm("and r0, r0, r1 ");
+	asm("bics r0, r0, #0xf8000000 ");								// mask unused bits (only 26 2nd-level ints defined)
+	asm("ldmeqfd sp!, {r4,pc} ");									// if no 2nd level interrupts pending, exit
+	asm("cmp r0, #0x00010000 ");
+	asm("movcc r0, r0, lsl #16 ");
+	asm("subcc r2, r2, #16 ");
+	asm("cmp r0, #0x01000000 ");
+	asm("movcc r0, r0, lsl #8 ");
+	asm("subcc r2, r2, #8 ");
+	asm("cmp r0, #0x10000000 ");
+	asm("movcc r0, r0, lsl #4 ");
+	asm("subcc r2, r2, #4 ");
+	asm("cmp r0, #0x40000000 ");
+	asm("movcc r0, r0, lsl #2 ");
+	asm("subcc r2, r2, #2 ");
+	asm("cmp r0, #0x80000000 ");
+	asm("subcc r2, r2, #1 ");										// r2=bit no. of MS 1
+	asm("add r0, r4, r2, lsl #3 ");									// r0->handler for this interrupt
+	asm("adr lr, 0b ");												// look again after calling handler
+	asm("ldmia r0, {r0,pc} ");										// jump to handler
+	}