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1 <?xml version="1.0" encoding="utf-8"?> |
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2 <!-- Copyright (c) 2007-2010 Nokia Corporation and/or its subsidiary(-ies) All rights reserved. --> |
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3 <!-- This component and the accompanying materials are made available under the terms of the License |
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4 "Eclipse Public License v1.0" which accompanies this distribution, |
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5 and is available at the URL "http://www.eclipse.org/legal/epl-v10.html". --> |
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6 <!-- Initial Contributors: |
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7 Nokia Corporation - initial contribution. |
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8 Contributors: |
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9 --> |
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10 <!DOCTYPE concept |
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11 PUBLIC "-//OASIS//DTD DITA Concept//EN" "concept.dtd"> |
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12 <concept id="GUID-10FD1B94-EC0C-458F-839F-B60A8E47BAD6" xml:lang="en"><title>Baseport Template Configuration Guide</title><shortdesc>Describes the configuration of the Baseport Template platform |
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13 service.</shortdesc><prolog><metadata><keywords/></metadata></prolog><conbody> |
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14 <p>The <filepath>config.inc</filepath> file provided at <filepath>os/kernelhwsrv/bsptemplate/asspandvariant/template_variant/config.inc</filepath> is used to set up the platform specific values in the Baseport. |
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15 The comments in the <filepath>config.inc</filepath> file explains |
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16 the various options that can be used to configure the baseport. </p> |
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17 <section id="GUID-67DA5F25-67FB-440D-8473-1261922AFC73"><title>Template |
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18 configuration</title><p>A sample configuration file is available in |
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19 the template. The configuration file looks like the one below:</p><codeblock xml:space="preserve"> |
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20 ; template\config.inc |
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21 ; |
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22 ;Include to enable tracing |
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23 ; GBLL CFG_DebugBootRom |
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24 |
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25 ; |
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26 ; Include one of these to select the CPU |
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27 ; GBLL CFG_CPU_GENERIC_ARM4 |
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28 ; GBLL CFG_CPU_ARM710T |
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29 ; GBLL CFG_CPU_ARM720T |
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30 ; GBLL CFG_CPU_SA1 |
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31 ; GBLL CFG_CPU_ARM925T |
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32 ; GBLL CFG_CPU_ARM926J |
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33 ; GBLL CFG_CPU_XSCALE |
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34 ; GBLL CFG_CPU_ARM1136 |
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35 ; GBLL CFG_CPU_ARM1176 |
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36 ; GBLL CFG_CORTEX_A8 |
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37 |
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38 ; Include the following line if this is a bootloader bootstrap |
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39 ; GBLL CFG_BootLoader |
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40 |
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41 ; TO DO: |
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42 ; The following line needs to be removed for target hardware |
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43 GBLL CFG_Template |
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44 |
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45 ; If you want to supply a custom set of initial vectors (including reset vector) include the following line |
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46 ; GBLL CFG_CustomVectors |
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47 ; |
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48 ; and provide a custom_vectors.inc file |
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49 |
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50 ; Variant Number, just an example: |
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51 INIT_NUMERIC_CONSTANT CFG_HWVD, 0x09080001 |
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52 |
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53 ; On ARM architecture 6 processors, include the following line to override the threshold |
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54 ; on total physical RAM size at which the multiple memory model switches into large address space mode |
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55 ; i.e. size>threshold -> 2Gb per process, size<=threshold -> 1Gb per process |
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56 ; Defaults to 32Mb. |
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57 ; INIT_NUMERIC_CONSTANT CFG_ARMV6_LARGE_CONFIG_THRESHOLD, ;<value &rt; |
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58 ; For the direct memory model only, include the following line if you wish the exception vectors at the |
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59 ; start of the bootstrap to be used at all times. This is only relevant if an MMU is present - this option |
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60 ; is mandatory if not. |
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61 ; GBLL CFG_UseBootstrapVectors |
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62 ; |
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63 ; If the above option is in use (including if no MMU is present) the following symbol should be defined |
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64 ; to specify the offset from the bootstrap to the kernel image. INIT_NUMERIC_CONSTANT KernelCodeOffset, 0x4000 |
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65 ; Include the following line if you wish to include the ROM autodetection code based on data bus |
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66 ; capacitance and image repeats. |
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67 ; GBLL CFG_AutoDetectROM |
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68 ; Include the following line to minimise the initial kernel heap size |
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69 ; On the direct memory model the size of the kernel data area (super page to end of kernel heap) |
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70 ; is rounded up to the next 1Mb if this is not included, 4K if it is. |
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71 ; On the moving and multiple models, the size of the initial kernel heap area is rounded up to |
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72 ; the next 64K if this is not included, 4K if it is. |
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73 ; GBLL CFG_MinimiseKernelHeap |
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74 ; Include the following line if default memory mapping should use shared memory. |
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75 ; Should be defined on multicore (SMP) devices. |
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76 ; GBLL CFG_USE_SHARED_MEMORY |
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77 ; On the moving or multiple memory models, include either or both of the following lines to |
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78 ; specify the size of the initial kernel heap |
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79 ; INIT_NUMERIC_CONSTANT CFG_KernelHeapMultiplier, <multiplier> |
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80 ; INIT_NUMERIC_CONSTANT CFG_KernelHeapBaseSize, <base> |
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81 ; |
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82 ; The initial kernel heap size is MAX( <base> + <multiplier> * N / 16, value specified in ROMBUILD ) |
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83 ; where N is the total physical RAM size in pages. |
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84 ; <base> defaults to 24K and <multiplier> defaults to 9*16 (ie 9 bytes per page). |
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85 ; Uncomment if using ARM1136 processor and ARM1136 Erratum 353494 |
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86 ; "Rare conditions can cause corruption of the Instruction Cache" |
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87 ; is fixed on this hardware. |
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88 ; NOTE: The boot table should use this macro to determine whether RONO or RORO permissions |
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89 ; are used for the exception vectors. If the erratum is not fixed, RORO must be used. |
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90 ; |
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91 ; GBLL CFG_CPU_ARM1136_ERRATUM_353494_FIXED |
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92 ; Uncomment if using ARM1136 processor and ARM1136 Erratum 364296 |
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93 ; "Possible Cache Data Corruption with Hit-Under-Miss" |
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94 ; is fixed on this hardware. |
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95 ; |
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96 ; GBLL CFG_CPU_ARM1136_ERRATUM_364296_FIXED |
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97 ; Uncomment if using ARM1136 processor and ARM1136 Erratum 399234 |
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98 ; "Write back data cache entry evicted by write through entry causes data corruption" |
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99 ; is fixed on this hardware. |
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100 ; |
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101 ; Workaround |
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102 ; The erratum may be avoided by marking all cacheable memory as one of write through or write back. |
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103 ; This requires the memory attributes described in the translation tables to be modified by software |
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104 ; appropriately, or the use of the remapping capability to remap write through regions to non cacheable. |
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105 ; |
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106 ; If this macro is enabled, it should be accompanied by: |
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107 ; "macro __CPU_ARM1136_ERRATUM_399234_FIXED" in variant.mmh |
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108 ; GBLL CFG_CPU_ARM1136_ERRATUM_399234_FIXED |
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109 ; |
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110 ; Uncomment if: |
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111 ; 1) using ARM1136 processor and ARM1136 Erratum 411920: "Invalidate Entire Instruction Cache |
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112 ; operation might fail to invalidate some lines if coincident with linefill" |
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113 ; is fixed on this hardware, or |
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114 ; 2) using ARM1176 processor and ARM1176 Erratum 415045: "Invalidate Entire Instruction Cache |
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115 ; operation might fail to invalidate some lines if coincident with linefill |
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116 ; is fixed on this hardware. |
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117 ; Workaround: |
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118 ; 1) Disables the use of of prefetch range cache operations by setting RV bit in Auxiliary Ctrl Reg. |
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119 ; 2) Replaces Invalidate ICache operation with the sequence defined in the errata document. |
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120 ; |
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121 ; If this macro is enabled, it should be accompanied by: |
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122 ; "macro __CPU_ARM1136_ERRATUM_411920_FIXED" in variant.mmh |
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123 ; |
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124 ; GBLL CFG_CPU_ARM1136_ERRATUM_411920_FIXED |
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125 ; |
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126 ; Uncomment if using ARM1136 processor and ARM1136 Erratum 415662: "Invalidate Instruction Cache by |
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127 ; Index might corrupt cache when used with background prefetch range" is fixed on this hardware. |
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128 ; Workaround: |
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129 ; Disables the use of of prefetch range cache operations by setting RV bit in Auxiliary Ctrl Reg. |
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130 ; |
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131 ; GBLL CFG_CPU_ARM1136_ERRATUM_415662_FIXED |
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132 ; |
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133 ; These are deduced from the supplied configuration |
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134 ; CFG_ARMV6 ; CFG_MMUPresent |
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135 ; CFG_CachePresent ; CFG_WriteBufferPresent |
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136 ; CFG_SplitCache |
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137 ; CFG_SplitTLB |
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138 ; CFG_AltDCachePresent |
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139 ; CFG_WriteBackCache |
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140 ; CFG_CacheWriteAllocate |
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141 ; CFG_CachePhysicalTag |
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142 ; CFG_CacheFlushByDataRead |
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143 ; CFG_CacheFlushByWaySetIndex |
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144 ; CFG_CacheFlushByLineAlloc |
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145 ; CFG_CachePolicyInPTE |
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146 ; CFG_TEX |
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147 ; CFG_SingleEntryDCacheFlush |
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148 ; CFG_SingleEntryICacheFlush |
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149 ; CFG_SingleEntryITLBFlush |
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150 ; CFG_SingleEntryTLBFlush |
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151 ; CFG_CacheTypeReg |
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152 ; CFG_BTBPresent |
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153 ; CFG_CARPresent |
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154 ; CFG_PrefetchBuffer |
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155 ; CFG_FCSE_Present |
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156 ; CFG_ASID_Present |
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157 ; CFG_IncludeRAMAllocator |
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158 END |
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159 </codeblock><note> Ensure that you have made the line <codeph>GBLL CFG_Template </codeph> a comment and have selected the lines for the required configuration.</note></section> |
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160 </conbody><related-links> |
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161 <link href="GUID-AE486C82-8854-463F-8CB9-B7353D6B2804.dita"><linktext>Baseport |
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162 Template Build Guide</linktext></link> |
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163 </related-links></concept> |