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1 <?xml version="1.0" encoding="utf-8"?> |
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2 <!-- Copyright (c) 2007-2010 Nokia Corporation and/or its subsidiary(-ies) All rights reserved. --> |
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3 <!-- This component and the accompanying materials are made available under the terms of the License |
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4 "Eclipse Public License v1.0" which accompanies this distribution, |
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5 and is available at the URL "http://www.eclipse.org/legal/epl-v10.html". --> |
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6 <!-- Initial Contributors: |
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7 Nokia Corporation - initial contribution. |
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8 Contributors: |
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9 --> |
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10 <!DOCTYPE concept |
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11 PUBLIC "-//OASIS//DTD DITA Concept//EN" "concept.dtd"> |
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12 <concept id="GUID-4E3C086B-25BE-4DAC-9E21-CFC4F8B792A5" xml:lang="en"><title>DMA Technology Guide</title><shortdesc>Describes the Direct Memory Access framework.</shortdesc><prolog><metadata><keywords/></metadata></prolog><conbody> |
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13 <section id="GUID-E987EF55-27CE-4EC2-B250-2C3D7C36CAF9"><title>Purpose</title><p>The DMA framework provides a generic simple interface for the |
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14 clients to access DMA resources in a device. The primary clients are |
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15 device drivers that will use the DMA framework to set up DMA transfers. |
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16 A device can have more than one DMA controller (DMAC). </p></section> |
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17 <section id="GUID-7607CC80-0FA0-4FC2-897A-C4AB6B6C74FC"><title>Architectural |
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18 concepts</title><p>The key concepts related to DMA framework are:</p><fig id="GUID-ECCF1F57-DBD0-4653-A631-F8972E24DECF"> |
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19 <title>DMA Framework</title> |
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20 <image href="GUID-10FE825A-4383-4A10-A507-58577BB230FB_d0e89974_href.png" placement="inline"/> |
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21 </fig><dl> |
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22 <dlentry> |
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23 <dt>DMA Client</dt> |
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24 <dd><p>A device driver or a kernel object that needs to use the resources |
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25 of the DMA framework. On the Symbian platform, the Physical Device |
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26 Drivers are the primary clients of the DMA framework. </p></dd> |
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27 </dlentry> |
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28 <dlentry> |
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29 <dt>DMA Platform Service API</dt> |
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30 <dd><p>The generic interface to provide DMA services to the clients.</p></dd> |
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31 </dlentry> |
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32 <dlentry> |
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33 <dt>DMA Import Library</dt> |
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34 <dd><p>The DMA clients link against the <filepath>dma.lib</filepath> file.</p></dd> |
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35 </dlentry> |
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36 <dlentry> |
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37 <dt>DMA Platform-Independent Layer (PIL)</dt> |
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38 <dd><p>The platform-independent layer contains the generic framework |
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39 independent from the hardware.</p></dd> |
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40 </dlentry> |
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41 <dlentry> |
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42 <dt>DMA Platform-Specific Layer (PSL)</dt> |
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43 <dd><p>The platform-specific layer is specific to the baseport and |
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44 the hardware used.</p></dd> |
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45 </dlentry> |
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46 <dlentry> |
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47 <dt>DMA Controller (DMAC)</dt> |
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48 <dd><p>The DMAC is the DMA hardware implementation. The number of |
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49 DMAC in the implementation of the DMA Framework depends on the hardware. |
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50 The DMAC is a peripheral to the CPU and is programmed to control data |
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51 transfers without using the CPU. </p></dd> |
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52 </dlentry> |
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53 </dl></section> |
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54 <section id="GUID-CAC0FE8F-A338-4B0E-92ED-7A1D1FD52C24"><title>DMA |
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55 functionality</title><p>The key concepts related to functionality |
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56 provided by the DMA framework are:</p><dl> |
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57 <dlentry> |
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58 <dt>Scatter/Gather Mode</dt> |
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59 <dd><p>Some DMA controllers transfer data using scatter/gather mode. |
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60 In this mode, the operating system creates a DMA descriptor with source |
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61 and destination memory addresses and the configuration. The source |
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62 and destination data can be a list of scattered memory blocks. The |
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63 DMA controller uses this configuration to perform the data transfer.</p></dd> |
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64 </dlentry> |
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65 <dlentry> |
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66 <dt>DMA Descriptors</dt> |
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67 <dd><p>The data structure used by the DMA framework to store the configuration |
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68 of the data transfer. These will store details such as source address, |
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69 destination address, number of bytes and pointer to the next descriptor, |
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70 when the DMA is used to transfer disjoint blocks of data. This structure |
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71 is defined in the platform specific layer. The descriptors are always |
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72 used to store the configuration even if the DMA controller does not |
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73 support scatter/gather mode. When the scatter/gather mode is not supported |
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74 by the DMAC, the descriptors used to store the configuration are called |
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75 as pseudo-descriptors.</p></dd> |
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76 </dlentry> |
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77 <dlentry> |
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78 <dt>Descriptor Headers</dt> |
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79 <dd><p>The descriptor headers are used to store additional information |
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80 about the descriptors. The descriptors are accessed using the descriptor |
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81 headers which contain the pointer to the descriptor.</p></dd> |
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82 </dlentry> |
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83 <dlentry> |
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84 <dt>Transfer Request</dt> |
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85 <dd><p>The device drivers configure and initialize a data transfer |
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86 using the class <xref href="GUID-780F4D53-5546-3B69-B328-0226C70EBDE2.dita"><apiname>DDmaRequest</apiname></xref>. The data can be transferred |
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87 between:<ul> |
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88 <li><p>memory to memory</p></li> |
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89 <li><p>memory to peripheral</p></li> |
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90 <li><p>peripheral to memory</p></li> |
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91 </ul>The transfer request stores the callback function of the clients. |
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92 The callback function is used to notify the success or failure of |
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93 a data transfer.</p></dd> |
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94 </dlentry> |
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95 <dlentry> |
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96 <dt>DMA Channel</dt> |
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97 <dd><p>The object which represents a single hardware, logical or a |
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98 virtual channel. In the DMA platform service API, each DMA channel |
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99 is referred to by a 32-bit value called a cookie. Each DMA transfer |
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100 is in the form of a description header and its associated DMA descriptor. |
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101 The queue of transfer requests (both being transferred and pending) |
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102 consists of a linked list of the DMA headers. </p></dd> |
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103 </dlentry> |
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104 <dlentry> |
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105 <dt>DMA Channel Allocator</dt> |
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106 <dd><p>The channel manager controls the opening and closing of DMA |
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107 channels. The channel manager functions are defined in the platform |
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108 independent layer and implemented in the platform specific layer. </p></dd> |
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109 </dlentry> |
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110 </dl></section> |
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111 <section id="GUID-F64155FC-5245-447F-88E7-C642EDEB2CEE"><title>Typical |
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112 Uses</title><p>The typical use cases of a DMA framework are:</p><ul> |
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113 <li><p>programmable data transfer between hardware peripherals and |
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114 memory buffers</p></li> |
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115 <li><p>programmable data transfer of block of data between different |
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116 regions of memory</p></li> |
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117 </ul></section> |
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118 </conbody><related-links> |
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119 <link href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0424b/index.html.dita"> |
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120 <linktext>ARM DMA Controller Reference Manual</linktext></link> |
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121 </related-links></concept> |