--- a/Symbian3/PDK/Source/GUID-96F07979-3863-5198-AF8B-4ACC1193CF3E.dita	Thu Mar 11 15:24:26 2010 +0000
+++ b/Symbian3/PDK/Source/GUID-96F07979-3863-5198-AF8B-4ACC1193CF3E.dita	Thu Mar 11 18:02:22 2010 +0000
@@ -1,30 +1,30 @@
-<?xml version="1.0" encoding="utf-8"?>
-<!-- Copyright (c) 2007-2010 Nokia Corporation and/or its subsidiary(-ies) All rights reserved. -->
-<!-- This component and the accompanying materials are made available under the terms of the License 
-"Eclipse Public License v1.0" which accompanies this distribution, 
-and is available at the URL "http://www.eclipse.org/legal/epl-v10.html". -->
-<!-- Initial Contributors:
-    Nokia Corporation - initial contribution.
-Contributors: 
--->
-<!DOCTYPE concept
-  PUBLIC "-//OASIS//DTD DITA Concept//EN" "concept.dtd">
-<concept id="GUID-96F07979-3863-5198-AF8B-4ACC1193CF3E" xml:lang="en"><title>Level
-2 Cache Tutorial</title><shortdesc>This topic describes how to configure the base port to use the
-ARM L210 cache or L220 cache controllers in ARM processors. </shortdesc><prolog><metadata><keywords/></metadata></prolog><conbody>
-<p>Cache is a fast buffer that keeps copies of recently accessed memory. </p>
-<section id="GUID-6ECBAFBD-87A5-4CB2-8A83-24F5208A58DA"><title>L210 Cache</title> <p>In the <filepath>variant.mmh</filepath> file,
-set the macro: </p> <codeblock id="GUID-FB4E4E84-828F-5FD6-A296-F55FA8F7C25D" xml:space="preserve">__ARM_L210_CACHE__</codeblock> <p>You
-must also set a L210 Cache macro and initialise Level 2 cache in the Bootstrap.
-See <xref href="GUID-4A910E9F-E881-51D7-A84A-CBC6AC343FD1.dita">Level 2 Cache Macros</xref> and <xref href="GUID-F67FA7B5-F6D1-5C5C-8E10-A8E317A778E4.dita#GUID-F67FA7B5-F6D1-5C5C-8E10-A8E317A778E4/GUID-C111DA06-F7EE-5E70-8D86-26BA2213B506">HardwareInitialise()</xref>. </p> <p>The
-L210 cache is switched on by generic Symbian OS code before jumping into the
-kernel code. The cache is switched on after the MMU and L1 cache are enabled. </p> </section>
-<section id="GUID-D713DF71-C896-45EA-86D6-55E5FF9CFABC"><title>L220 Cache</title> <p>In the <filepath>variant.mmh</filepath> file,
-set the macro: </p> <codeblock id="GUID-8DCEE6B7-E852-5B3D-AFE7-E512DCAA73C0" xml:space="preserve">__ARM_L220_CACHE__</codeblock> <p>You
-must also set a L220 Cache macro and initialise Level 2 cache in the Bootstrap.
-See <xref href="GUID-4A910E9F-E881-51D7-A84A-CBC6AC343FD1.dita">Level 2 Cache Macros</xref> and <xref href="GUID-F67FA7B5-F6D1-5C5C-8E10-A8E317A778E4.dita#GUID-F67FA7B5-F6D1-5C5C-8E10-A8E317A778E4/GUID-C111DA06-F7EE-5E70-8D86-26BA2213B506">HardwareInitialise()</xref>. </p> <p>Code
-to switch on the L220 cache on must be provided by the base port. You can
-do this in the <xref href="GUID-F67FA7B5-F6D1-5C5C-8E10-A8E317A778E4.dita#GUID-F67FA7B5-F6D1-5C5C-8E10-A8E317A778E4/GUID-C111DA06-F7EE-5E70-8D86-26BA2213B506">HardwareInitialise()</xref> function
-or the <xref href="GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE.dita#GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE/GUID-EEF889E7-915F-57E9-8E2D-DC17B24C7728">BTF_Final()</xref> function
-in the Bootstrap. </p> </section>
+<?xml version="1.0" encoding="utf-8"?>
+<!-- Copyright (c) 2007-2010 Nokia Corporation and/or its subsidiary(-ies) All rights reserved. -->
+<!-- This component and the accompanying materials are made available under the terms of the License 
+"Eclipse Public License v1.0" which accompanies this distribution, 
+and is available at the URL "http://www.eclipse.org/legal/epl-v10.html". -->
+<!-- Initial Contributors:
+    Nokia Corporation - initial contribution.
+Contributors: 
+-->
+<!DOCTYPE concept
+  PUBLIC "-//OASIS//DTD DITA Concept//EN" "concept.dtd">
+<concept id="GUID-96F07979-3863-5198-AF8B-4ACC1193CF3E" xml:lang="en"><title>Level
+2 Cache Tutorial</title><shortdesc>This topic describes how to configure the base port to use the
+ARM L210 cache or L220 cache controllers in ARM processors. </shortdesc><prolog><metadata><keywords/></metadata></prolog><conbody>
+<p>Cache is a fast buffer that keeps copies of recently accessed memory. </p>
+<section id="GUID-6ECBAFBD-87A5-4CB2-8A83-24F5208A58DA"><title>L210 Cache</title> <p>In the <filepath>variant.mmh</filepath> file,
+set the macro: </p> <codeblock id="GUID-FB4E4E84-828F-5FD6-A296-F55FA8F7C25D" xml:space="preserve">__ARM_L210_CACHE__</codeblock> <p>You
+must also set a L210 Cache macro and initialise Level 2 cache in the Bootstrap.
+See <xref href="GUID-4A910E9F-E881-51D7-A84A-CBC6AC343FD1.dita">Level 2 Cache Macros</xref> and <xref href="GUID-F67FA7B5-F6D1-5C5C-8E10-A8E317A778E4.dita#GUID-F67FA7B5-F6D1-5C5C-8E10-A8E317A778E4/GUID-C111DA06-F7EE-5E70-8D86-26BA2213B506">HardwareInitialise()</xref>. </p> <p>The
+L210 cache is switched on by generic Symbian OS code before jumping into the
+kernel code. The cache is switched on after the MMU and L1 cache are enabled. </p> </section>
+<section id="GUID-D713DF71-C896-45EA-86D6-55E5FF9CFABC"><title>L220 Cache</title> <p>In the <filepath>variant.mmh</filepath> file,
+set the macro: </p> <codeblock id="GUID-8DCEE6B7-E852-5B3D-AFE7-E512DCAA73C0" xml:space="preserve">__ARM_L220_CACHE__</codeblock> <p>You
+must also set a L220 Cache macro and initialise Level 2 cache in the Bootstrap.
+See <xref href="GUID-4A910E9F-E881-51D7-A84A-CBC6AC343FD1.dita">Level 2 Cache Macros</xref> and <xref href="GUID-F67FA7B5-F6D1-5C5C-8E10-A8E317A778E4.dita#GUID-F67FA7B5-F6D1-5C5C-8E10-A8E317A778E4/GUID-C111DA06-F7EE-5E70-8D86-26BA2213B506">HardwareInitialise()</xref>. </p> <p>Code
+to switch on the L220 cache on must be provided by the base port. You can
+do this in the <xref href="GUID-F67FA7B5-F6D1-5C5C-8E10-A8E317A778E4.dita#GUID-F67FA7B5-F6D1-5C5C-8E10-A8E317A778E4/GUID-C111DA06-F7EE-5E70-8D86-26BA2213B506">HardwareInitialise()</xref> function
+or the <xref href="GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE.dita#GUID-B3F6FC45-3BF0-5F92-8325-44C705BA47AE/GUID-EEF889E7-915F-57E9-8E2D-DC17B24C7728">BTF_Final()</xref> function
+in the Bootstrap. </p> </section>
 </conbody></concept>
\ No newline at end of file