Bootstrap Source Macros

This set of macros is available for use in source files, but not in platform +specific configuration header files. Their definitions are obtained by including os/kernelhwsrv/kernel/eka/include/kernel/arm/bootcpu.inc.

General macros

GETCPSR

GETCPSR reg

Reads +the CPSR into the specified ARM general register reg.

This +macro should be used in preference to MRS instructions to avoid problems related +to syntax incompatibility between different assembler versions.

CGETCPSR

CGETCPSR reg, cc

Reads +the CPSR into the specified ARM general register reg. This +is conditionally executed using cc as the execution condition.

This +macro should be used in preference to MRS instructions to avoid problems related +to syntax incompatibility between different assembler versions.

GETSPSR

GETSPSR reg

Reads +the SPSR into the specified ARM general register reg.

This +macro should be used in preference to MRS instructions to avoid problems related +to syntax incompatibility between different assembler versions.

CGETSPSR

CGETSPSR reg, cc

Reads +the SPSR into the specified ARM general register reg. This +is conditionally executed using cc as the execution condition.

This +macro should be used in preference to MRS instructions to avoid problems related +to syntax incompatibility between different assembler versions.

SETCPSR

SETCPSR reg

Writes +the entire (all 32 bits) CPSR from the specified ARM general register reg.

This +macro should be used in preference to MRS instructions to avoid problems related +to syntax incompatibility between different assembler versions.

CSETCPSR

CSETCPSR reg, cc

Writes +the entire (all 32 bits) CPSR from the specified ARM general register reg. +This is conditionally executed using cc as the execution +condition.

This macro should be used in preference to MRS instructions +to avoid problems related to syntax incompatibility between different assembler +versions.

SETSPSR

SETSPSR reg

Writes +the entire (all 32 bits) SPSR from the specified ARM general register reg.

This +macro should be used in preference to MRS instructions to avoid problems related +to syntax incompatibility between different assembler versions.

CSETSPSR

CSETSPSR reg, cc

Writes +the entire (all 32 bits) SPSR from the specified ARM general register reg. +This is conditionally executed using cc as the execution +condition.

This macro should be used in preference to MRS instructions +to avoid problems related to syntax incompatibility between different assembler +versions.

BOOTCALL

BOOTCALL call_numbe

Calls +the specified function via the boot table. call_number should +be one of the BTF_* values in the TBootTableEntry enumeration, +defined in os/kernelhwsrv/kernel/eka/include/kernel/arm/bootdefs.h.

The +macro is transparent; the function is entered with all registers and flags +having the same values as immediately before the macro.

GETPARAM

GETPARAM pnum, default

Retrieves +the parameter with number pnum from the boot parameter table, +and returns its value in R0. If the parameter is not present +in the table, then R0 is loaded with value default.

See +the description of BTF_Params for +more information on the boot parameter table.

GETMPARAM

GETMPARAM pnum

Retrieves +the parameter with number pnum from the boot parameter table, +and returns its value in R0. If the parameter is not present +in the table, then the macro faults the system.

See the description +of BTF_Params for +more information on the boot parameter table.

FAULT

FAULT cc

Faults +the system if condition cc is true. The condition is a standard +ARM condition code.

BTP_ENTRY

Declares +MMU permissions and cache attributes. The macro takes a variable number of +arguments depending on the processor in use.

For ARM architecture 6 +CPUs:

BTP_ENTRY $domain, $perm, $cache, $execute, $global, $P, $S

For +XScale CPUs:

BTP_ENTRY $domain, $perm, $cache, $P

For +other CPUs:

BTP_ENTRY $domain, $perm, $cache + + + +

$domain

ARM domain number 0-15. In general only one memory-model-dependent +value is used here and the symbol CLIENT_DOMAIN specifies +this.

+ + +

$perm

Permissions for mapping.

For architecture 6 CPUs, use one +of PERM_NONO, PERM_RWNO, PERM_RWRO, PERM_RWRW, PERM_RONO, PERM_RORO.

For other CPUs, use one of PERM_RORO, PERM_RWNO, PERM_RWRO, PERM_RWRW.

In each of these names the first pair of letters +refers to supervisor, and the second pair to user access, so PERM_RWNO means +supervisor read/write, user no access.

+ + +

$cache

Cache attributes for mapping. These are processor dependent - see +the CACHE_* macros in os/kernelhwsrv/kernel/eka/include/kernel/arm/bootcpu.inc.

+ + +

$execute

ARM architecture 6 only. Determines whether code can be executed +from the mapped region; either BTPERM_EXECUTE or BTPERM_NO_EXECUTE.

+ + +

$global

ARM architecture 6 only. Determines whether the mapped region is +ASID specific (local) or non-ASID specific (global); either BTPERM_LOCAL or BTPERM_GLOBAL.

+ + +

ARM architecture 6 and XScale only. Determines whether or not ECC +should be used on the mapped region (assuming hardware supports ECC); either BTPERM_ECC or BTPERM_NON_ECC.

+ + +

ARM architecture 6 only. Determines whether the mapped region is +shared between multiple CPUs or not; either BTPERM_SHARED or BTPERM_NON_SHARED.

+ + + +

ROM_BANK

ROM_BANK PHYS, SIZE, LIN, WIDTH, TYPE, RAND, SEQ

Declares +an XIP ROM bank entry.

+ + + +

PHYS

The physical base address of the ROM bank.

+ + +

SIZE

The size of the ROM bank.

+ + +

LIN

Linear address override (usually 0).

+ + +

WIDTH

Bus width. One of: ROM_WIDTH_8, ROM_WIDTH_16 or ROM_WIDTH_32

+ + +

TYPE

The ROM type; see the TRomType enumeration.

+ + +

RAND

Random access speed.

+ + +

SEQ

Sequential access speed.

+ + + +

See also BTF_RomBanks in Boot Table Functions.

Macros for +declaring I/O mappings

HW_MAPPING

HW_MAPPING PHYS,SIZE,MULT

Defines +an I/O mapping using the standard permissions and cache attributes for I/O +mappings, i.e. those defined for the BTP_Hw boot table entry. +See Boot Table MMU +Permission and Cache Attribute Definitions.

+ + + +

PHYS

Physical base address.

+ + +

SIZE

Size of the mapping.

+ + +

MULT

Granularity +of the I/O mapping (below).

+ + + +