diff -r 578be2adaf3e -r 307f4279f433 Adaptation/GUID-654A788A-526A-4C3F-838C-05B09F0D5445.dita --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/Adaptation/GUID-654A788A-526A-4C3F-838C-05B09F0D5445.dita Fri Oct 15 14:32:18 2010 +0100 @@ -0,0 +1,109 @@ + + + + + +Interrupt Technology GuideDescribes the concepts of the Interrupts platform service. +

The Interrupt platform service provides an interface to the kernel +and device drivers to associate interrupt with an Interrupt Service +Routine (ISR). There are three levels of interrupt management:

    +
  1. CPU level: Control +of interrupts available only to the kernel.

  2. +
  3. Controller level: +Control provided by functions of the Interrupt class.

  4. +
  5. Device level: +Control of hardware sources that are managed by a device specific +control scheme.

  6. +

+
+ Key concepts
+ +
Interrupt
+

An interrupt is a hardware or a software event that may need +to be serviced. An example of a hardware interrupt is a key press +.

+
+ +
Interrupt ID
+

The unique ID of an interrupt source. The interrupt ID are +defined by the developers creating ASSP and variant.

+
+ +
Spurious interrupts
+

Interrupts not associated with an Interrupt Service Routine +are called the spurious interrupts. The spurious interrupts are handled +by a spurious interrupt handler which is only used for debugging.

+
+ +
ISR
+

An Interrupt Service Routine (ISR ) is the function to handle +an interrupt. ISR is not a class member. ISR provides the minimum +processing such as storing data that may not be available later and +requests a DFC for further processing.

+
+ +
Interrupt priority
+

The Interrupt platform service allows developers to set a priority +for each interrupt source. The meaning of the priority value depends +on the hardware and the baseport implementation.

+
+ +
Interrupt dispatch
+

When an interrupt is received by the system, it calls the associated +ISR. This is called interrupt dispatch. The interrupt dispatch is +provided by the implementation of the interrupt class +in the ASSP layer.

+
+ +
ISR table
+

The table that maps the interrupt ID and the associated ISR. +The ISR table is implemented by the developers creating the baseport +variant.

+
+ +
Binding
+

The process of associating an interrupt ID with an ISR. Unbinding +removes the association.

+
+ +
Chained interrupts
+

The output of a low priority interrupt controller is provided +as an input to a higher priority interrupt controller.

+
+
+ +
Pseudo-interrupts
+

Pseudo-interrupts correspond to multiple interrupt sources +sharing a single input to an interrupt controller but requiring separate +ISRs to service them. The ISRs cannot all be bound to the single real +interrupt and are therefore bound to the pseudo-interrupt instead.

+
+
+ +
IRQs and FIQs
+

An IRQ (interrupt request) is the signal generated by an item +of hardware or software to request an interrupt from the processor. +An FIQ (fast IRQ) is an IRQ with high priority on systems +which support prioritization of requests.

+
+
+
Typical +uses

The Interrupt platform service allows the kernel and +device drivers to :

    +
  • associate an ISR with an interrupt ID

  • +
  • enable/disable a specific interrupt

  • +
  • clear pending actions on a specific interrupt

  • +
  • change the priority of a specific interrupt.

  • +
+
+Interrupt +Implementation Guide +Handling +Interrupts +
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