diff -r 578be2adaf3e -r 307f4279f433 Adaptation/GUID-7ECDCF7B-3B2A-561F-9136-04BC4DAE46E4.dita --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/Adaptation/GUID-7ECDCF7B-3B2A-561F-9136-04BC4DAE46E4.dita Fri Oct 15 14:32:18 2010 +0100 @@ -0,0 +1,161 @@ + + + + + +ARM +Exception Types, Fault Status Register Values, and Processor Mode ValuesReference for users of the debug monitor tool to ARM exception +types, fault status register values, and processor mode values. +
ARM exception +types

The numeric value in the left hand column is the value of +the ExcId field displayed as a result of entering an f command +in the debug monitor.

+ + + +

00000000

+

Prefetch abort

+
+ +

00000001

+

Data abort

+
+ +

00000002

+

Undefined instruction

+
+ + +
+
Fault status +register values (FSR register)

The lowest 4-bits of the FSR register +indicates the fault generated by the MMU. The FSR register value is displayed +as a result of entering an f command +in the debug monitor.

+ + + +

0

+

Vector exception

+
+ +

1

+

Alignment fault

+
+ +

2

+

Terminal exception

+
+ +

3

+

Alignment fault

+
+ +

4

+

External abort on linefetch for section translation

+
+ +

5

+

Section translation fault (unmapped virtual address)

+
+ +

6

+

External abort on linefetch for page translation

+
+ +

7

+

Page translation fault (unmapped virtual address)

+
+ +

8

+

External abort on non-linefetch for section translation

+
+ +

9

+

Domain fault on section translation (i.e. accessing invalid domain)

+
+ +

A

+

External abort on non-linefetch for page translation

+
+ +

B

+

Domain fault on page translation (i.e. accessing invalid domain)

+
+ +

C

+

External abort on first level translation

+
+ +

D

+

Permission fault on section (i.e. no permission to access virtual +address)

+
+ +

E

+

External abort on second level translation

+
+ +

F

+

Permission fault on page (i.e. no permission to access virtual address)

+
+ + +
+
ARM processor +modes (CPSR register)

The 5 least-significant bits of the CPSR +register indicate the ARM processor mode. The CPSR register value is displayed +as a result of entering an f command +in the debug monitor.

+ + + +

CPSR[4:0]

+

Mode

+

Register set

+
+ +

10000

+

User

+

PC, R14..R0, CPSR

+
+ +

10001

+

FIQ

+

PC, R14_fiq..R8_fiq, R7-R0, CPSR, SPSR_fiq

+
+ +

10010

+

IRQ

+

PC, R14_irq, R13_irq, R12-R0, CPSR, SPSR_irq

+
+ +

10011

+

SVC

+

PC, R14_svc, R13_svc, R12-R0, CPSR, SPSR_sv

+
+ +

10111

+

Abort

+

PC, R14_abt, R13_abt, R12-R0, CPSR, SPSR_abt

+
+ +

11011

+

Undef

+

PC, R14_und, R13_und, R12-R0, CPSR, SPSR_und

+
+ +

11111

+

System

+

PC, R14..R0, CPSR

+
+ + +
+
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