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// Copyright (c) 2008-2009 Nokia Corporation and/or its subsidiary(-ies).
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// All rights reserved.
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// This component and the accompanying materials are made available
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// under the terms of the License "Eclipse Public License v1.0"
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// which accompanies this distribution, and is available
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// at the URL "http://www.eclipse.org/legal/epl-v10.html".
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//
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// Initial Contributors:
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// Nokia Corporation - initial contribution.
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//
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// Contributors:
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//
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// Description:
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// omap3530/omap3530_drivers/i2c/i2c.cpp
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// I2C Driver
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// Main interface, I2c, is declared in omap3530_i2c.h
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// A more restricted register orientated interface, I2cReg, is declared in omap3530_i2creg.h
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// This file is part of the Beagle Base port
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//
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#include <assp/omap3530_assp/omap3530_i2creg.h>
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#include <assp/omap3530_assp/omap3530_irqmap.h>
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#include <assp/omap3530_assp/omap3530_hardware_base.h>
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#include <assp/omap3530_assp/omap3530_ktrace.h>
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//#include <assp/omap3530_assp/omap3530_prm.h>
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#include <assp/omap3530_assp/omap3530_prcm.h>
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#include <nk_priv.h>
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#include <nklib.h>
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//#include <resourceman.h>
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_LIT(KDfcName, "I2C_DFC"); // Not used by the I2c dfc!
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DECLARE_STANDARD_EXTENSION()
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{
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return KErrNone;
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}
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namespace I2c
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{
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const TInt KMaxDevicesPerUnit = 8; // arbitary - change if required
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const TInt KNumUnits = E3 + 1;
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// Each unit has KMaxDevicesPerUnit of these structures. At least one for each slave device on it's bus.
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struct TDeviceControl
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{
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TDeviceAddress iAddress; // the slave devices address; 7 or 10 bits
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TDfcQue* iDfcQueue; // calling driver's DFC thread
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NFastSemaphore iSyncSem; // used to block the calling thread during synchronous transfers
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};
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// There are three instances of this structure - one for each I2C bus on the OMAP3530
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struct TUnitControl
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{
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TUnitControl();
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TSpinLock iLock; // prevents concurrent access to the request queue
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DMutex* iOpenMutex;
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enum
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{
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EIdle,
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ERead,
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EWrite
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} iState;
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// Configuration stored and checked during Open()
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TRole iRole;
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TMode iMode;
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void* iExclusiveClient;
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TRate iRate;
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TDeviceAddress iOwnAddress;
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// The DFC for this unit - it runs on the thread associated with the active transfer
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TDfc iDfc;
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// the slave devices on this unit's bus
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TDeviceControl iDevice[KMaxDevicesPerUnit];
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TInt iNumDevices;
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// The queue of requested transfers - the active transfer is the head of the queue
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TTransferPb* iTransferQ;
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TTransferPb* iTransferQTail; // the last transfer on the queue
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// the current phase of the sctive transfer
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TTransferPb* iCurrentPhase;
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};
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// The OMAP3530 register address
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const TUint KI2C_IE[KNumUnits] =
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{Omap3530HwBase::TVirtual<0x48070004>::Value, Omap3530HwBase::TVirtual<0x48072004>::Value, Omap3530HwBase::TVirtual<0x48060004>::Value};
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const TUint KI2C_STAT[KNumUnits] =
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{Omap3530HwBase::TVirtual<0x48070008>::Value, Omap3530HwBase::TVirtual<0x48072008>::Value, Omap3530HwBase::TVirtual<0x48060008>::Value};
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//const TUint KI2C_WE[KNumUnits] =
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// {Omap3530HwBase::TVirtual<0x4807000C>::Value, Omap3530HwBase::TVirtual<0x4807200C>::Value, Omap3530HwBase::TVirtual<0x4806000C>::Value};
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const TUint KI2C_SYSS[KNumUnits] =
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{Omap3530HwBase::TVirtual<0x48070010>::Value, Omap3530HwBase::TVirtual<0x48072010>::Value, Omap3530HwBase::TVirtual<0x48060010>::Value};
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const TUint KI2C_BUF[KNumUnits] =
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{Omap3530HwBase::TVirtual<0x48070014>::Value, Omap3530HwBase::TVirtual<0x48072014>::Value, Omap3530HwBase::TVirtual<0x48060014>::Value};
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const TUint KI2C_CNT[KNumUnits] =
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{Omap3530HwBase::TVirtual<0x48070018>::Value, Omap3530HwBase::TVirtual<0x48072018>::Value, Omap3530HwBase::TVirtual<0x48060018>::Value};
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const TUint KI2C_DATA[KNumUnits] =
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{Omap3530HwBase::TVirtual<0x4807001C>::Value, Omap3530HwBase::TVirtual<0x4807201C>::Value, Omap3530HwBase::TVirtual<0x4806001C>::Value};
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const TUint KI2C_SYSC[KNumUnits] =
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{Omap3530HwBase::TVirtual<0x48070020>::Value, Omap3530HwBase::TVirtual<0x48072020>::Value, Omap3530HwBase::TVirtual<0x48060020>::Value};
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const TUint KI2C_CON[KNumUnits] =
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{Omap3530HwBase::TVirtual<0x48070024>::Value, Omap3530HwBase::TVirtual<0x48072024>::Value, Omap3530HwBase::TVirtual<0x48060024>::Value};
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//const TUint KI2C_OA0[KNumUnits] =
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// {Omap3530HwBase::TVirtual<0x48070028>::Value, Omap3530HwBase::TVirtual<0x48072028>::Value, Omap3530HwBase::TVirtual<0x48060028>::Value};
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const TUint KI2C_SA[KNumUnits] =
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{Omap3530HwBase::TVirtual<0x4807002C>::Value, Omap3530HwBase::TVirtual<0x4807202C>::Value, Omap3530HwBase::TVirtual<0x4806002C>::Value};
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const TUint KI2C_PSC[KNumUnits] =
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{Omap3530HwBase::TVirtual<0x48070030>::Value, Omap3530HwBase::TVirtual<0x48072030>::Value, Omap3530HwBase::TVirtual<0x48060030>::Value};
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const TUint KI2C_SCLL[KNumUnits] =
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{Omap3530HwBase::TVirtual<0x48070034>::Value, Omap3530HwBase::TVirtual<0x48072034>::Value, Omap3530HwBase::TVirtual<0x48060034>::Value};
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const TUint KI2C_SCLH[KNumUnits] =
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{Omap3530HwBase::TVirtual<0x48070038>::Value, Omap3530HwBase::TVirtual<0x48072038>::Value, Omap3530HwBase::TVirtual<0x48060038>::Value};
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//const TUint KI2C_SYSTEST[KNumUnits] =
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// {Omap3530HwBase::TVirtual<0x4807003C>::Value, Omap3530HwBase::TVirtual<0x4807203C>::Value, Omap3530HwBase::TVirtual<0x4806003C>::Value};
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const TUint KI2C_BUFSTAT[KNumUnits] =
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{Omap3530HwBase::TVirtual<0x48070040>::Value, Omap3530HwBase::TVirtual<0x48072040>::Value, Omap3530HwBase::TVirtual<0x48060040>::Value};
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const TUint KI2C_OA1[KNumUnits] =
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{Omap3530HwBase::TVirtual<0x48070044>::Value, Omap3530HwBase::TVirtual<0x48072044>::Value, Omap3530HwBase::TVirtual<0x48060044>::Value};
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//const TUint KI2C_OA2[KNumUnits] =
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// {Omap3530HwBase::TVirtual<0x48070048>::Value, Omap3530HwBase::TVirtual<0x48072048>::Value, Omap3530HwBase::TVirtual<0x48060048>::Value};
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//const TUint KI2C_OA3[KNumUnits] =
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// {Omap3530HwBase::TVirtual<0x4807004C>::Value, Omap3530HwBase::TVirtual<0x4807204C>::Value, Omap3530HwBase::TVirtual<0x4806004C>::Value};
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//const TUint KI2C_ACTOA[KNumUnits] =
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// {Omap3530HwBase::TVirtual<0x48070050>::Value, Omap3530HwBase::TVirtual<0x48072050>::Value, Omap3530HwBase::TVirtual<0x48060050>::Value};
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//const TUint KI2C_SBLOCK[KNumUnits] =
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// {Omap3530HwBase::TVirtual<0x48070054>::Value, Omap3530HwBase::TVirtual<0x48072054>::Value, Omap3530HwBase::TVirtual<0x48060054>::Value};
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const TUint KCM_ICLKEN1_CORE = Omap3530HwBase::TVirtual<0x48004A10>::Value;
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const TUint KCM_FCLKEN1_CORE = Omap3530HwBase::TVirtual<0x48004A00>::Value;
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// the Id's used when binding the interrupts
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const TOmap3530_IRQ KIrqId[KNumUnits] = {EOmap3530_IRQ56_I2C1_IRQ, EOmap3530_IRQ57_I2C2_IRQ, EOmap3530_IRQ61_I2C3_IRQ};
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// The three unit control blocks; one for each unit
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TUnitControl gUcb[KNumUnits];
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//TUint prmClientId;
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TUnit RawUnit(THandle aHandle);
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TUnit Unit(THandle aHandle);
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TUnitControl& UnitCb(THandle aHandle);
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TDeviceAddress Device(THandle aHandle);
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TDeviceControl& DeviceCb(THandle aHandle);
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THandle Handle(TUnit aUnit, TDeviceAddress aDeviceAddress);
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void Complete(TUnitControl& aUnit, TInt aResult);
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void Configure(TUnit); // reset and configure an I2C unit
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void Deconfigure(TUnit);
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void TheIsr(void*);
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void TheDfc(TAny* aUnit);
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EXPORT_C TConfigPb::TConfigPb() :
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iUnit((TUnit)-1), // ensure that an un-initialised cpb will return KErrArgument from Open()
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iExclusiveClient(0),
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iDeviceAddress(1)
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{}
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EXPORT_C TTransferPb::TTransferPb() :
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iNextPhase(0)
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{}
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EXPORT_C THandle Open(const TConfigPb& aConfig)
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{
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//TInt r = PowerResourceManager::RegisterClient( prmClientId, KDfcName );
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//__NK_ASSERT_ALWAYS(r==KErrNone);
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THandle h;
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__NK_ASSERT_ALWAYS(aConfig.iVersion == I2C_VERSION);
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if (aConfig.iUnit >= E1 && aConfig.iUnit <= E3)
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{
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TUnitControl& unit = gUcb[aConfig.iUnit];
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Kern::MutexWait( *unit.iOpenMutex );
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if (unit.iNumDevices == 0)
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{
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if (aConfig.iRole == EMaster &&
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aConfig.iMode == E7Bit &&
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aConfig.iRate >= E100K && aConfig.iRate <= E400K)
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{
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unit.iRole = aConfig.iRole;
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unit.iMode = aConfig.iMode;
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unit.iExclusiveClient = aConfig.iExclusiveClient;
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unit.iRate = aConfig.iRate;
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unit.iDevice[unit.iNumDevices].iAddress = aConfig.iDeviceAddress;
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unit.iDevice[unit.iNumDevices++].iDfcQueue = aConfig.iDfcQueue;
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h = Handle(aConfig.iUnit, aConfig.iDeviceAddress);
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Configure(aConfig.iUnit);
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TInt r = Interrupt::Bind(KIrqId[aConfig.iUnit], TheIsr, (void*) aConfig.iUnit);
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__NK_ASSERT_DEBUG(r == KErrNone);
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}
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else
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{
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h = KErrArgument;
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}
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}
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else // unit is already open
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{
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if (unit.iNumDevices < KMaxDevicesPerUnit)
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{
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if (unit.iRole == aConfig.iRole &&
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unit.iMode == aConfig.iMode &&
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unit.iExclusiveClient == aConfig.iExclusiveClient &&
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unit.iRate == aConfig.iRate)
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{
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h = 0;
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for (TInt i = 0; i < unit.iNumDevices; i++)
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{
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if (unit.iDevice[i].iAddress == aConfig.iDeviceAddress)
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{
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h = KErrInUse;
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break;
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}
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}
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if (h == 0)
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{
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unit.iDevice[unit.iNumDevices].iAddress = aConfig.iDeviceAddress;
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unit.iDevice[unit.iNumDevices++].iDfcQueue = aConfig.iDfcQueue;
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h = Handle(aConfig.iUnit, aConfig.iDeviceAddress);
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}
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}
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else
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{
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h = KErrInUse;
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}
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}
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else
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{
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h = KErrTooBig;
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}
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}
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Kern::MutexSignal( *unit.iOpenMutex );
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}
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else
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{
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h = KErrArgument;
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}
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return h;
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}
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EXPORT_C void Close(THandle& aHandle)
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{
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TUnit unitI = RawUnit(aHandle);
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if (unitI >= E1 && unitI <= E3)
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{
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TUnitControl& unit = gUcb[unitI];
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Kern::MutexWait( *unit.iOpenMutex );
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TInt i = 0;
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for (; i < unit.iNumDevices; i++)
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{
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if (unit.iDevice[i].iAddress == Device(aHandle))
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{
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unit.iNumDevices--;
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break;
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}
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}
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for (; i < unit.iNumDevices; i++)
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{
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unit.iDevice[i] = unit.iDevice[i + 1];
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}
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if (unit.iNumDevices == 0)
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{
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(void) Interrupt::Unbind(KIrqId[unitI]);
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Deconfigure(TUnit(unitI));
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}
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Kern::MutexSignal( *unit.iOpenMutex );
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}
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aHandle = -1;
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//PowerResourceManager::DeRegisterClient(prmClientId);
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//prmClientId=0;
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}
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void AddToQueue( TUnitControl& aUnit, TDeviceControl& aDcb, TTransferPb& aWcb )
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{
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TInt irq = __SPIN_LOCK_IRQSAVE(aUnit.iLock);
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if (aUnit.iTransferQ == 0)
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{
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__NK_ASSERT_DEBUG(aUnit.iState == TUnitControl::EIdle);
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aUnit.iTransferQ = &aWcb;
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aUnit.iCurrentPhase = &aWcb;
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aUnit.iTransferQTail = &aWcb;
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aUnit.iDfc.SetDfcQ(aDcb.iDfcQueue);
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aUnit.iDfc.Enque();
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}
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else
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{
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__NK_ASSERT_DEBUG(aUnit.iTransferQTail->iNextTransfer == 0);
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aUnit.iTransferQTail->iNextTransfer = &aWcb;
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aUnit.iTransferQTail = &aWcb;
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}
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__SPIN_UNLOCK_IRQRESTORE(unit.iLock, irq);
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}
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|
296 |
|
|
|
297 |
|
|
|
298 |
EXPORT_C TInt TransferS(THandle aHandle, TTransferPb& aWcb)
|
|
|
299 |
{
|
|
|
300 |
__KTRACE_OPT(KI2C, __KTRACE_OPT(KI2C, Kern::Printf("+I2C:TransferS")));
|
|
|
301 |
|
|
|
302 |
CHECK_PRECONDITIONS(MASK_NOT_ISR, "I2c::TransferS");
|
|
|
303 |
|
|
|
304 |
aWcb.iNextTransfer = 0;
|
|
|
305 |
aWcb.iCompletionDfc = 0; // indicate that it is a sync transfer and the FSM needs to Signal the semaphore
|
|
|
306 |
TDeviceControl& dcb = DeviceCb(aHandle);
|
|
|
307 |
aWcb.iDcb = &dcb;
|
|
|
308 |
aWcb.iResult = (TInt)&dcb.iSyncSem; // use the async tranfer result member to store the semaphore // Todo: store ptr to dcb in aWcb
|
|
|
309 |
|
|
|
310 |
NKern::FSSetOwner(&dcb.iSyncSem, 0);
|
|
|
311 |
|
|
|
312 |
TUnitControl& unit = UnitCb(aHandle);
|
|
|
313 |
|
|
|
314 |
AddToQueue( unit, dcb, aWcb );
|
|
|
315 |
|
|
|
316 |
NKern::FSWait(&dcb.iSyncSem);
|
|
|
317 |
|
|
|
318 |
__KTRACE_OPT(KI2C, __KTRACE_OPT(KI2C, Kern::Printf("-I2C:TransferS:%d", aWcb.iResult)));
|
|
|
319 |
|
|
|
320 |
return aWcb.iResult;
|
|
|
321 |
}
|
|
|
322 |
|
|
|
323 |
EXPORT_C void TransferA(THandle aHandle, TTransferPb& aWcb)
|
|
|
324 |
{
|
|
|
325 |
__KTRACE_OPT(KI2C, __KTRACE_OPT(KI2C, Kern::Printf("+I2C:TransferA")));
|
|
|
326 |
|
|
|
327 |
CHECK_PRECONDITIONS(MASK_NOT_ISR, "I2c::TransferA");
|
|
|
328 |
|
|
|
329 |
aWcb.iNextTransfer = 0;
|
|
|
330 |
TDeviceControl& dcb = DeviceCb(aHandle);
|
|
|
331 |
aWcb.iDcb = &dcb;
|
|
|
332 |
TUnitControl& unit = UnitCb(aHandle);
|
|
|
333 |
|
|
|
334 |
AddToQueue( unit, dcb, aWcb );
|
|
|
335 |
|
|
|
336 |
__KTRACE_OPT(KI2C, __KTRACE_OPT(KI2C, Kern::Printf("-I2C:TransferA")));
|
|
|
337 |
}
|
|
|
338 |
|
|
|
339 |
EXPORT_C void CancelATransfer(THandle)
|
|
|
340 |
{
|
|
|
341 |
}
|
|
|
342 |
|
|
|
343 |
inline TBool BitSet(TUint32 aWord, TUint32 aMask)
|
|
|
344 |
{
|
|
|
345 |
return (aWord & aMask) != 0;
|
|
|
346 |
}
|
|
|
347 |
const TUint32 KStatBb = 1 << 12;
|
|
|
348 |
const TUint32 KStatNack = 1 << 1;
|
|
|
349 |
const TUint32 KStatAl = 1 << 0;
|
|
|
350 |
const TUint32 KStatArdy = 1 << 2;
|
|
|
351 |
const TUint32 KStatRdr = 1 << 13;
|
|
|
352 |
const TUint32 KStatRRdy = 1 << 3;
|
|
|
353 |
const TUint32 KStatXdr = 1 << 14;
|
|
|
354 |
const TUint32 KStatXrdy = 1 << 4;
|
|
|
355 |
const TUint32 KStatBf = 1 << 8;
|
|
|
356 |
const TUint32 KStatInterupts = KStatXdr | KStatRdr | KStatBf | KStatXrdy | KStatRRdy | KStatArdy | KStatNack | KStatAl;
|
|
|
357 |
|
|
|
358 |
const TUint32 KConMst = 1 << 10;
|
|
|
359 |
const TUint32 KConI2cEn = 1 << 15;
|
|
|
360 |
const TUint32 KConTrx = 1 << 9;
|
|
|
361 |
const TUint32 KConStp = 1 << 1;
|
|
|
362 |
const TUint32 KConStt = 1 << 0;
|
|
|
363 |
|
|
|
364 |
void TheDfc(TAny* aUnit)
|
|
|
365 |
{
|
|
|
366 |
TUnit unitI = (TUnit)(TInt)aUnit;
|
|
|
367 |
TUnitControl& unit = gUcb[unitI];
|
|
|
368 |
|
|
|
369 |
__KTRACE_OPT(KI2C, __KTRACE_OPT(KI2C, Kern::Printf("I2C:DFC:S%d", unit.iState)) );
|
|
|
370 |
|
|
|
371 |
switch (unit.iState)
|
|
|
372 |
{
|
|
|
373 |
case TUnitControl::EIdle:
|
|
|
374 |
{
|
|
|
375 |
// 18.5.1.1.2
|
|
|
376 |
// 1
|
|
|
377 |
TTransferPb& tpb = *unit.iTransferQ;
|
|
|
378 |
TTransferPb& ppb = *unit.iCurrentPhase;
|
|
|
379 |
|
|
|
380 |
TUint32 con = KConI2cEn | KConMst;
|
|
|
381 |
if (ppb.iType == TTransferPb::EWrite)
|
|
|
382 |
{
|
|
|
383 |
con |= KConTrx;
|
|
|
384 |
}
|
|
|
385 |
AsspRegister::Write16(KI2C_CON[unitI], con);
|
|
|
386 |
// 18.5.1.1.3
|
|
|
387 |
TUint32 sa = AsspRegister::Read16(KI2C_SA[unitI]);
|
|
|
388 |
__KTRACE_OPT(KI2C, Kern::Printf("I2C:SA[%d]: 0x%04x<-0x%04x", unitI, sa, tpb.iDcb->iAddress));
|
|
|
389 |
AsspRegister::Write16(KI2C_SA[unitI], tpb.iDcb->iAddress);
|
|
|
390 |
TUint32 cnt = AsspRegister::Read16(KI2C_CNT[unitI]);
|
|
|
391 |
__KTRACE_OPT(KI2C, Kern::Printf("I2C:CNT[%d]: 0x%04x<-0x%04x", unitI, cnt, ppb.iLength));
|
|
|
392 |
AsspRegister::Write16(KI2C_CNT[unitI], ppb.iLength);
|
|
|
393 |
// 18.5.1.1.4
|
|
|
394 |
if (ppb.iNextPhase == 0) // last phase
|
|
|
395 |
{
|
|
|
396 |
con |= KConStp; // STP
|
|
|
397 |
}
|
|
|
398 |
con |= KConStt; // STT
|
|
|
399 |
if (&tpb == &ppb) // first phase
|
|
|
400 |
{
|
|
|
401 |
TInt im = NKern::DisableAllInterrupts(); // ensure that the transaction is started while the bus is free
|
|
|
402 |
TUint32 stat = AsspRegister::Read16(KI2C_STAT[unitI]);
|
|
|
403 |
__KTRACE_OPT(KI2C, Kern::Printf("I2C:STAT[%d]: 0x%04x", unitI, stat));
|
|
|
404 |
__NK_ASSERT_ALWAYS(!BitSet(stat, KStatBb)); // if multi-master then need a polling state with a timeout
|
|
|
405 |
AsspRegister::Write16(KI2C_CON[unitI], con);
|
|
|
406 |
NKern::RestoreInterrupts(im);
|
|
|
407 |
}
|
|
|
408 |
else // a follow on phase
|
|
|
409 |
{
|
|
|
410 |
AsspRegister::Write16(KI2C_CON[unitI], con);
|
|
|
411 |
}
|
|
|
412 |
__KTRACE_OPT(KI2C, Kern::Printf("I2C:CON[%d]: 0x%04x", unitI, con));
|
|
|
413 |
__KTRACE_OPT(KI2C, Kern::Printf("I2C:..CNT[%d]: 0x%04x", unitI, AsspRegister::Read16(KI2C_CNT[unitI])));
|
|
|
414 |
|
|
|
415 |
if (ppb.iType == TTransferPb::ERead)
|
|
|
416 |
{
|
|
|
417 |
unit.iState = TUnitControl::ERead;
|
|
|
418 |
}
|
|
|
419 |
else
|
|
|
420 |
{
|
|
|
421 |
unit.iState = TUnitControl::EWrite;
|
|
|
422 |
}
|
|
|
423 |
}
|
|
|
424 |
break;
|
|
|
425 |
case TUnitControl::ERead:
|
|
|
426 |
case TUnitControl::EWrite:
|
|
|
427 |
{
|
|
|
428 |
TTransferPb& ppb = *unit.iCurrentPhase;
|
|
|
429 |
TUint32 stat = AsspRegister::Read16(KI2C_STAT[unitI]);
|
|
|
430 |
__KTRACE_OPT(KI2C, Kern::Printf("I2C:STAT[%d]: 0x%04x", unitI, stat));
|
|
|
431 |
do
|
|
|
432 |
{
|
|
|
433 |
if (BitSet(stat, KStatNack))
|
|
|
434 |
{
|
|
|
435 |
__KTRACE_OPT(KI2C, Kern::Printf("I2C:N"));
|
|
|
436 |
Configure(unitI); // reset the whole unit. Need more testing to determine the correct behavior.
|
|
|
437 |
__KTRACE_OPT(KI2C, Kern::Printf("I2C:CON|STAT[%d]: 0x%04x|0x%04x", unitI, AsspRegister::Read16(KI2C_CON[unitI]), AsspRegister::Read16(KI2C_STAT[unitI])));
|
|
|
438 |
Complete(unit, KErrGeneral);
|
|
|
439 |
return;
|
|
|
440 |
}
|
|
|
441 |
if (BitSet(stat, KStatAl))
|
|
|
442 |
{
|
|
|
443 |
__KTRACE_OPT(KI2C, Kern::Printf("I2C:A"));
|
|
|
444 |
AsspRegister::Write16(KI2C_STAT[unitI], KStatAl);
|
|
|
445 |
|
|
|
446 |
if((AsspRegister::Read16(KI2C_CON[unitI]) & (KConMst | KConStp)) == 0)
|
|
|
447 |
{
|
|
|
448 |
AsspRegister::Modify16(KI2C_CON[unitI], KClearNone, KConStp);
|
|
|
449 |
Complete(unit, KErrGeneral);
|
|
|
450 |
return;
|
|
|
451 |
}
|
|
|
452 |
}
|
|
|
453 |
if (BitSet(stat, KStatArdy))
|
|
|
454 |
{
|
|
|
455 |
__KTRACE_OPT(KI2C, Kern::Printf("I2C:Y"));
|
|
|
456 |
AsspRegister::Write16(KI2C_STAT[unitI], KStatArdy);
|
|
|
457 |
|
|
|
458 |
if (ppb.iNextPhase != 0)
|
|
|
459 |
{
|
|
|
460 |
unit.iCurrentPhase = ppb.iNextPhase;
|
|
|
461 |
unit.iState = TUnitControl::EIdle;
|
|
|
462 |
unit.iDfc.Enque();
|
|
|
463 |
return;
|
|
|
464 |
}
|
|
|
465 |
else
|
|
|
466 |
{
|
|
|
467 |
Complete(unit, KErrNone);
|
|
|
468 |
return;
|
|
|
469 |
}
|
|
|
470 |
}
|
|
|
471 |
if (BitSet(stat, KStatRdr))
|
|
|
472 |
{
|
|
|
473 |
__NK_ASSERT_DEBUG(unit.iState == TUnitControl::ERead);
|
|
|
474 |
TUint32 rxstat = AsspRegister::Read16(KI2C_BUFSTAT[unitI]) >> 8;
|
|
|
475 |
rxstat &= 0x3f;
|
|
|
476 |
__KTRACE_OPT(KI2C, Kern::Printf("I2C:R%d", rxstat));
|
|
|
477 |
for (TUint i = 0; i < rxstat; i++)
|
|
|
478 |
{
|
|
|
479 |
TUint8* d = const_cast<TUint8*>(ppb.iData++);
|
|
|
480 |
*d = (TUint8) AsspRegister::Read16(KI2C_DATA[unitI]);
|
|
|
481 |
}
|
|
|
482 |
AsspRegister::Write16(KI2C_STAT[unitI], KStatRdr);
|
|
|
483 |
}
|
|
|
484 |
else if (BitSet(stat, KStatRRdy))
|
|
|
485 |
{
|
|
|
486 |
__KTRACE_OPT(KI2C, Kern::Printf("I2C:..BUF:%x BUFSTAT:%x", AsspRegister::Read16(KI2C_BUF[unitI]), AsspRegister::Read16(KI2C_BUFSTAT[unitI])));
|
|
|
487 |
__NK_ASSERT_DEBUG(unit.iState == TUnitControl::ERead);
|
|
|
488 |
TUint32 rtrsh = AsspRegister::Read16(KI2C_BUF[unitI]) >> 8;
|
|
|
489 |
rtrsh &= 0x3f;
|
|
|
490 |
__KTRACE_OPT(KI2C, Kern::Printf("I2C:RD%d", rtrsh + 1));
|
|
|
491 |
for (TUint i = 0; i < rtrsh + 1; i++)
|
|
|
492 |
{
|
|
|
493 |
TUint8* d = const_cast<TUint8*>(ppb.iData++);
|
|
|
494 |
*d = (TUint8) AsspRegister::Read16(KI2C_DATA[unitI]);
|
|
|
495 |
}
|
|
|
496 |
AsspRegister::Write16(KI2C_STAT[unitI], KStatRRdy);
|
|
|
497 |
}
|
|
|
498 |
if (BitSet(stat, KStatXdr))
|
|
|
499 |
{
|
|
|
500 |
__NK_ASSERT_DEBUG(unit.iState == TUnitControl::EWrite);
|
|
|
501 |
TUint32 txstat = AsspRegister::Read16(KI2C_BUFSTAT[unitI]);
|
|
|
502 |
txstat &= 0x3f;
|
|
|
503 |
__KTRACE_OPT(KI2C, Kern::Printf("I2C:W%d", txstat));
|
|
|
504 |
for (TUint i = 0; i < txstat; i++)
|
|
|
505 |
{
|
|
|
506 |
AsspRegister::Write16(KI2C_DATA[unitI], *ppb.iData++);
|
|
|
507 |
}
|
|
|
508 |
AsspRegister::Write16(KI2C_STAT[unitI], KStatXdr);
|
|
|
509 |
}
|
|
|
510 |
else if (BitSet(stat, KStatXrdy))
|
|
|
511 |
{
|
|
|
512 |
__NK_ASSERT_DEBUG(unit.iState == TUnitControl::EWrite);
|
|
|
513 |
TUint32 xtrsh = AsspRegister::Read16(KI2C_BUF[unitI]);
|
|
|
514 |
xtrsh &= 0x3f;
|
|
|
515 |
__KTRACE_OPT(KI2C, Kern::Printf("I2C:WD%d", xtrsh + 1));
|
|
|
516 |
for (TUint i = 0; i < xtrsh + 1; i++)
|
|
|
517 |
{
|
|
|
518 |
AsspRegister::Write16(KI2C_DATA[unitI], *ppb.iData++);
|
|
|
519 |
}
|
|
|
520 |
AsspRegister::Write16(KI2C_STAT[unitI], KStatXrdy);
|
|
|
521 |
}
|
|
|
522 |
/* if (stat == KStatBf)
|
|
|
523 |
{
|
|
|
524 |
__KTRACE_OPT(KI2C, Kern::Printf("F"));
|
|
|
525 |
__NK_ASSERT_ALWAYS(ppb.iNextPhase == 0);
|
|
|
526 |
AsspRegister::Write16(KI2C_STAT[unitI], KStatBf);
|
|
|
527 |
Complete(unit, KErrNone);
|
|
|
528 |
return;
|
|
|
529 |
}
|
|
|
530 |
*/ stat = AsspRegister::Read16(KI2C_STAT[unitI]);
|
|
|
531 |
__KTRACE_OPT(KI2C, Kern::Printf("I2C:STAT[%d]: 0x%04x", unitI, stat));
|
|
|
532 |
} while (BitSet(stat, KStatInterupts));
|
|
|
533 |
}
|
|
|
534 |
break;
|
|
|
535 |
}
|
|
|
536 |
Interrupt::Enable(KIrqId[unitI]);
|
|
|
537 |
}
|
|
|
538 |
|
|
|
539 |
TUnitControl::TUnitControl() :
|
|
|
540 |
iLock(/*TSpinLock::EOrderGenericIrqLow1*/),
|
|
|
541 |
iDfc(TheDfc, 0, 1),
|
|
|
542 |
iNumDevices(0),
|
|
|
543 |
iTransferQ(0)
|
|
|
544 |
{
|
|
|
545 |
iDfc.iPtr = (void*)(this - gUcb); // unit index
|
|
|
546 |
__ASSERT_ALWAYS( Kern::MutexCreate( iOpenMutex, KNullDesC, KMutexOrdGeneral0 ) == KErrNone, Kern::Fault( "I2C", __LINE__ ) );
|
|
|
547 |
}
|
|
|
548 |
|
|
|
549 |
void TheIsr(void* aUnit)
|
|
|
550 |
{
|
|
|
551 |
TUnit unitI = (TUnit)(TInt)aUnit;
|
|
|
552 |
Interrupt::Disable(KIrqId[unitI]);
|
|
|
553 |
|
|
|
554 |
TUnitControl& unit = gUcb[unitI];
|
|
|
555 |
__KTRACE_OPT(KI2C, __KTRACE_OPT(KI2C, Kern::Printf("=I2C:DFC:u%x", &unit )));
|
|
|
556 |
unit.iDfc.Add();
|
|
|
557 |
}
|
|
|
558 |
|
|
|
559 |
void Configure(TUnit aUnitI)
|
|
|
560 |
{
|
|
|
561 |
__ASSERT_NO_FAST_MUTEX;
|
|
|
562 |
__NK_ASSERT_ALWAYS(aUnitI<3);
|
|
|
563 |
// 18.5.1.1.1
|
|
|
564 |
// 1
|
|
|
565 |
//TInt r = PowerResourceManager::ChangeResourceState( prmClientId, Omap3530Prm::EPrmClkI2c1_F+aUnitI, Prcm::EClkOn );
|
|
|
566 |
//r = PowerResourceManager::ChangeResourceState( prmClientId, Omap3530Prm::EPrmClkI2c1_I+aUnitI, Prcm::EClkOn );
|
|
|
567 |
TUint32 iClkEn = AsspRegister::Read16(KCM_ICLKEN1_CORE);
|
|
|
568 |
TUint32 fClkEn = AsspRegister::Read16(KCM_FCLKEN1_CORE);
|
|
|
569 |
__KTRACE_OPT(KI2C, Kern::Printf("I2C:CM_I|FCLKEN1[%d]: 0x%04x|0x%04x", aUnitI, iClkEn, fClkEn));
|
|
|
570 |
AsspRegister::Modify32(KCM_ICLKEN1_CORE, 0, 1 << 15 + aUnitI);
|
|
|
571 |
AsspRegister::Modify32(KCM_FCLKEN1_CORE, 0, 1 << 15 + aUnitI);
|
|
|
572 |
// Reset
|
|
|
573 |
AsspRegister::Write16(KI2C_SYSC[aUnitI], 0x0002);
|
|
|
574 |
|
|
|
575 |
if (gUcb[aUnitI].iRate == E100K)
|
|
|
576 |
{
|
|
|
577 |
// 2
|
|
|
578 |
AsspRegister::Write16(KI2C_PSC[aUnitI], 23);
|
|
|
579 |
// 3 + 4
|
|
|
580 |
AsspRegister::Write16(KI2C_SCLL[aUnitI], 0x000d); // 100kHz F/S, 400kHz HS
|
|
|
581 |
AsspRegister::Write16(KI2C_SCLH[aUnitI], 0x000f);
|
|
|
582 |
}
|
|
|
583 |
else if (gUcb[aUnitI].iRate == E400K)
|
|
|
584 |
{
|
|
|
585 |
// 2
|
|
|
586 |
AsspRegister::Write16(KI2C_PSC[aUnitI], 9);
|
|
|
587 |
// 3 + 4
|
|
|
588 |
AsspRegister::Write16(KI2C_SCLL[aUnitI], 0x0005); // 400kHz F/S, 400kHz HS
|
|
|
589 |
AsspRegister::Write16(KI2C_SCLH[aUnitI], 0x0007);
|
|
|
590 |
}
|
|
|
591 |
// 6
|
|
|
592 |
AsspRegister::Write16(KI2C_OA1[aUnitI], gUcb[aUnitI].iOwnAddress);
|
|
|
593 |
// 7
|
|
|
594 |
TUint32 buf = AsspRegister::Read16(KI2C_BUF[aUnitI]);
|
|
|
595 |
__KTRACE_OPT(KI2C, Kern::Printf("I2C:I2C_BUF[%d]: 0x%04x", aUnitI, buf));
|
|
|
596 |
// 8
|
|
|
597 |
TUint32 con = AsspRegister::Read16(KI2C_CON[aUnitI]);
|
|
|
598 |
__KTRACE_OPT(KI2C, Kern::Printf("I2C:I2C_CON[%d]: 0x%04x<-0x%04x", aUnitI, con, con | 1 << 15));
|
|
|
599 |
AsspRegister::Modify16(KI2C_CON[aUnitI], 0, 1 << 15);
|
|
|
600 |
|
|
|
601 |
TUint32 syss = AsspRegister::Read16(KI2C_SYSS[aUnitI]);
|
|
|
602 |
__NK_ASSERT_DEBUG(syss == 0x1);
|
|
|
603 |
|
|
|
604 |
// set-up interrupts
|
|
|
605 |
TUint32 ie = AsspRegister::Read16(KI2C_IE[aUnitI]);
|
|
|
606 |
__KTRACE_OPT(KI2C, Kern::Printf("I2C:IE[%d]: 0x%04x<-0x%04x", aUnitI, ie, KStatInterupts));
|
|
|
607 |
AsspRegister::Write16(KI2C_IE[aUnitI], KStatInterupts);
|
|
|
608 |
}
|
|
|
609 |
|
|
|
610 |
void Deconfigure(TUnit aUnitI)
|
|
|
611 |
{
|
|
|
612 |
__ASSERT_NO_FAST_MUTEX;
|
|
|
613 |
__NK_ASSERT_ALWAYS(aUnitI<3);
|
|
|
614 |
//TInt r = PowerResourceManager::ChangeResourceState( prmClientId, Omap3530Prm::EPrmClkI2c1_F+aUnitI, Prcm::EClkOff );
|
|
|
615 |
//__KTRACE_OPT(KBOOT, Kern::Printf("EPrmClkI2c%d_F DIS %d", aUnitI, r));
|
|
|
616 |
//r = PowerResourceManager::ChangeResourceState( prmClientId, Omap3530Prm::EPrmClkI2c1_I+aUnitI, Prcm::EClkOff );
|
|
|
617 |
//__KTRACE_OPT(KBOOT, Kern::Printf("EPrmClkI2c%d_I DIS %d", aUnitI, r));
|
|
|
618 |
AsspRegister::Modify32(KCM_ICLKEN1_CORE, 1 << 15 + aUnitI, 0);
|
|
|
619 |
AsspRegister::Modify32(KCM_FCLKEN1_CORE, 1 << 15 + aUnitI, 0);
|
|
|
620 |
}
|
|
|
621 |
|
|
|
622 |
THandle Handle(TUnit aUnit, TDeviceAddress aDeviceAddress)
|
|
|
623 |
{
|
|
|
624 |
return THandle(aUnit << 16 | aDeviceAddress);
|
|
|
625 |
}
|
|
|
626 |
|
|
|
627 |
TUnit RawUnit(THandle aHandle)
|
|
|
628 |
{
|
|
|
629 |
TUnit r = TUnit(aHandle >> 16);
|
|
|
630 |
return r;
|
|
|
631 |
}
|
|
|
632 |
|
|
|
633 |
TUnit Unit(THandle aHandle)
|
|
|
634 |
{
|
|
|
635 |
TUnit r = RawUnit(aHandle);
|
|
|
636 |
if (r < E1 || r > E3)
|
|
|
637 |
{
|
|
|
638 |
__KTRACE_OPT(KI2C, Kern::Printf("I2C Unit out of range: %d", r));
|
|
|
639 |
r = E1;
|
|
|
640 |
}
|
|
|
641 |
return r;
|
|
|
642 |
}
|
|
|
643 |
|
|
|
644 |
TUnitControl& UnitCb(THandle aHandle)
|
|
|
645 |
{
|
|
|
646 |
return gUcb[Unit(aHandle)];
|
|
|
647 |
}
|
|
|
648 |
|
|
|
649 |
TDeviceAddress Device(THandle aHandle)
|
|
|
650 |
{
|
|
|
651 |
TDeviceAddress r = TDeviceAddress(aHandle & 0x0000ffff);
|
|
|
652 |
if (r < 0 || r > 1023)
|
|
|
653 |
{
|
|
|
654 |
__KTRACE_OPT(KI2C, Kern::Printf("I2C Device out of range: %d", r));
|
|
|
655 |
}
|
|
|
656 |
return r;
|
|
|
657 |
}
|
|
|
658 |
|
|
|
659 |
TDeviceControl& DeviceCb(THandle aHandle)
|
|
|
660 |
{
|
|
|
661 |
TUnitControl& unit = UnitCb(aHandle);
|
|
|
662 |
TDeviceAddress device = Device(aHandle);
|
|
|
663 |
TInt i = 0;
|
|
|
664 |
for (; i < unit.iNumDevices; i++)
|
|
|
665 |
{
|
|
|
666 |
if (unit.iDevice[i].iAddress == device)
|
|
|
667 |
{
|
|
|
668 |
break;
|
|
|
669 |
}
|
|
|
670 |
}
|
|
|
671 |
return unit.iDevice[i];
|
|
|
672 |
}
|
|
|
673 |
|
|
|
674 |
void Complete(TUnitControl& aUnit, TInt aResult)
|
|
|
675 |
{
|
|
|
676 |
aUnit.iTransferQ->iResult = aResult;
|
|
|
677 |
aUnit.iState = TUnitControl::EIdle;
|
|
|
678 |
|
|
|
679 |
TInt irq = __SPIN_LOCK_IRQSAVE(aUnit.iLock);
|
|
|
680 |
TTransferPb& tpb = *aUnit.iTransferQ;
|
|
|
681 |
aUnit.iTransferQ = aUnit.iTransferQ->iNextTransfer;
|
|
|
682 |
__SPIN_UNLOCK_IRQRESTORE(aUnit.iLock, irq);
|
|
|
683 |
|
|
|
684 |
if (tpb.iCompletionDfc == 0)
|
|
|
685 |
{
|
|
|
686 |
NKern::FSSignal(&tpb.iDcb->iSyncSem);
|
|
|
687 |
}
|
|
|
688 |
else
|
|
|
689 |
{
|
|
|
690 |
tpb.iCompletionDfc->Enque();
|
|
|
691 |
}
|
|
|
692 |
}
|
|
|
693 |
|
|
|
694 |
} // namespace I2c
|
|
|
695 |
|
|
|
696 |
namespace I2cReg
|
|
|
697 |
{
|
|
|
698 |
EXPORT_C TUint8 ReadB(I2c::THandle aH, TUint8 aAddr)
|
|
|
699 |
{
|
|
|
700 |
const TUint8 KAddress = aAddr;
|
|
|
701 |
I2c::TTransferPb addressPhase;
|
|
|
702 |
addressPhase.iType = I2c::TTransferPb::EWrite;
|
|
|
703 |
addressPhase.iLength = 1;
|
|
|
704 |
addressPhase.iData = &KAddress;
|
|
|
705 |
|
|
|
706 |
TUint8 readData;
|
|
|
707 |
I2c::TTransferPb dataPhase;
|
|
|
708 |
dataPhase.iType = I2c::TTransferPb::ERead;
|
|
|
709 |
dataPhase.iLength = 1;
|
|
|
710 |
dataPhase.iData = &readData;
|
|
|
711 |
|
|
|
712 |
addressPhase.iNextPhase = &dataPhase; // link into a two phase transfer
|
|
|
713 |
|
|
|
714 |
TInt r = KErrNone;
|
|
|
715 |
TInt retryCount = 0;
|
|
|
716 |
|
|
|
717 |
do
|
|
|
718 |
{
|
|
|
719 |
r=I2c::TransferS(aH, addressPhase);
|
|
|
720 |
retryCount++;
|
|
|
721 |
}
|
|
|
722 |
while (r != KErrNone && retryCount < 5);
|
|
|
723 |
|
|
|
724 |
__NK_ASSERT_ALWAYS(r == KErrNone);
|
|
|
725 |
|
|
|
726 |
return readData;
|
|
|
727 |
}
|
|
|
728 |
|
|
|
729 |
EXPORT_C void WriteB(I2c::THandle aH, TUint8 aAddr, TUint8 aData)
|
|
|
730 |
{
|
|
|
731 |
const TUint8 KAddrData[2] = {aAddr, aData};
|
|
|
732 |
I2c::TTransferPb fullTransfer;
|
|
|
733 |
fullTransfer.iType = I2c::TTransferPb::EWrite;
|
|
|
734 |
fullTransfer.iLength = 2;
|
|
|
735 |
fullTransfer.iData = KAddrData;
|
|
|
736 |
|
|
|
737 |
TInt r = KErrNone;
|
|
|
738 |
TInt retryCount = 0;
|
|
|
739 |
|
|
|
740 |
do
|
|
|
741 |
{
|
|
|
742 |
r=I2c::TransferS(aH, fullTransfer);
|
|
|
743 |
retryCount++;
|
|
|
744 |
}
|
|
|
745 |
while (r != KErrNone && retryCount < 5);
|
|
|
746 |
|
|
|
747 |
__NK_ASSERT_ALWAYS(r == KErrNone);
|
|
|
748 |
}
|
|
|
749 |
} // namespace I2cReg
|